coreboot-gerrit April 2018

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Change in coreboot[master]: opencellular/supabrckv1: Add LPC TPM to devicetree
by Philipp Deppenwiese (Code Review) 18 Apr '18

18 Apr '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/25705 Change subject: opencellular/supabrckv1: Add LPC TPM to devicetree ...................................................................... opencellular/supabrckv1: Add LPC TPM to devicetree Change-Id: I2ec0fca97f4581a1da35d424ace0526017a8e651 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/25705/1 diff --git a/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb b/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb index 25405e6..15bce45 100644 --- a/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb +++ b/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb @@ -75,7 +75,11 @@ device pci 1e.3 on end # 8086 0F0A - HSUART 1 device pci 1e.4 off end # 8086 0F0C - HSUART 2 device pci 1e.5 off end # 8086 0F0E - SPI - device pci 1f.0 on end # 8086 0F1C - LPC bridge + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # 8086 0F1C - LPC bridge device pci 1f.3 on end # 8086 0F12 - SMBus 0 end end -- To view, visit https://review.coreboot.org/25705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2ec0fca97f4581a1da35d424ace0526017a8e651 Gerrit-Change-Number: 25705 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: soc/intel/cannonlake: Set DISB after Dram init
by build bot (Jenkins) (Code Review) 18 Apr '18

18 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25704 ) Change subject: soc/intel/cannonlake: Set DISB after Dram init ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70251/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/24471/ : SUCCESS -- To view, visit https://review.coreboot.org/25704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I16dd3787cb743bc5b7492042f3c3757534e1a51c Gerrit-Change-Number: 25704 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Apr 2018 23:42:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Set DISB after Dram init
by Lijian Zhao (Code Review) 18 Apr '18

18 Apr '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/25704 Change subject: soc/intel/cannonlake: Set DISB after Dram init ...................................................................... soc/intel/cannonlake: Set DISB after Dram init DRAM Initialization Scratchpad Bit need to be set after Dram Initialization finished. BUG=None Change-Id: I16dd3787cb743bc5b7492042f3c3757534e1a51c Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/cannonlake/romstage/romstage.c 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/25704/1 diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index a5d1833..3749b1c 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -128,6 +128,19 @@ return gpe_sts_bits; } +void pmc_set_disb(void) +{ + /* Set the DISB after DRAM init */ + uint8_t disb_val; + + disb_val = read8(pmc_mmio_regs() + GEN_PMCON_A + 2); + disb_val |= DISB; + + /* Don't clear bits that are write-1-to-clear */ + disb_val &= ~(MS4V | SUS_PWR_FLR); + write8((pmc_mmio_regs() + GEN_PMCON_A + 2), disb_val); +} + /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index dc96526..c8cb927 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -123,6 +123,7 @@ timestamp_add_now(TS_START_ROMSTAGE); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); + pmc_set_disb(); if (!s3wake) save_dimm_info(); if (postcar_frame_init(&pcf, 1 * KiB)) -- To view, visit https://review.coreboot.org/25704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I16dd3787cb743bc5b7492042f3c3757534e1a51c Gerrit-Change-Number: 25704 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: mb/google/cyan/spd/spd.c: Fix module part number transfer
by build bot (Jenkins) (Code Review) 18 Apr '18

18 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25702 ) Change subject: mb/google/cyan/spd/spd.c: Fix module part number transfer ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70250/ : SUCCESS -- To view, visit https://review.coreboot.org/25702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iba0ef4149acfc09b7672fce079df06bf1a01dff6 Gerrit-Change-Number: 25702 Gerrit-PatchSet: 6 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Apr 2018 23:21:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/cyan/spd/spd.c: Fix module part number transfer
by build bot (Jenkins) (Code Review) 18 Apr '18

18 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25702 ) Change subject: mb/google/cyan/spd/spd.c: Fix module part number transfer ...................................................................... Patch Set 5: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/70249/ : ABORTED -- To view, visit https://review.coreboot.org/25702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iba0ef4149acfc09b7672fce079df06bf1a01dff6 Gerrit-Change-Number: 25702 Gerrit-PatchSet: 5 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Apr 2018 23:17:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/common/block/pi/heapmanager.c: Simplify code
by build bot (Jenkins) (Code Review) 18 Apr '18

18 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25703 ) Change subject: soc/amd/common/block/pi/heapmanager.c: Simplify code ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70248/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/24470/ : SUCCESS -- To view, visit https://review.coreboot.org/25703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib4c69981eab7452228ccae9ed9bc288c8baceffe Gerrit-Change-Number: 25703 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Apr 2018 21:29:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/common/block/pi/heapmanager.c: Simplify code
by Richard Spiegel (Code Review) 18 Apr '18

18 Apr '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/25703 Change subject: soc/amd/common/block/pi/heapmanager.c: Simplify code ...................................................................... soc/amd/common/block/pi/heapmanager.c: Simplify code There are sections of code that are almost identical and they can be converted to auxiliary procedures. For allocating heap, 3 sizes are used often so they could be stored in temporary variables. These 2 changes will make code shorter, with less indentation problems and overall easier to read. The actual logic of the code is not changed. BUG=b:77940747 TEST=Build and boot grunt. Change-Id: Ib4c69981eab7452228ccae9ed9bc288c8baceffe Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/common/block/pi/heapmanager.c 1 file changed, 79 insertions(+), 86 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/25703/1 diff --git a/src/soc/amd/common/block/pi/heapmanager.c b/src/soc/amd/common/block/pi/heapmanager.c index a469a45..aa3a40d 100644 --- a/src/soc/amd/common/block/pi/heapmanager.c +++ b/src/soc/amd/common/block/pi/heapmanager.c @@ -30,6 +30,44 @@ memset(BiosManagerPtr, 0, BIOS_HEAP_SIZE); } +static AGESA_STATUS FindNode(uint32_t handle, BIOS_BUFFER_NODE **pointer) +{ + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_STATUS Status = AGESA_SUCCESS; + + BiosHeapBaseAddr = agesa_heap_base(); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *)BiosHeapBaseAddr; + + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + AllocNodeOffset); + + while (handle != AllocNodePtr->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + Status = AGESA_BOUNDS_CHK; + break; + } + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + + AllocNodeOffset); + } + *pointer = AllocNodePtr; + return Status; +} + +static void ConcatenateNodes(BIOS_BUFFER_NODE *FirstNodePtr, + BIOS_BUFFER_NODE *SecondNodePtr) +{ + FirstNodePtr->BufferSize += SecondNodePtr->BufferSize + + sizeof(BIOS_BUFFER_NODE); + FirstNodePtr->NextNodeOffset = SecondNodePtr->NextNodeOffset; + + /* Zero out the SecondNode header */ + memset((UINT8 *)SecondNodePtr, 0, sizeof(BIOS_BUFFER_NODE)); +} + #if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) #error "Only EARLY_CBMEM_INIT is supported." #endif @@ -42,9 +80,12 @@ UINT32 CurrNodeOffset; UINT32 PrevNodeOffset; UINT32 FreedNodeOffset; + UINT32 FreedNodeSize; UINT32 BestFitNodeOffset; + UINT32 BestFitNodeSize; UINT32 BestFitPrevNodeOffset; UINT32 NextFreeOffset; + UINT32 MinimumSize; BIOS_BUFFER_NODE *CurrNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; BIOS_BUFFER_NODE *BestFitNodePtr; @@ -52,11 +93,14 @@ BIOS_BUFFER_NODE *NextFreePtr; BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; + AGESA_STATUS Status; AllocParams = ((AGESA_BUFFER_PARAMS *)ConfigPtr); AllocParams->BufferPointer = NULL; + MinimumSize = AllocParams->BufferLength + sizeof(BIOS_BUFFER_NODE); AvailableHeapSize = BIOS_HEAP_SIZE - sizeof(BIOS_HEAP_MANAGER); + BestFitNodeSize = AvailableHeapSize; /* init with largest possible */ BiosHeapBaseAddr = agesa_heap_base(); BiosHeapBasePtr = (BIOS_HEAP_MANAGER *)BiosHeapBaseAddr; @@ -85,37 +129,29 @@ BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset; BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset; } else { - /* Find out whether BufferHandle has been allocated on the heap. + /* + * Find out whether BufferHandle has been allocated on the heap. * If it has, return AGESA_BOUNDS_CHK. */ - CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; - CurrNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr - + CurrNodeOffset); + Status = FindNode(AllocParams->BufferHandle, &CurrNodePtr); + if (Status == AGESA_SUCCESS) + return AGESA_BOUNDS_CHK; - while (CurrNodeOffset != 0) { - CurrNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr - + CurrNodeOffset); - if (CurrNodePtr->BufferHandle == - AllocParams->BufferHandle) { - return AGESA_BOUNDS_CHK; - } - CurrNodeOffset = CurrNodePtr->NextNodeOffset; - /* If BufferHandle has not been allocated on the heap, - * CurrNodePtr here points to the end of the allocated - * nodes list. - */ - } + /* + * If status ditn't returned AGESA_SUCCESS, CurrNodePtr here + * points to the end of the allocated nodes list. + */ + /* Find the node that best fits the requested buffer size */ FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; PrevNodeOffset = FreedNodeOffset; BestFitNodeOffset = 0; BestFitPrevNodeOffset = 0; - while (FreedNodeOffset != 0) { /* todo: simplify this */ + while (FreedNodeOffset != 0) { FreedNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + FreedNodeOffset); - if (FreedNodePtr->BufferSize >= - (AllocParams->BufferLength + - sizeof(BIOS_BUFFER_NODE))) { + FreedNodeSize = FreedNodePtr->BufferSize; + if (FreedNodeSize >= MinimumSize) { if (BestFitNodeOffset == 0) { /* * First node that fits the requested @@ -123,21 +159,19 @@ */ BestFitNodeOffset = FreedNodeOffset; BestFitPrevNodeOffset = PrevNodeOffset; + BestFitNodeSize = FreedNodeSize; } else { /* * Find out whether current node is a * betterfit than the previous nodes */ - BestFitNodePtr = (BIOS_BUFFER_NODE *) - (BiosHeapBaseAddr + - BestFitNodeOffset); - if (BestFitNodePtr->BufferSize > - FreedNodePtr->BufferSize) { + if (BestFitNodeSize > FreedNodeSize) { BestFitNodeOffset = FreedNodeOffset; BestFitPrevNodeOffset = PrevNodeOffset; + BestFitNodeSize = FreedNodeSize; } } } @@ -162,22 +196,19 @@ * If BestFitNode is larger than the requested buffer, * fragment the node further */ - if (BestFitNodePtr->BufferSize > - (AllocParams->BufferLength + sizeof(BIOS_BUFFER_NODE))) { - NextFreeOffset = BestFitNodeOffset + - AllocParams->BufferLength + - sizeof(BIOS_BUFFER_NODE); + if (BestFitNodePtr->BufferSize > MinimumSize) { + NextFreeOffset = BestFitNodeOffset + MinimumSize; NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); - NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - - (AllocParams->BufferLength + - sizeof(BIOS_BUFFER_NODE)); + NextFreePtr->BufferSize = BestFitNodeSize - MinimumSize; + + /* Remove BestFitNode from list of Freed nodes */ NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; } else { /* - * Otherwise, next free node is - * NextNodeOffset of BestFitNode + * Otherwise, next free node is NextNodeOffset of + * BestFitNode. Remove it from list of Freed nodes. */ NextFreeOffset = BestFitNodePtr->NextNodeOffset; } @@ -197,7 +228,6 @@ BestFitNodePtr->BufferHandle = AllocParams->BufferHandle; BestFitNodePtr->NextNodeOffset = 0; - /* Remove BestFitNode from list of Freed nodes */ AllocParams->BufferPointer = (UINT8 *)BestFitNodePtr + sizeof(BIOS_BUFFER_NODE); } @@ -264,14 +294,7 @@ /* If the freed node is adjacent to the first node in * the list, concatenate both nodes */ - AllocNodePtr->BufferSize += FreedNodePtr->BufferSize + - sizeof(BIOS_BUFFER_NODE); - AllocNodePtr->NextNodeOffset = - FreedNodePtr->NextNodeOffset; - - /* Zero out the FreedNode header */ - memset((UINT8 *)FreedNodePtr, 0, - sizeof(BIOS_BUFFER_NODE)); + ConcatenateNodes(AllocNodePtr, FreedNodePtr); } else { /* Otherwise, add freed node to the start of the list * Update NextNodeOffset and BufferSize to include the @@ -302,14 +325,7 @@ if (NextNodeOffset == EndNodeOffset) { NextNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + NextNodeOffset); - AllocNodePtr->BufferSize += NextNodePtr->BufferSize + - sizeof(BIOS_BUFFER_NODE); - AllocNodePtr->NextNodeOffset = - NextNodePtr->NextNodeOffset; - - /* Zero out the NextNode header */ - memset((UINT8 *)NextNodePtr, 0, - sizeof(BIOS_BUFFER_NODE)); + ConcatenateNodes(AllocNodePtr, NextNodePtr); } else { /*AllocNodePtr->NextNodeOffset = * FreedNodePtr->NextNodeOffset; */ @@ -324,53 +340,30 @@ EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize + sizeof(BIOS_BUFFER_NODE); - if (AllocNodeOffset == EndNodeOffset) { - PrevNodePtr->NextNodeOffset = - AllocNodePtr->NextNodeOffset; - PrevNodePtr->BufferSize += AllocNodePtr->BufferSize + - sizeof(BIOS_BUFFER_NODE); - - /* Zero out the AllocNode header */ - memset((UINT8 *)AllocNodePtr, 0, - sizeof(BIOS_BUFFER_NODE)); - } else { + if (AllocNodeOffset == EndNodeOffset) + ConcatenateNodes(PrevNodePtr, AllocNodePtr); + else PrevNodePtr->NextNodeOffset = AllocNodeOffset; - } } return AGESA_SUCCESS; } AGESA_STATUS agesa_LocateBuffer (UINT32 Func, UINTN Data, VOID *ConfigPtr) { - UINT32 AllocNodeOffset; - UINT8 *BiosHeapBaseAddr; BIOS_BUFFER_NODE *AllocNodePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; + AGESA_STATUS Status; AllocParams = (AGESA_BUFFER_PARAMS *)ConfigPtr; - BiosHeapBaseAddr = agesa_heap_base(); - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *)BiosHeapBaseAddr; + Status = FindNode(AllocParams->BufferHandle, &AllocNodePtr); - AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; - AllocNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + AllocNodeOffset); - - while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) { - if (AllocNodePtr->NextNodeOffset == 0) { - AllocParams->BufferPointer = NULL; - AllocParams->BufferLength = 0; - return AGESA_BOUNDS_CHK; - } - AllocNodeOffset = AllocNodePtr->NextNodeOffset; - AllocNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + - AllocNodeOffset); + if (Status == AGESA_SUCCESS) { + AllocParams->BufferPointer = (UINT8 *)((UINT8 *)AllocNodePtr + + sizeof(BIOS_BUFFER_NODE)); + AllocParams->BufferLength = AllocNodePtr->BufferSize; } - AllocParams->BufferPointer = (UINT8 *)((UINT8 *)AllocNodePtr - + sizeof(BIOS_BUFFER_NODE)); - AllocParams->BufferLength = AllocNodePtr->BufferSize; - - return AGESA_SUCCESS; + return Status; } -- To view, visit https://review.coreboot.org/25703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib4c69981eab7452228ccae9ed9bc288c8baceffe Gerrit-Change-Number: 25703 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: mb/google/cyan/spd/spd.c: Fix module part number transfer
by build bot (Jenkins) (Code Review) 18 Apr '18

18 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25702 ) Change subject: mb/google/cyan/spd/spd.c: Fix module part number transfer ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70247/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/24469/ : SUCCESS -- To view, visit https://review.coreboot.org/25702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iba0ef4149acfc09b7672fce079df06bf1a01dff6 Gerrit-Change-Number: 25702 Gerrit-PatchSet: 4 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Apr 2018 20:37:58 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/cyan/spd/spd.c: Fix module part number transfer
by build bot (Jenkins) (Code Review) 18 Apr '18

18 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25702 ) Change subject: mb/google/cyan/spd/spd.c: Fix module part number transfer ...................................................................... Patch Set 3: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/70246/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/24468/ : SUCCESS -- To view, visit https://review.coreboot.org/25702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iba0ef4149acfc09b7672fce079df06bf1a01dff6 Gerrit-Change-Number: 25702 Gerrit-PatchSet: 3 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Apr 2018 19:19:58 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/cyan/spd/spd.c: Fix module part number transfer
by build bot (Jenkins) (Code Review) 18 Apr '18

18 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25702 ) Change subject: mb/google/cyan/spd/spd.c: Fix module part number transfer ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/70245/ : ABORTED -- To view, visit https://review.coreboot.org/25702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iba0ef4149acfc09b7672fce079df06bf1a01dff6 Gerrit-Change-Number: 25702 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Apr 2018 19:12:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit April 2018