coreboot-gerrit April 2018

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Change in coreboot[master]: pci: Guard ACPI
by Patrick Rudolph (Code Review) 18 Apr '18

18 Apr '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25722 Change subject: pci: Guard ACPI ...................................................................... pci: Guard ACPI Guard ACPI headers and functions with preprocessor directives. Fixes compilation on non ACPI enabled platforms. Change-Id: Iaff20463375d1e3ec573d9486a859a0514b0b390 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/device/pci_device.c M src/device/pci_rom.c M src/include/device/pci_rom.h 3 files changed, 12 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/25722/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index c18f529..539c2a3 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -30,8 +30,9 @@ /* * PCI Bus Services, see include/linux/pci.h for further explanation. */ - +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) #include <arch/acpi.h> +#endif #include <arch/io.h> #include <bootmode.h> #include <console/console.h> @@ -695,9 +696,11 @@ /* If S3_VGA_ROM_RUN is disabled, skip running VGA option * ROMs when coming out of an S3 resume. */ +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) if (!IS_ENABLED(CONFIG_S3_VGA_ROM_RUN) && acpi_is_wakeup_s3() && ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) return 0; +#endif if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) return 1; if (should_run_oprom(dev)) diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 15b0c4c..d772884 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -26,7 +26,9 @@ #include <string.h> #include <cbfs.h> #include <cbmem.h> +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) #include <arch/acpigen.h> +#endif /* Rmodules don't like weak symbols. */ u32 __attribute__((weak)) map_oprom_vendev(u32 vendev) { return vendev; } diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index a4aa52a..dc9f97b 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -2,7 +2,9 @@ #define PCI_ROM_H #include <endian.h> #include <stddef.h> +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) #include <arch/acpi.h> +#endif #define PCI_ROM_HDR 0xAA55 #define PCI_DATA_HDR ((uint32_t) (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) @@ -38,10 +40,12 @@ struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header); +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) unsigned long pci_rom_write_acpi_tables(struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp); + unsigned long current, + struct acpi_rsdp *rsdp); +#endif void pci_rom_ssdt(struct device *device); -- To view, visit https://review.coreboot.org/25722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iaff20463375d1e3ec573d9486a859a0514b0b390 Gerrit-Change-Number: 25722 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: pci: Move inline function to device/pci.h
by Patrick Rudolph (Code Review) 18 Apr '18

18 Apr '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25720 Change subject: pci: Move inline function to device/pci.h ...................................................................... pci: Move inline function to device/pci.h Move inline function where they belong to. Fixes compilation on non x86. Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/include/arch/io.h M src/include/device/pci.h 2 files changed, 54 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/25720/1 diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index d35e964..37b2e95 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -427,63 +427,4 @@ } #endif /* __SIMPLE_DEVICE__ */ - -#ifndef __SIMPLE_DEVICE__ -#include <device/pci_ops.h> -#endif - -static inline __attribute__((always_inline)) -void pci_or_config8(device_t dev, unsigned int where, u8 ormask) -{ - u8 value = pci_read_config8(dev, where); - pci_write_config8(dev, where, value | ormask); -} - -static inline __attribute__((always_inline)) -void pci_or_config16(device_t dev, unsigned int where, u16 ormask) -{ - u16 value = pci_read_config16(dev, where); - pci_write_config16(dev, where, value | ormask); -} - -static inline __attribute__((always_inline)) -void pci_or_config32(device_t dev, unsigned int where, u32 ormask) -{ - u32 value = pci_read_config32(dev, where); - pci_write_config32(dev, where, value | ormask); -} - -static inline __attribute__((always_inline)) -void pci_update_config8(device_t dev, int reg, u8 mask, u8 or) -{ - u8 reg8; - - reg8 = pci_read_config8(dev, reg); - reg8 &= mask; - reg8 |= or; - pci_write_config8(dev, reg, reg8); -} - -static inline __attribute__((always_inline)) -void pci_update_config16(device_t dev, int reg, u16 mask, u16 or) -{ - u16 reg16; - - reg16 = pci_read_config16(dev, reg); - reg16 &= mask; - reg16 |= or; - pci_write_config16(dev, reg, reg16); -} - -static inline __attribute__((always_inline)) -void pci_update_config32(device_t dev, int reg, u32 mask, u32 or) -{ - u32 reg32; - - reg32 = pci_read_config32(dev, reg); - reg32 &= mask; - reg32 |= or; - pci_write_config32(dev, reg, reg32); -} - #endif diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 5eb6a4a..284ad69 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -136,6 +136,60 @@ } #endif +static inline __attribute__((always_inline)) +void pci_or_config8(device_t dev, unsigned int where, u8 ormask) +{ + u8 value = pci_read_config8(dev, where); + pci_write_config8(dev, where, value | ormask); +} + +static inline __attribute__((always_inline)) +void pci_or_config16(device_t dev, unsigned int where, u16 ormask) +{ + u16 value = pci_read_config16(dev, where); + pci_write_config16(dev, where, value | ormask); +} + +static inline __attribute__((always_inline)) +void pci_or_config32(device_t dev, unsigned int where, u32 ormask) +{ + u32 value = pci_read_config32(dev, where); + pci_write_config32(dev, where, value | ormask); +} + +static inline __attribute__((always_inline)) +void pci_update_config8(device_t dev, int reg, u8 mask, u8 or) +{ + u8 reg8; + + reg8 = pci_read_config8(dev, reg); + reg8 &= mask; + reg8 |= or; + pci_write_config8(dev, reg, reg8); +} + +static inline __attribute__((always_inline)) +void pci_update_config16(device_t dev, int reg, u16 mask, u16 or) +{ + u16 reg16; + + reg16 = pci_read_config16(dev, reg); + reg16 &= mask; + reg16 |= or; + pci_write_config16(dev, reg, reg16); +} + +static inline __attribute__((always_inline)) +void pci_update_config32(device_t dev, int reg, u32 mask, u32 or) +{ + u32 reg32; + + reg32 = pci_read_config32(dev, reg); + reg32 &= mask; + reg32 |= or; + pci_write_config32(dev, reg, reg32); +} + #endif /* CONFIG_PCI */ #endif /* PCI_H */ -- To view, visit https://review.coreboot.org/25720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71 Gerrit-Change-Number: 25720 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: arch/x86: Print core APIC ID in case of exception
by build bot (Jenkins) (Code Review) 18 Apr '18

18 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25709 ) Change subject: arch/x86: Print core APIC ID in case of exception ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70257/ : SUCCESS -- To view, visit https://review.coreboot.org/25709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2d3776c9259747197a5f2410032f9b03786407fb Gerrit-Change-Number: 25709 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 18 Apr 2018 07:58:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/octopus: Select DRIVERS_I2C_HID
by build bot (Jenkins) (Code Review) 18 Apr '18

18 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25710 ) Change subject: mb/google/octopus: Select DRIVERS_I2C_HID ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70256/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/24476/ : SUCCESS -- To view, visit https://review.coreboot.org/25710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I526c0ac7b88dec7b2b22d022d911840555f15cde Gerrit-Change-Number: 25710 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 18 Apr 2018 06:44:22 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/octopus: Select DRIVERS_I2C_HID
by Furquan Shaikh (Code Review) 18 Apr '18

18 Apr '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/25710 Change subject: mb/google/octopus: Select DRIVERS_I2C_HID ...................................................................... mb/google/octopus: Select DRIVERS_I2C_HID This change selects DRIVERS_I2C_HID which is required for adding SSDT node for digitizer. BUG=b:78099046 Change-Id: I526c0ac7b88dec7b2b22d022d911840555f15cde Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/25710/1 diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 90f58ad..0ca047a 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -6,6 +6,7 @@ select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_DA7219 select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID select DRIVERS_PS2_KEYBOARD select DRIVERS_SPI_ACPI select EC_GOOGLE_CHROMEEC -- To view, visit https://review.coreboot.org/25710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I526c0ac7b88dec7b2b22d022d911840555f15cde Gerrit-Change-Number: 25710 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: arch/x86: Debug print to know core APIC ID incase of exception
by build bot (Jenkins) (Code Review) 18 Apr '18

18 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25709 ) Change subject: arch/x86: Debug print to know core APIC ID incase of exception ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70254/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/24474/ : SUCCESS -- To view, visit https://review.coreboot.org/25709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2d3776c9259747197a5f2410032f9b03786407fb Gerrit-Change-Number: 25709 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 18 Apr 2018 06:38:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Set DISB after Dram init
by build bot (Jenkins) (Code Review) 18 Apr '18

18 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25704 ) Change subject: soc/intel/cannonlake: Set DISB after Dram init ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70255/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/24475/ : SUCCESS -- To view, visit https://review.coreboot.org/25704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I16dd3787cb743bc5b7492042f3c3757534e1a51c Gerrit-Change-Number: 25704 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Kin Wai Ng <kin.wai.ng(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Wed, 18 Apr 2018 06:35:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Assign Cpu Mp PPI FSP upd to handle feature pro...
by build bot (Jenkins) (Code Review) 18 Apr '18

18 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25657 ) Change subject: soc/intel/cannonlake: Assign Cpu Mp PPI FSP upd to handle feature programming ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70253/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/24473/ : SUCCESS -- To view, visit https://review.coreboot.org/25657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iae1984cfd81cbaecf24bb82229e48b9f36abd110 Gerrit-Change-Number: 25657 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 18 Apr 2018 06:31:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: arch/x86: Debug print to know core APIC ID incase of exception
by Subrata Banik (Code Review) 18 Apr '18

18 Apr '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/25709 Change subject: arch/x86: Debug print to know core APIC ID incase of exception ...................................................................... arch/x86: Debug print to know core APIC ID incase of exception BUG=b:74436746 BRANCH=none TEST=Able to get APIC ID number for debug. Change-Id: I2d3776c9259747197a5f2410032f9b03786407fb Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/exception.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/25709/1 diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index 36697c6..8473449 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -14,6 +14,7 @@ #include <console/console.h> #include <console/streams.h> #include <string.h> +#include <cpu/x86/lapic.h> #if IS_ENABLED(CONFIG_GDB_STUB) @@ -496,10 +497,11 @@ #else /* !CONFIG_GDB_STUB */ #define MDUMP_SIZE 0x80 printk(BIOS_EMERG, - "Unexpected Exception: %d @ %02x:%08x - Halting\n" + "APIC %d Unexpected Exception: %d @ %02x:%08x - Halting\n" "Code: %d eflags: %08x\n" "eax: %08x ebx: %08x ecx: %08x edx: %08x\n" "edi: %08x esi: %08x ebp: %08x esp: %08x\n", + (unsigned int)lapicid(), info->vector, info->cs, info->eip, info->error_code, info->eflags, info->eax, info->ebx, info->ecx, info->edx, -- To view, visit https://review.coreboot.org/25709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2d3776c9259747197a5f2410032f9b03786407fb Gerrit-Change-Number: 25709 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: opencellular/supabrckv1: Add LPC TPM to devicetree
by build bot (Jenkins) (Code Review) 18 Apr '18

18 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25705 ) Change subject: opencellular/supabrckv1: Add LPC TPM to devicetree ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/70252/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/24472/ : SUCCESS -- To view, visit https://review.coreboot.org/25705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2ec0fca97f4581a1da35d424ace0526017a8e651 Gerrit-Change-Number: 25705 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 18 Apr 2018 00:54:43 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit April 2018