coreboot-gerrit March 2018

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Change in coreboot[master]: soc/intel/broadwell: If L1 Sub state is disabled, do not set capability
by Matt DeVillier (Code Review) 22 Mar '18

22 Mar '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/25325 Change subject: soc/intel/broadwell: If L1 Sub state is disabled, do not set capability ...................................................................... soc/intel/broadwell: If L1 Sub state is disabled, do not set capability I finally found out why disabling the L1 sub state option did not prevent some NVMe drives from locking up in L1 substate. I expect that the disabled L1 substate initialization that coreboot does is negated because Linux might itself configure it if it finds the capability enabled on the PCIe root port. Removing the capability from the PCIe root port when L1 sub states are disabled in the configuration should fix the problem. This was not tested because it's a difficult issue to reproduce and I do not have the problematic hardware that caused it anymore. Change-Id: I293a650db307e77cee024a43fbfc81e1d8c86265 Signed-off-by: Youness Alaoui <kakaroto(a)kakaroto.homelinux.net> --- M src/soc/intel/broadwell/pcie.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/25325/1 diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index aff66a3..cf25749 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -558,7 +558,10 @@ (1 << 29) | 0x10001); /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */ - pci_update_config32(dev, 0x200, ~0xffff, 0x001e); + if (IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE)) + pci_update_config32(dev, 0x200, ~0xfffff, 0x001e); + else + pci_update_config32(dev, 0x200, ~0xfffff, 0); pci_update_config32(dev, 0x320, ~(3 << 20) & ~(7 << 6), (1 << 20) | (3 << 6)); -- To view, visit https://review.coreboot.org/25325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I293a650db307e77cee024a43fbfc81e1d8c86265 Gerrit-Change-Number: 25325 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: purism/librem_skl: Add AC/DC LoadLine to VR Config
by Matt DeVillier (Code Review) 22 Mar '18

22 Mar '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/25324 Change subject: purism/librem_skl: Add AC/DC LoadLine to VR Config ...................................................................... purism/librem_skl: Add AC/DC LoadLine to VR Config The FSP 2.0 needs to set the ac_loadline and dc_loadline for each VR config. Without it, the Loadline is considered to be 0 mOhm and this causes CPU temp to jump all over the place whenever the CPU is used. These values were copied from the Google Poppy devicetree. Change-Id: I6aeb6ee521988b94f2ae94a60d1a28b87ba984d4 Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> --- M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb 2 files changed, 50 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/25324/1 diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index 159d921..86808eb 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -31,8 +31,8 @@ # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" - # Enable DPTF - register "dptf_enable" = "1" + # Disable DPTF + register "dptf_enable" = "0" # FSP Configuration register "ProbelessTrace" = "0" @@ -82,19 +82,21 @@ register "pirqh_routing" = "PCH_IRQ11" # VR Settings Configuration for 4 Domains - #+----------------+-------+-------+-------------+-------+ - #| Domain/Setting | SA | IA | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------+ + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm | + #| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm | + #+----------------+-----------+-----------+-------------+----------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), @@ -106,6 +108,8 @@ .imon_offset = 0x0, .icc_max = VR_CFG_AMP(7), .voltage_limit = 1520, + .ac_loadline = 1500, + .dc_loadline = 1430, }" register "domain_vr_config[VR_IA_CORE]" = "{ @@ -119,6 +123,8 @@ .imon_offset = 0x0, .icc_max = VR_CFG_AMP(34), .voltage_limit = 1520, + .ac_loadline = 570, + .dc_loadline = 483, }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ @@ -132,6 +138,8 @@ .imon_offset = 0x0, .icc_max = VR_CFG_AMP(35), .voltage_limit = 1520, + .ac_loadline = 520, + .dc_loadline = 420, }" register "domain_vr_config[VR_GT_SLICED]" = "{ @@ -145,6 +153,8 @@ .imon_offset = 0x0, .icc_max = VR_CFG_AMP(35), .voltage_limit = 1520, + .ac_loadline = 520, + .dc_loadline = 420, }" # Enable Root Ports 5 and 9 diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index 035db18..fddb0aa 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -31,8 +31,8 @@ # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" - # Enable DPTF - register "dptf_enable" = "1" + # Disable DPTF + register "dptf_enable" = "0" # FSP Configuration register "ProbelessTrace" = "0" @@ -82,19 +82,21 @@ register "pirqh_routing" = "PCH_IRQ11" # VR Settings Configuration for 4 Domains - #+----------------+-------+-------+-------------+-------+ - #| Domain/Setting | SA | IA | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------+ + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm | + #| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm | + #+----------------+-----------+-----------+-------------+----------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), @@ -106,6 +108,8 @@ .imon_offset = 0x0, .icc_max = VR_CFG_AMP(7), .voltage_limit = 1520, + .ac_loadline = 1500, + .dc_loadline = 1430, }" register "domain_vr_config[VR_IA_CORE]" = "{ @@ -119,6 +123,8 @@ .imon_offset = 0x0, .icc_max = VR_CFG_AMP(34), .voltage_limit = 1520, + .ac_loadline = 570, + .dc_loadline = 483, }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ @@ -132,6 +138,8 @@ .imon_offset = 0x0, .icc_max = VR_CFG_AMP(35), .voltage_limit = 1520, + .ac_loadline = 520, + .dc_loadline = 420, }" register "domain_vr_config[VR_GT_SLICED]" = "{ @@ -145,6 +153,8 @@ .imon_offset = 0x0, .icc_max = VR_CFG_AMP(35), .voltage_limit = 1520, + .ac_loadline = 520, + .dc_loadline = 420, }" # Enable Root Ports 5 and 9 -- To view, visit https://review.coreboot.org/25324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6aeb6ee521988b94f2ae94a60d1a28b87ba984d4 Gerrit-Change-Number: 25324 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: purism/librem_skl: Set TCC Activation at 95C
by Matt DeVillier (Code Review) 22 Mar '18

22 Mar '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/25323 Change subject: purism/librem_skl: Set TCC Activation at 95C ...................................................................... purism/librem_skl: Set TCC Activation at 95C Set the Thermal Control Circuit (TCC) activaction value to 95C even though FSP integration guide says to set it to 100C for SKL-U (offset at 0), because when the TCC activates at 100C, the CPU will have already shut itself down from overheating protection. This was tested on Purism Librem 13 v2. A bisect showed that the immediate shutdowns happened after commit [1] was merged which led to this solution. [1] ec5a947b (soc/intel/skylake: make tcc_offset take effect) Change-Id: Idfc001c8e46ed3b07b24150c961c4b9bc9b71a62 Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/25323/1 diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index 9ce1d91..159d921 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -10,6 +10,12 @@ register "eist_enable" = "1" register "VmxEnable" = "1" + # Set the Thermal Control Circuit (TCC) activaction value to 95C + # even though FSP integration guide says to set it to 100C for SKL-U + # (offset at 0), because when the TCC activates at 100C, the CPU + # will have already shut itself down from overheating protection. + register "tcc_offset" = "5" # TCC of 95C + # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index ac082e6..035db18 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -10,6 +10,12 @@ register "eist_enable" = "1" register "VmxEnable" = "1" + # Set the Thermal Control Circuit (TCC) activaction value to 95C + # even though FSP integration guide says to set it to 100C for SKL-U + # (offset at 0), because when the TCC activates at 100C, the CPU + # will have already shut itself down from overheating protection. + register "tcc_offset" = "5" # TCC of 95C + # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE -- To view, visit https://review.coreboot.org/25323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idfc001c8e46ed3b07b24150c961c4b9bc9b71a62 Gerrit-Change-Number: 25323 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: mb/google/kahlee: Fix IRQ routing
by build bot (Jenkins) (Code Review) 22 Mar '18

22 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25107 ) Change subject: mb/google/kahlee: Fix IRQ routing ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23298/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68933/ : SUCCESS -- To view, visit https://review.coreboot.org/25107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibb048d3e728dc562cb31b9ddd50bfd8fb032017e Gerrit-Change-Number: 25107 Gerrit-PatchSet: 7 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Mar 2018 20:24:06 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: include: Update dimm_info documentation
by build bot (Jenkins) (Code Review) 22 Mar '18

22 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25301 ) Change subject: include: Update dimm_info documentation ...................................................................... Patch Set 9: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23294/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68929/ : SUCCESS -- To view, visit https://review.coreboot.org/25301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1f2a3a70919c34f17472904323ec5accdfc876be Gerrit-Change-Number: 25301 Gerrit-PatchSet: 9 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Comment-Date: Thu, 22 Mar 2018 17:29:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd: Fix generating SMBIOS Type 17
by build bot (Jenkins) (Code Review) 22 Mar '18

22 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25304 ) Change subject: soc/amd: Fix generating SMBIOS Type 17 ...................................................................... Patch Set 12: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23297/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68932/ : SUCCESS -- To view, visit https://review.coreboot.org/25304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I076bc3f965f81a9374c8976da48c7fdce014dc0c Gerrit-Change-Number: 25304 Gerrit-PatchSet: 12 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Comment-Date: Thu, 22 Mar 2018 17:28:51 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: arch/x86/smbios: Strip trailing whitespace on DMI 17 part number.
by build bot (Jenkins) (Code Review) 22 Mar '18

22 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25302 ) Change subject: arch/x86/smbios: Strip trailing whitespace on DMI 17 part number. ...................................................................... Patch Set 10: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23295/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68930/ : SUCCESS -- To view, visit https://review.coreboot.org/25302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia10ef434a2377e34ae7a8f733c6465c2f8ee8dfa Gerrit-Change-Number: 25302 Gerrit-PatchSet: 10 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Mar 2018 17:27:10 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd: Print dimm_info and TYPE17_DMI_INFO to help debug incorrect ...
by build bot (Jenkins) (Code Review) 22 Mar '18

22 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25303 ) Change subject: soc/amd: Print dimm_info and TYPE17_DMI_INFO to help debug incorrect values ...................................................................... Patch Set 10: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23296/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68931/ : SUCCESS -- To view, visit https://review.coreboot.org/25303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5eac00b9400056357915761287770a400b3f9f8b Gerrit-Change-Number: 25303 Gerrit-PatchSet: 10 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Comment-Date: Thu, 22 Mar 2018 17:27:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd: Fix generating SMBIOS Type 17
by build bot (Jenkins) (Code Review) 22 Mar '18

22 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25304 ) Change subject: soc/amd: Fix generating SMBIOS Type 17 ...................................................................... Patch Set 11: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23293/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68928/ : SUCCESS -- To view, visit https://review.coreboot.org/25304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I076bc3f965f81a9374c8976da48c7fdce014dc0c Gerrit-Change-Number: 25304 Gerrit-PatchSet: 11 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Comment-Date: Thu, 22 Mar 2018 17:17:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: include: Update dimm_info documentation
by build bot (Jenkins) (Code Review) 22 Mar '18

22 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25301 ) Change subject: include: Update dimm_info documentation ...................................................................... Patch Set 8: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23290/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68925/ : SUCCESS -- To view, visit https://review.coreboot.org/25301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1f2a3a70919c34f17472904323ec5accdfc876be Gerrit-Change-Number: 25301 Gerrit-PatchSet: 8 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Comment-Date: Thu, 22 Mar 2018 17:14:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit March 2018