coreboot-gerrit March 2018

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Change in coreboot[master]: purism/librem_skl: Set TCC Activation at 95C
by build bot (Jenkins) (Code Review) 22 Mar '18

22 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25323 ) Change subject: purism/librem_skl: Set TCC Activation at 95C ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/68937/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/23302/ : SUCCESS -- To view, visit https://review.coreboot.org/25323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idfc001c8e46ed3b07b24150c961c4b9bc9b71a62 Gerrit-Change-Number: 25323 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Mar 2018 21:21:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: drivers/intel/fsp: Fix TPM initialization when vboot is disabled
by build bot (Jenkins) (Code Review) 22 Mar '18

22 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23680 ) Change subject: drivers/intel/fsp: Fix TPM initialization when vboot is disabled ...................................................................... Patch Set 2: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/68934/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/23299/ : SUCCESS -- To view, visit https://review.coreboot.org/23680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic43d1aa31a296386c7eab6d997f9b701e9ea0fe5 Gerrit-Change-Number: 23680 Gerrit-PatchSet: 2 Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Mar 2018 21:21:22 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: purism/librem_skl: Enable VMX and Intel SpeedStep in devicetree
by build bot (Jenkins) (Code Review) 22 Mar '18

22 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23684 ) Change subject: purism/librem_skl: Enable VMX and Intel SpeedStep in devicetree ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/68935/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/23300/ : SUCCESS -- To view, visit https://review.coreboot.org/23684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I968ef36ec9382a10db13d96fd3a5c0fc904db387 Gerrit-Change-Number: 23684 Gerrit-PatchSet: 3 Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Mar 2018 21:21:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/skylake: enable VMX support
by Matt DeVillier (Code Review) 22 Mar '18

22 Mar '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/25332 Change subject: soc/intel/skylake: enable VMX support ...................................................................... soc/intel/skylake: enable VMX support Use soc/common VMX block to enable VMX on supported devices. Change-Id: Iaa1a6201b431783d709c0509715fa8e8b1ce349a Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/cpu.c 2 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/25332/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index aac4a8f..a4178be 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -84,6 +84,7 @@ select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_UART + select SOC_INTEL_COMMON_BLOCK_VMX select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_GFX_OPREGION select SOC_INTEL_COMMON_NHLT diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 1a2de73..4a9d298 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -39,6 +39,7 @@ #include <intelblocks/mp_init.h> #include <intelblocks/sgx.h> #include <intelblocks/smm.h> +#include <intelblocks/vmx.h> #include <pc80/mc146818rtc.h> #include <soc/cpu.h> #include <soc/msr.h> @@ -476,6 +477,8 @@ smm_lock(); #endif + mp_run_on_all_cpus(vmx_configure, 2000); + mp_run_on_all_cpus(sgx_configure, 2000); } @@ -552,3 +555,17 @@ sgx_param->enable = conf->sgx_enable; return 0; } +int soc_fill_vmx_param(struct vmx_param *vmx_param) +{ + device_t dev = SA_DEV_ROOT; + assert(dev != NULL); + config_t *conf = dev->chip_info; + + if (!conf) { + printk(BIOS_ERR, "Failed to get chip_info for VMX param\n"); + return -1; + } + + vmx_param->enable = conf->VmxEnable; + return 0; +} -- To view, visit https://review.coreboot.org/25332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iaa1a6201b431783d709c0509715fa8e8b1ce349a Gerrit-Change-Number: 25332 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: soc/intel/common/block: add VMX support
by Matt DeVillier (Code Review) 22 Mar '18

22 Mar '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/25331 Change subject: soc/intel/common/block: add VMX support ...................................................................... soc/intel/common/block: add VMX support Enable VMX (and SMX) if supported by CPU and enabled in board devicetree. Check lock bit unset before enabling VMX. Change-Id: Ic57eac45e9c65baa4479735c6d70a7eb685f080e Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/common/block/include/intelblocks/msr.h A src/soc/intel/common/block/include/intelblocks/vmx.h A src/soc/intel/common/block/vmx/Kconfig A src/soc/intel/common/block/vmx/Makefile.inc A src/soc/intel/common/block/vmx/vmx.c 5 files changed, 132 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/25331/1 diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 7aa81f0..ea29bed 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -19,6 +19,8 @@ #define MSR_CORE_THREAD_COUNT 0x35 #define IA32_FEATURE_CONTROL 0x3a #define FEATURE_CONTROL_LOCK (1) +#define FEATURE_ENABLE_VMX (1 << 2) +#define FEATURE_ENABLE_SMX (1 << 1) #define CPUID_VMX (1 << 5) #define CPUID_SMX (1 << 6) #define SGX_GLOBAL_ENABLE (1 << 18) diff --git a/src/soc/intel/common/block/include/intelblocks/vmx.h b/src/soc/intel/common/block/include/intelblocks/vmx.h new file mode 100644 index 0000000..6336498 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/vmx.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_VMX_H +#define SOC_INTEL_COMMON_BLOCK_VMX_H + +struct vmx_param { + uint8_t enable; +}; + +/* + * Configure VMX. + */ +void vmx_configure(void); + +/* SOC specific API to get VMX params. + * returns 0, if able to get VMX params; otherwise returns -1 */ +int soc_fill_vmx_param(struct vmx_param *vmx_param); + +#endif /* SOC_INTEL_COMMON_BLOCK_VMX_H */ diff --git a/src/soc/intel/common/block/vmx/Kconfig b/src/soc/intel/common/block/vmx/Kconfig new file mode 100644 index 0000000..f8dce07 --- /dev/null +++ b/src/soc/intel/common/block/vmx/Kconfig @@ -0,0 +1,3 @@ +config SOC_INTEL_COMMON_BLOCK_VMX + bool "Enable VMX for virtualization" + default n diff --git a/src/soc/intel/common/block/vmx/Makefile.inc b/src/soc/intel/common/block/vmx/Makefile.inc new file mode 100644 index 0000000..861e2f9 --- /dev/null +++ b/src/soc/intel/common/block/vmx/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_VMX) += vmx.c diff --git a/src/soc/intel/common/block/vmx/vmx.c b/src/soc/intel/common/block/vmx/vmx.c new file mode 100644 index 0000000..c7c594d --- /dev/null +++ b/src/soc/intel/common/block/vmx/vmx.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +//#include <assert.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +//#include <cpu/x86/mtrr.h> +//#include <cpu/intel/microcode.h> +//#include <intelblocks/mp_init.h> +#include <intelblocks/msr.h> +#include <intelblocks/vmx.h> +//#include <intelblocks/systemagent.h> +#include <soc/cpu.h> +//#include <soc/pci_devs.h> +#include <string.h> + +static bool vmx_param_valid; +static struct vmx_param g_vmx_param; + +static const struct vmx_param *get_vmx_param(void) +{ + if (vmx_param_valid) + return &g_vmx_param; + + memset(&g_vmx_param, 0, sizeof(g_vmx_param)); + if (soc_fill_vmx_param(&g_vmx_param) < 0) { + printk(BIOS_ERR, "VMX : Failed to get soc vmx param\n"); + return NULL; + } + vmx_param_valid = true; + printk(BIOS_INFO, "VMX : param.enable = %d\n", g_vmx_param.enable); + + return &g_vmx_param; +} + +static int soc_vmx_enabled(void) +{ + const struct vmx_param *vmx_param = get_vmx_param(); + return vmx_param ? vmx_param->enable : 0; +} + +static int is_vmx_supported(struct cpuid_result regs) +{ + /* Check that VMX is supported */ + if (!(regs.ecx & CPUID_VMX)) { + printk(BIOS_DEBUG, "CPU doesn't support VMX\n"); + return 0; + } + return 1; +} + +void vmx_configure(void) +{ + msr_t msr; + struct cpuid_result regs; + + regs = cpuid(1); + + if (!soc_vmx_enabled() || !is_vmx_supported(regs)) { + printk(BIOS_ERR, "VMX: pre-conditions not met\n"); + return; + } + + msr = rdmsr(IA32_FEATURE_CONTROL); + + /* Only enable it when it is not locked */ + if ((msr.lo & FEATURE_CONTROL_LOCK) == 0) { + /* Enable VMX (and SMX, if supported) */ + msr.lo |= FEATURE_ENABLE_VMX; + if (regs.ecx & CPUID_SMX) + msr.lo |= FEATURE_ENABLE_SMX; + wrmsr(IA32_FEATURE_CONTROL, msr); + } else { + printk(BIOS_ERR, "VMX: feature control locked, cannot set\n"); + } + + /* Report current status */ + msr = rdmsr(IA32_FEATURE_CONTROL); + printk(BIOS_DEBUG, "VMX status: %s, %s\n", + (msr.lo & FEATURE_ENABLE_VMX) ? "enabled" : "disabled", + (msr.lo & FEATURE_CONTROL_LOCK) ? "locked" : "unlocked"); +} -- To view, visit https://review.coreboot.org/25331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic57eac45e9c65baa4479735c6d70a7eb685f080e Gerrit-Change-Number: 25331 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: soc/skylake/cpu: Fix Intel SpeedStep enable/disable
by Matt DeVillier (Code Review) 22 Mar '18

22 Mar '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/25330 Change subject: soc/skylake/cpu: Fix Intel SpeedStep enable/disable ...................................................................... soc/skylake/cpu: Fix Intel SpeedStep enable/disable In an attempt at consolidation, commit 0a203d1 [1] introduced an additional read/write of the MISC_ENABLE msr, as well a bug which nullified the setting of Intel SpeedStep by inserting said read/write calls in between another set of read/write calls to the same msr. Fix by reverting to previous (simpler) implementation. [1] soc/intel/skylake: Use CPU common library code https://review.coreboot.org/19566 Test: boot Linux on Librem13v2, read MISC_ENABLE msr and verify SpeedStep bit correctly set based on devicetree setting. Change-Id: Id2ac660bf8ea56d45e8c3f631a586b74106a6cc9 Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/skylake/cpu.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/25330/1 diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 6e98afa..1a2de73 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -293,9 +293,9 @@ msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ if (conf->eist_enable) - cpu_enable_eist(); + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ else - cpu_disable_eist(); + msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */ wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ -- To view, visit https://review.coreboot.org/25330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id2ac660bf8ea56d45e8c3f631a586b74106a6cc9 Gerrit-Change-Number: 25330 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: ec/purism: Fix CPU Turbo value (PPCM) set by the EC
by Matt DeVillier (Code Review) 22 Mar '18

22 Mar '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/25329 Change subject: ec/purism: Fix CPU Turbo value (PPCM) set by the EC ...................................................................... ec/purism: Fix CPU Turbo value (PPCM) set by the EC The EC needs to set the PPCM value depending on whether Turbo is enabled or not, and the values differ between Broadwell (0, 1) and Skylake (1, 2) platforms. Change-Id: I662dce54415e685c054ffc00b6afde0f1f7765e2 Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> --- M src/ec/purism/librem/acpi/ec.asl M src/mainboard/purism/librem13v1/acpi/ec.asl M src/mainboard/purism/librem_skl/acpi/ec.asl 3 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/25329/1 diff --git a/src/ec/purism/librem/acpi/ec.asl b/src/ec/purism/librem/acpi/ec.asl index e95f126..ff325aa 100644 --- a/src/ec/purism/librem/acpi/ec.asl +++ b/src/ec/purism/librem/acpi/ec.asl @@ -218,11 +218,11 @@ * when the system is charging. */ If (TURB) { - Store (Zero, PPCM) + Store (PPCM_TURBO, PPCM) PPCN () Store (One, EDTB) } Else { - Store (One, PPCM) + Store (PPCM_NOTURBO, PPCM) PPCN () Store (Zero, EDTB) } diff --git a/src/mainboard/purism/librem13v1/acpi/ec.asl b/src/mainboard/purism/librem13v1/acpi/ec.asl index cf8b9a9..b2fa5b9 100644 --- a/src/mainboard/purism/librem13v1/acpi/ec.asl +++ b/src/mainboard/purism/librem13v1/acpi/ec.asl @@ -14,5 +14,7 @@ */ #define EC_SCI_GPI 10 +#define PPCM_TURBO Zero +#define PPCM_NOTURBO One #include <ec/purism/librem/acpi/ec.asl> diff --git a/src/mainboard/purism/librem_skl/acpi/ec.asl b/src/mainboard/purism/librem_skl/acpi/ec.asl index 4215213..c667b6c 100644 --- a/src/mainboard/purism/librem_skl/acpi/ec.asl +++ b/src/mainboard/purism/librem_skl/acpi/ec.asl @@ -14,5 +14,7 @@ */ #define EC_SCI_GPI 0x50 +#define PPCM_TURBO One +#define PPCM_NOTURBO 0x02 #include <ec/purism/librem/acpi/ec.asl> -- To view, visit https://review.coreboot.org/25329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I662dce54415e685c054ffc00b6afde0f1f7765e2 Gerrit-Change-Number: 25329 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: purism/librem13v1, librem13v2, liberm15v3: Fix EC LPC I/O port
by Matt DeVillier (Code Review) 22 Mar '18

22 Mar '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/25328 Change subject: purism/librem13v1, librem13v2, liberm15v3: Fix EC LPC I/O port ...................................................................... purism/librem13v1, librem13v2, liberm15v3: Fix EC LPC I/O port The LPC I/O ports for EC communication were not set properly, causing ectool to fail to read the Index I/O from the EC. The EC Index I/O is on port 0x380 and the LPC I/O port needs to be decoded by the PCI device for it to be accessible. Correct the value for the Librem 13v1, 13v2 and 15v3. Change-Id: Ide1d158340eadfabbce5f70ceccddfabb4db188a Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> --- M src/mainboard/purism/librem13v1/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb 3 files changed, 10 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/25328/1 diff --git a/src/mainboard/purism/librem13v1/devicetree.cb b/src/mainboard/purism/librem13v1/devicetree.cb index ba38070..c916e9a 100644 --- a/src/mainboard/purism/librem13v1/devicetree.cb +++ b/src/mainboard/purism/librem13v1/devicetree.cb @@ -18,6 +18,10 @@ register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms + # EC host command ranges are in 0x380-0x383 & 0x80-0x8f + register "gen1_dec" = "0x00000381" + register "gen2_dec" = "0x000c0081" + # Port 0 is HDD # Port 3 is M.2 NGFF register "sata_port_map" = "0x9" diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index 1fc19a5..50e484b 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -15,9 +15,9 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + # EC host command ranges are in 0x380-0x383 & 0x80-0x8f + register "gen1_dec" = "0x00000381" + register "gen2_dec" = "0x000c0081" # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index 647f054..a52e4b7 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -15,9 +15,9 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + # EC host command ranges are in 0x380-0x383 & 0x80-0x8f + register "gen1_dec" = "0x00000381" + register "gen2_dec" = "0x000c0081" # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" -- To view, visit https://review.coreboot.org/25328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ide1d158340eadfabbce5f70ceccddfabb4db188a Gerrit-Change-Number: 25328 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: purism/librem13v1: Disable PCI Express AER capability
by Matt DeVillier (Code Review) 22 Mar '18

22 Mar '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/25327 Change subject: purism/librem13v1: Disable PCI Express AER capability ...................................................................... purism/librem13v1: Disable PCI Express AER capability The Librem 13v1 does not seem to have working AER and this option was needed and tested on the Librem 13v1. Without it, the linux console gets spammed with AER errrors. Change-Id: I13d0afa085b426920d7a946e6209f924ce29ae52 Signed-off-by: Youness Alaoui <kakaroto(a)kakaroto.homelinux.net> --- M src/mainboard/purism/librem13v1/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/25327/1 diff --git a/src/mainboard/purism/librem13v1/Kconfig b/src/mainboard/purism/librem13v1/Kconfig index abd499c..c4fb14b 100644 --- a/src/mainboard/purism/librem13v1/Kconfig +++ b/src/mainboard/purism/librem13v1/Kconfig @@ -24,6 +24,9 @@ config PCIEXP_L1_SUB_STATE def_bool n +config PCIEXP_AER + def_bool n + config HAVE_IFD_BIN bool default n -- To view, visit https://review.coreboot.org/25327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I13d0afa085b426920d7a946e6209f924ce29ae52 Gerrit-Change-Number: 25327 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: soc/intel/broadwell: Add option to disable PCIe AER capability
by Matt DeVillier (Code Review) 22 Mar '18

22 Mar '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/25326 Change subject: soc/intel/broadwell: Add option to disable PCIe AER capability ...................................................................... soc/intel/broadwell: Add option to disable PCIe AER capability The Advanced Error Reporting capability was hardcoded in the PCIe extended capability list, but it might not always be possible. The Librem 13v1 does not seem to have working AER and this option was needed and tested on the Librem 13v1. Without it, the linux console gets spammed with AER errrors. Change-Id: If2e0ec42c93f1fee927eacdf0099004cf9302fbe Signed-off-by: Youness Alaoui <kakaroto(a)kakaroto.homelinux.net> --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/pcie.c 2 files changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/25326/1 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index cfab489..5d8d602 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -47,6 +47,10 @@ bool default y +config PCIEXP_AER + bool + default y + config PCIEXP_COMMON_CLOCK bool default y diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index cf25749..53a1eac 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -554,8 +554,12 @@ pci_update_config8(dev, 0xf5, 0x0f, 0); /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */ - pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff, - (1 << 29) | 0x10001); + if (IS_ENABLED(CONFIG_PCIEXP_AER)) + pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff, + (1 << 29) | 0x10001); + else + pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff, + (1 << 29)); /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */ if (IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE)) -- To view, visit https://review.coreboot.org/25326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If2e0ec42c93f1fee927eacdf0099004cf9302fbe Gerrit-Change-Number: 25326 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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coreboot-gerrit March 2018