coreboot-gerrit March 2018

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Change in coreboot[master]: Eve: NHLT changes to enable Windows use audio codecs
by HARSHAPRIYA N (Code Review) 23 Mar '18

23 Mar '18

HARSHAPRIYA N has posted comments on this change. ( https://review.coreboot.org/25334 ) Change subject: Eve: NHLT changes to enable Windows use audio codecs ...................................................................... Patch Set 1: Code-Review-1 -- To view, visit https://review.coreboot.org/25334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib13110f4d42e140aa1356ed0b6a6127943b6e800 Gerrit-Change-Number: 25334 Gerrit-PatchSet: 1 Gerrit-Owner: HARSHAPRIYA N <harshapriya.n(a)intel.com> Gerrit-Reviewer: HARSHAPRIYA N <harshapriya.n(a)intel.com> Gerrit-Comment-Date: Fri, 23 Mar 2018 01:42:29 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Eve: NHLT changes to enable Windows use audio codecs
by HARSHAPRIYA N (Code Review) 23 Mar '18

23 Mar '18

HARSHAPRIYA N has uploaded this change for review. ( https://review.coreboot.org/25334 Change subject: Eve: NHLT changes to enable Windows use audio codecs ...................................................................... Eve: NHLT changes to enable Windows use audio codecs This patch adds changes to nhlt to enable windows use audio codecs and enable audio functionality Change-Id: Ib13110f4d42e140aa1356ed0b6a6127943b6e800 --- M src/include/nhlt.h M src/lib/nhlt.c M src/mainboard/google/eve/mainboard.c M src/soc/intel/skylake/include/soc/nhlt.h M src/soc/intel/skylake/nhlt/max98927.c M src/soc/intel/skylake/nhlt/rt5514.c M src/soc/intel/skylake/nhlt/rt5663.c 7 files changed, 58 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/25334/1 diff --git a/src/include/nhlt.h b/src/include/nhlt.h index 5b72320..ddebd5f 100644 --- a/src/include/nhlt.h +++ b/src/include/nhlt.h @@ -207,6 +207,7 @@ NHLT_DIR_RENDER, NHLT_DIR_CAPTURE, NHLT_DIR_BIDIRECTIONAL, + NHLT_DIR_FEEDBACK, }; /* Channel Mask for an endpoint. While they are prefixed with 'SPEAKER' the @@ -301,6 +302,7 @@ uint8_t num_endpoints; struct nhlt_endpoint endpoints[MAX_ENDPOINTS]; uint8_t current_instance_id[NHLT_MAX_LINK_TYPES]; + uint32_t buffer_size; }; struct nhlt_tdm_config { @@ -313,6 +315,13 @@ NHLT_TDM_MIC_ARRAY, }; +struct maxm_array_config { + struct nhlt_tdm_config tdm_config1; + uint8_t feedback_virtual_slot; + uint16_t feedback_channels; + uint16_t feedback_valid_bits_per_sample; +}; + struct nhlt_dmic_array_config { struct nhlt_tdm_config tdm_config; uint8_t array_type; diff --git a/src/lib/nhlt.c b/src/lib/nhlt.c index da94415..723123c 100644 --- a/src/lib/nhlt.c +++ b/src/lib/nhlt.c @@ -275,7 +275,7 @@ size_t nhlt_current_size(struct nhlt *nhlt) { - return calc_size(nhlt) + sizeof(acpi_header_t); + return calc_size(nhlt) + sizeof(acpi_header_t) + sizeof(uint32_t); } static void nhlt_free_resources(struct nhlt *nhlt) @@ -386,6 +386,7 @@ for (i = 0; i < nhlt->num_endpoints; i++) serialize_endpoint(&nhlt->endpoints[i], cur); + ser32(cur, nhlt->buffer_size); } uintptr_t nhlt_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) diff --git a/src/mainboard/google/eve/mainboard.c b/src/mainboard/google/eve/mainboard.c index d30eff2..f8e3126 100644 --- a/src/mainboard/google/eve/mainboard.c +++ b/src/mainboard/google/eve/mainboard.c @@ -45,14 +45,26 @@ /* 4 Channel DMIC array */ if (nhlt_soc_add_rt5514(nhlt, AUDIO_LINK_SSP0, 4)) printk(BIOS_ERR, "Couldn't add rt5514.\n"); + nhlt->endpoints[nhlt->num_endpoints-1].instance_id = 0; + nhlt->endpoints[nhlt->num_endpoints-1].subsystem_id = 0x006B; /* RT5663 Headset codec */ if (nhlt_soc_add_rt5663(nhlt, AUDIO_LINK_SSP1)) printk(BIOS_ERR, "Couldn't add headset codec.\n"); + nhlt->endpoints[nhlt->num_endpoints-1].instance_id = 0; + nhlt->endpoints[nhlt->num_endpoints-1].subsystem_id = 0x006B; + nhlt->endpoints[nhlt->num_endpoints-2].instance_id = 0; + nhlt->endpoints[nhlt->num_endpoints-2].subsystem_id = 0x006B; /* MAXIM98927 Smart Amps for left and right channel */ if (nhlt_soc_add_max98927(nhlt, AUDIO_LINK_SSP0)) printk(BIOS_ERR, "Couldn't add max98927\n"); + nhlt->endpoints[nhlt->num_endpoints-1].instance_id = 0; + nhlt->endpoints[nhlt->num_endpoints-1].subsystem_id = 0x006B; + nhlt->endpoints[nhlt->num_endpoints-2].instance_id = 0; + nhlt->endpoints[nhlt->num_endpoints-2].subsystem_id = 0x006B; + + nhlt->buffer_size = 0; end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr, oem_id_maxim, oem_table_id_maxim, 0); diff --git a/src/soc/intel/skylake/include/soc/nhlt.h b/src/soc/intel/skylake/include/soc/nhlt.h index 1af27e8..b74d2e2 100644 --- a/src/soc/intel/skylake/include/soc/nhlt.h +++ b/src/soc/intel/skylake/include/soc/nhlt.h @@ -19,6 +19,7 @@ #include <nhlt.h> #define NHLT_VID 0x8086 +#define NHLT_GOOGLE_VID 0x1ae0 #define NHLT_DID_DMIC 0xae20 #define NHLT_DID_BT 0xae30 #define NHLT_DID_SSP 0xae34 diff --git a/src/soc/intel/skylake/nhlt/max98927.c b/src/soc/intel/skylake/nhlt/max98927.c index bbaf15d..060657a 100644 --- a/src/soc/intel/skylake/nhlt/max98927.c +++ b/src/soc/intel/skylake/nhlt/max98927.c @@ -16,15 +16,6 @@ #include <soc/nhlt.h> static const struct nhlt_format_config max98927_render_formats[] = { - /* 48 KHz 24-bits per sample. */ - { - .num_channels = 2, - .sample_freq_khz = 48, - .container_bits_per_sample = 32, - .valid_bits_per_sample = 24, - .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98927-render-2ch-48khz-24b.bin", - }, /* 48 KHz 16-bits per sample. */ { .num_channels = 2, @@ -41,29 +32,55 @@ { .num_channels = 4, .sample_freq_khz = 48, - .container_bits_per_sample = 32, + .container_bits_per_sample = 16, .valid_bits_per_sample = 16, .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT | SPEAKER_BACK_LEFT | SPEAKER_BACK_RIGHT, .settings_file = "max98927-render-2ch-48khz-16b.bin", }, }; + +static const struct maxm_array_config render_config = { + .tdm_config1 = { + .virtual_slot = 0x0, + .config_type = 0x3, + }, + .feedback_virtual_slot = 2, + .feedback_channels = 4, + .feedback_valid_bits_per_sample = 16, +}; + +static const struct maxm_array_config capture_config = { + .tdm_config1 = { + .virtual_slot = 0x2, + .config_type = 0x3, + }, + .feedback_virtual_slot = 0, + .feedback_channels = 2, + .feedback_valid_bits_per_sample = 16, +}; + + static const struct nhlt_endp_descriptor max98927_descriptors[] = { { .link = NHLT_LINK_SSP, .device = NHLT_SSP_DEV_I2S, .direction = NHLT_DIR_RENDER, - .vid = NHLT_VID, + .vid = NHLT_GOOGLE_VID, .did = NHLT_DID_SSP, + .cfg = &render_config, + .cfg_size = sizeof(render_config), .formats = max98927_render_formats, .num_formats = ARRAY_SIZE(max98927_render_formats), }, { .link = NHLT_LINK_SSP, .device = NHLT_SSP_DEV_I2S, - .direction = NHLT_DIR_CAPTURE, - .vid = NHLT_VID, + .direction = NHLT_DIR_FEEDBACK, + .vid = NHLT_GOOGLE_VID, .did = NHLT_DID_SSP, + .cfg = &capture_config, + .cfg_size = sizeof(capture_config), .formats = max98927_capture_formats, .num_formats = ARRAY_SIZE(max98927_capture_formats), }, diff --git a/src/soc/intel/skylake/nhlt/rt5514.c b/src/soc/intel/skylake/nhlt/rt5514.c index 9c48c7b..686f3a4 100644 --- a/src/soc/intel/skylake/nhlt/rt5514.c +++ b/src/soc/intel/skylake/nhlt/rt5514.c @@ -30,6 +30,7 @@ static const struct nhlt_dmic_array_config rt5514_4ch_mic_config = { .tdm_config = { + .virtual_slot = 0x1, .config_type = NHLT_TDM_MIC_ARRAY, }, .array_type = NHLT_MIC_ARRAY_4CH_L_SHAPED, @@ -40,7 +41,7 @@ .link = NHLT_LINK_SSP, .device = NHLT_SSP_DEV_I2S, .direction = NHLT_DIR_CAPTURE, - .vid = NHLT_VID, + .vid = NHLT_GOOGLE_VID, .did = NHLT_DID_SSP, .cfg = &rt5514_4ch_mic_config, .cfg_size = sizeof(rt5514_4ch_mic_config), diff --git a/src/soc/intel/skylake/nhlt/rt5663.c b/src/soc/intel/skylake/nhlt/rt5663.c index c5a3f53..d602425 100644 --- a/src/soc/intel/skylake/nhlt/rt5663.c +++ b/src/soc/intel/skylake/nhlt/rt5663.c @@ -46,7 +46,7 @@ .link = NHLT_LINK_SSP, .device = NHLT_SSP_DEV_I2S, .direction = NHLT_DIR_RENDER, - .vid = NHLT_VID, + .vid = NHLT_GOOGLE_VID, .did = NHLT_DID_SSP, .cfg = &tdm_config, .cfg_size = sizeof(tdm_config), @@ -58,7 +58,7 @@ .link = NHLT_LINK_SSP, .device = NHLT_SSP_DEV_I2S, .direction = NHLT_DIR_CAPTURE, - .vid = NHLT_VID, + .vid = NHLT_GOOGLE_VID, .did = NHLT_DID_SSP, .cfg = &tdm_config, .cfg_size = sizeof(tdm_config), -- To view, visit https://review.coreboot.org/25334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib13110f4d42e140aa1356ed0b6a6127943b6e800 Gerrit-Change-Number: 25334 Gerrit-PatchSet: 1 Gerrit-Owner: HARSHAPRIYA N <harshapriya.n(a)intel.com>

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Change in coreboot[master]: soc/intel/common/block: add VMX support
by build bot (Jenkins) (Code Review) 23 Mar '18

23 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25331 ) Change subject: soc/intel/common/block: add VMX support ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23322/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68959/ : SUCCESS -- To view, visit https://review.coreboot.org/25331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic57eac45e9c65baa4479735c6d70a7eb685f080e Gerrit-Change-Number: 25331 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 23 Mar 2018 01:04:55 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/common/block: add VMX support
by Matt DeVillier (Code Review) 23 Mar '18

23 Mar '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/25331 to look at the new patch set (#2). Change subject: soc/intel/common/block: add VMX support ...................................................................... soc/intel/common/block: add VMX support Enable VMX (and SMX) if supported by CPU and enabled in board devicetree. Check lock bit unset before enabling VMX. Change-Id: Ic57eac45e9c65baa4479735c6d70a7eb685f080e Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/common/block/include/intelblocks/msr.h A src/soc/intel/common/block/include/intelblocks/vmx.h A src/soc/intel/common/block/vmx/Kconfig A src/soc/intel/common/block/vmx/Makefile.inc A src/soc/intel/common/block/vmx/vmx.c 5 files changed, 126 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/25331/2 -- To view, visit https://review.coreboot.org/25331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic57eac45e9c65baa4479735c6d70a7eb685f080e Gerrit-Change-Number: 25331 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mainboard/google/meowth: Disable debug consent
by build bot (Jenkins) (Code Review) 22 Mar '18

22 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25312 ) Change subject: mainboard/google/meowth: Disable debug consent ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23321/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68958/ : SUCCESS -- To view, visit https://review.coreboot.org/25312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I05001a41b13e7784c34fa8f1f773fb94bbdcd01f Gerrit-Change-Number: 25312 Gerrit-PatchSet: 2 Gerrit-Owner: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Mar 2018 23:16:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/google/meowth: Disable debug consent
by Vaibhav Shankar (Code Review) 22 Mar '18

22 Mar '18

Vaibhav Shankar has posted comments on this change. ( https://review.coreboot.org/25312 ) Change subject: mainboard/google/meowth: Disable debug consent ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/25312/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/25312/1//COMMIT_MSG@13 PS1, Line 13: None > Submit a partner issue and list the partner issue bug number here for tracking purpose. Done https://review.coreboot.org/#/c/25312/1/src/mainboard/google/zoombini/varia… File src/mainboard/google/zoombini/variants/meowth/devicetree.cb: https://review.coreboot.org/#/c/25312/1/src/mainboard/google/zoombini/varia… PS1, Line 9: DBC over USB 3.0 port only > Update this comment too. Done -- To view, visit https://review.coreboot.org/25312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I05001a41b13e7784c34fa8f1f773fb94bbdcd01f Gerrit-Change-Number: 25312 Gerrit-PatchSet: 1 Gerrit-Owner: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Mar 2018 23:07:50 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/google/meowth: Disable debug consent
by Vaibhav Shankar (Code Review) 22 Mar '18

22 Mar '18

Hello Nick Vaccaro, Bora Guvendik, build bot (Jenkins), Lijian Zhao, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/25312 to look at the new patch set (#2). Change subject: mainboard/google/meowth: Disable debug consent ...................................................................... mainboard/google/meowth: Disable debug consent This patch disables debug consent in the devicetree. When debug conset is set to DBC by default, it prevents some clocks from turning off during S0ix. This blocks S0ix entry. BUG=76163091 TEST=enter S0ix and check if slp_s0 is asserted Change-Id: I05001a41b13e7784c34fa8f1f773fb94bbdcd01f Signed-off-by: Vaibhav Shankar <vaibhav.shankar(a)intel.com> --- M src/mainboard/google/zoombini/variants/meowth/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/25312/2 -- To view, visit https://review.coreboot.org/25312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I05001a41b13e7784c34fa8f1f773fb94bbdcd01f Gerrit-Change-Number: 25312 Gerrit-PatchSet: 2 Gerrit-Owner: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/octopus: Disable PCIE NPK device
by build bot (Jenkins) (Code Review) 22 Mar '18

22 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25333 ) Change subject: mb/octopus: Disable PCIE NPK device ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68957/ : SUCCESS -- To view, visit https://review.coreboot.org/25333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8fe3a36dac2eff2225dacb0e6e16500a5750261e Gerrit-Change-Number: 25333 Gerrit-PatchSet: 2 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Thu, 22 Mar 2018 23:06:29 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/octopus: Disable PCIE NPK device
by Shaunak Saha (Code Review) 22 Mar '18

22 Mar '18

Hello Hannah Williams, I'd like you to reexamine a change. Please visit https://review.coreboot.org/25333 to look at the new patch set (#2). Change subject: mb/octopus: Disable PCIE NPK device ...................................................................... mb/octopus: Disable PCIE NPK device BUG = chrome-os-partner:76115112 TEST = Build for Octopus Change-Id: I8fe3a36dac2eff2225dacb0e6e16500a5750261e Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- M src/mainboard/google/octopus/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/25333/2 -- To view, visit https://review.coreboot.org/25333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I8fe3a36dac2eff2225dacb0e6e16500a5750261e Gerrit-Change-Number: 25333 Gerrit-PatchSet: 2 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com>

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Change in coreboot[master]: purism/librem_skl: Add AC/DC LoadLine to VR Config
by build bot (Jenkins) (Code Review) 22 Mar '18

22 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25324 ) Change subject: purism/librem_skl: Add AC/DC LoadLine to VR Config ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23320/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68956/ : SUCCESS -- To view, visit https://review.coreboot.org/25324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6aeb6ee521988b94f2ae94a60d1a28b87ba984d4 Gerrit-Change-Number: 25324 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Mar 2018 22:40:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit March 2018