coreboot-gerrit March 2018

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Change in coreboot[master]: soc/intel/denverton_ns: Enable Fast Strings
by Julien Viard de Galbert (Code Review) 29 Mar '18

29 Mar '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25431 Change subject: soc/intel/denverton_ns: Enable Fast Strings ...................................................................... soc/intel/denverton_ns: Enable Fast Strings Change-Id: I7cee3c40299abf14a24128b1ac14f1823f87a0e1 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/denverton_ns/include/soc/msr.h 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/25431/1 diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 528d2e5..fba6627 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2015 - 2017 Intel Corp. + * Copyright (C) 2018 Online SAS * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -39,6 +40,11 @@ printk(BIOS_DEBUG, "Init Denverton-NS SoC cores.\n"); + /* Enable Fast Strings */ + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= FAST_STRINGS_ENABLE_BIT; + wrmsr(IA32_MISC_ENABLE, msr); + /* Enable Turbo */ enable_turbo(); diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 4d1ac70..d56cc65 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -106,6 +106,7 @@ #define PRMRR_SUPPORTED (1 << 12) /* IA32_MISC_ENABLE bits */ +#define FAST_STRINGS_ENABLE_BIT (1 << 0) #define SPEED_STEP_ENABLE_BIT (1 << 16) /* Read BCLK from MSR */ -- To view, visit https://review.coreboot.org/25431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7cee3c40299abf14a24128b1ac14f1823f87a0e1 Gerrit-Change-Number: 25431 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: soc/intel/denverton_ns: Add ACPI T-States and P-States
by Julien Viard de Galbert (Code Review) 29 Mar '18

29 Mar '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25430 Change subject: soc/intel/denverton_ns: Add ACPI T-States and P-States ...................................................................... soc/intel/denverton_ns: Add ACPI T-States and P-States Also make soc_get_tss_table public and weak instead of static in intelblock so it can be overridden in denverton. Change-Id: Id9c7da474a81417a5cebd875023f7cd3d5a77796 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/acpi.h M src/soc/intel/denverton_ns/acpi.c 3 files changed, 31 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/25430/1 diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 68fe944..d375eff 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -377,7 +377,7 @@ acpigen_pop_len(); } -static acpi_tstate_t *soc_get_tss_table(int *entries) +__attribute__ ((weak)) acpi_tstate_t *soc_get_tss_table(int *entries) { *entries = 0; return NULL; diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 927da3c..4a96560 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -63,6 +63,12 @@ acpi_cstate_t *soc_get_cstate_map(size_t *num_entries); /* + * get_tstate_map returns a table of processor specific acpi_tstate_t entries + * and number of entries in the table + */ +acpi_tstate_t *soc_get_tss_table(int *entries); + +/* * Chipset specific quirks for the wake enable bits. * Returns wake events for the soc. */ diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 58c4891..9b99f11 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -250,6 +250,30 @@ motherboard_fill_fadt(fadt); } +static acpi_tstate_t denverton_tss_table[] = { + { 100, 1000, 0, 0x00, 0 }, + { 88, 875, 0, 0x1e, 0 }, + { 75, 750, 0, 0x1c, 0 }, + { 63, 625, 0, 0x1a, 0 }, + { 50, 500, 0, 0x18, 0 }, + { 38, 375, 0, 0x16, 0 }, + { 25, 250, 0, 0x14, 0 }, + { 13, 125, 0, 0x12, 0 }, +}; + +acpi_tstate_t *soc_get_tss_table(int *entries) +{ + *entries = ARRAY_SIZE(denverton_tss_table); + return denverton_tss_table; +} + +void soc_power_states_generation(int core_id, int cores_per_package) +{ + generate_p_state_entries(core_id, cores_per_package); + + generate_t_state_entries(core_id, cores_per_package); +} + int soc_madt_sci_irq_polarity(int sci) { if (sci >= 20) -- To view, visit https://review.coreboot.org/25430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id9c7da474a81417a5cebd875023f7cd3d5a77796 Gerrit-Change-Number: 25430 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: soc/intel/common/block/acpi: fix P-States extra entry
by Julien Viard de Galbert (Code Review) 29 Mar '18

29 Mar '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25429 Change subject: soc/intel/common/block/acpi: fix P-States extra entry ...................................................................... soc/intel/common/block/acpi: fix P-States extra entry The ratio_max step is appearing twice when PSS_RATIO_STEP is 1 This is because in this case there are no rounding down of ratio_max in the for loop. Change-Id: I91090b4d87eb82b57055c24271d679d1cbb3b7a7 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/common/block/acpi/acpi.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/25429/1 diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index ae0617d..68fe944 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -324,7 +324,9 @@ /* Determine ratio points */ ratio_step = PSS_RATIO_STEP; - num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; + num_entries = ((ratio_max - ratio_min) / ratio_step); + if (PSS_RATIO_STEP != 1) + num_entries += 1; if (num_entries > PSS_MAX_ENTRIES) { ratio_step += 1; num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; -- To view, visit https://review.coreboot.org/25429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I91090b4d87eb82b57055c24271d679d1cbb3b7a7 Gerrit-Change-Number: 25429 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: soc/intel/denverton_ns: Enable ACPI using intelblock
by Julien Viard de Galbert (Code Review) 29 Mar '18

29 Mar '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25428 Change subject: soc/intel/denverton_ns: Enable ACPI using intelblock ...................................................................... soc/intel/denverton_ns: Enable ACPI using intelblock - Porting the existing denverton tables to intelblock - Adding C-States table for denverton Note: Removed code is functionally identical to corresponding common code. Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/mainboard/scaleway/tagada/acpi_tables.c M src/mainboard/scaleway/tagada/fadt.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/include/soc/acpi.h M src/soc/intel/denverton_ns/include/soc/nvs.h M src/soc/intel/denverton_ns/include/soc/pm.h M src/soc/intel/denverton_ns/include/soc/pmc.h 9 files changed, 90 insertions(+), 123 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/25428/1 diff --git a/src/mainboard/scaleway/tagada/acpi_tables.c b/src/mainboard/scaleway/tagada/acpi_tables.c index acbdb30..35bc4c2 100644 --- a/src/mainboard/scaleway/tagada/acpi_tables.c +++ b/src/mainboard/scaleway/tagada/acpi_tables.c @@ -29,6 +29,7 @@ #include <cpu/cpu.h> #include <cpu/x86/msr.h> +#include <intelblocks/acpi.h> #include <soc/acpi.h> #include <soc/nvs.h> @@ -45,17 +46,3 @@ /* TPM Present */ gnvs->tpmp = 0; } - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 2, - IO_APIC_ADDR, 0); - - current = acpi_madt_irq_overrides(current); - - return current; -} diff --git a/src/mainboard/scaleway/tagada/fadt.c b/src/mainboard/scaleway/tagada/fadt.c index 9f41f64..6259c2d 100644 --- a/src/mainboard/scaleway/tagada/fadt.c +++ b/src/mainboard/scaleway/tagada/fadt.c @@ -3,6 +3,7 @@ * * Copyright (C) 2007 - 2009 coresystems GmbH * Copyright (C) 2014 - 2017 Intel Corporation. + * Copyright (C) 2018 Online SAS * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,30 +22,8 @@ #include <soc/acpi.h> #include <soc/soc_util.h> -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +void motherboard_fill_fadt(acpi_fadt_t *fadt) { - acpi_header_t *header = &(fadt->header); - - memset((void *)fadt, 0, sizeof(acpi_fadt_t)); - memcpy_s(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy_s(header->oem_id, OEM_ID, 6); - memcpy_s(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy_s(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long)facs; - fadt->dsdt = (unsigned long)dsdt; fadt->model = 1; fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; - - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - acpi_fill_in_fadt(fadt); - - header->checksum = acpi_checksum((void *)fadt, header->length); } diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index bf4003d..ae0617d 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -31,7 +31,7 @@ #include <soc/nvs.h> #include <soc/pm.h> -unsigned long acpi_fill_mcfg(unsigned long current) +__attribute__((weak)) unsigned long acpi_fill_mcfg(unsigned long current) { /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ current += acpi_create_mcfg_mmconfig((void *)current, @@ -180,6 +180,7 @@ return generic_pm1_en; } +#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) /* * Save wake source information for calculating ACPI _SWS values * @@ -218,6 +219,7 @@ return GPE0_REG_MAX; } +#endif __attribute__ ((weak)) void acpi_create_gnvs(struct global_nvs_t *gnvs) { diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 303b1e5..b9b3159 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -44,8 +44,10 @@ select PARALLEL_MP select PCR_COMMON_IOSF_1_0 select SMP + select COMMON_FADT select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CPU + select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_PMC select ACPI_INTEL_HARDWARE_SLEEP_VALUES # select SOC_INTEL_COMMON_BLOCK_SA diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 433d611..58c4891 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -4,6 +4,7 @@ * Copyright (C) 2007 - 2009 coresystems GmbH * Copyright (C) 2013 Google Inc. * Copyright (C) 2014 - 2017 Intel Corporation. + * Copyright (C) 2018 Online SAS * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,12 +26,54 @@ #include <cpu/cpu.h> #include <cbmem.h> +#include <intelblocks/acpi.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/soc_util.h> #include <soc/pmc.h> #include <soc/systemagent.h> +#define MWAIT_RES(state, sub_state) \ + { \ + .addrl = (((state) << 4) | (sub_state)), \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ + .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ + } + +#define CSTATE_RES(address_space, width, offset, address) \ + { \ + .space_id = address_space, \ + .bit_width = width, \ + .bit_offset = offset, \ + .addrl = address, \ + } + +static acpi_cstate_t cstate_map[] = { + { + /* C1 */ + .ctype = 1, /* ACPI C1 */ + .latency = 2, + .power = 1000, + .resource = MWAIT_RES(0, 0), + }, + { + .ctype = 2, /* ACPI C2 */ + .latency = 10, + .power = 10, + .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, + ACPI_BASE_ADDRESS + 0x14), + }, + { + .ctype = 3, /* ACPI C3 */ + .latency = 50, + .power = 10, + .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, + ACPI_BASE_ADDRESS + 0x15), + } +}; + void acpi_init_gnvs(global_nvs_t *gnvs) { /* CPU core count */ @@ -53,36 +96,20 @@ gnvs->tsegl = (u32)(get_top_of_low_memory() - get_tseg_memory()); } -static int acpi_sci_irq(void) +uint32_t soc_read_sci_irq_select(void) { - int scis, sci_irq; device_t dev = get_pmc_dev(); if (!dev) return 0; - /* Determine how SCI is routed. */ - scis = pci_read_config32(dev, PMC_ACPI_CNT) & PMC_ACPI_CNT_SCIS_MASK; - switch (scis) { - case PMC_ACPI_CNT_SCIS_IRQ9: - case PMC_ACPI_CNT_SCIS_IRQ10: - case PMC_ACPI_CNT_SCIS_IRQ11: - sci_irq = scis - PMC_ACPI_CNT_SCIS_IRQ9 + 9; - break; - case PMC_ACPI_CNT_SCIS_IRQ20: - case PMC_ACPI_CNT_SCIS_IRQ21: - case PMC_ACPI_CNT_SCIS_IRQ22: - case PMC_ACPI_CNT_SCIS_IRQ23: - sci_irq = scis - PMC_ACPI_CNT_SCIS_IRQ20 + 20; - break; - default: - printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); - sci_irq = 9; - break; - } + return pci_read_config32(dev, PMC_ACPI_CNT); +} - printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); - return sci_irq; +acpi_cstate_t *soc_get_cstate_map(size_t *entries) +{ + *entries = ARRAY_SIZE(cstate_map); + return cstate_map; } unsigned long acpi_fill_mcfg(unsigned long current) @@ -103,16 +130,17 @@ return current; } -void acpi_fill_in_fadt(acpi_fadt_t *fadt) +__attribute__ ((weak)) void motherboard_fill_fadt(acpi_fadt_t *fadt) +{ +} + +void soc_fill_fadt(acpi_fadt_t *fadt) { u16 pmbase = get_pmbase(); /* System Management */ - fadt->sci_int = acpi_sci_irq(); #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + // done in common code #else fadt->smi_cmd = 0x00; fadt->acpi_enable = 0x00; @@ -120,21 +148,11 @@ #endif /* Power Control */ - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x0; fadt->pm2_cnt_blk = pmbase + PM2_CNT; fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS(0); fadt->gpe1_blk = 0; /* Control Registers - Length */ - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 8; @@ -228,53 +246,16 @@ fadt->x_gpe1_blk.access_size = 0; fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; fadt->x_gpe1_blk.addrh = 0x00; + + motherboard_fill_fadt(fadt); } -void generate_cpu_entries(device_t device) +int soc_madt_sci_irq_polarity(int sci) { - int core; - int pcontrol_blk = get_pmbase(), plen = 6; - int num_cpus = get_cpu_count(); - - for (core = 0; core < num_cpus; core++) { - if (core > 0) { - pcontrol_blk = 0; - plen = 0; - } - - /* Generate processor \_PR.CPUx */ - acpigen_write_processor(core, pcontrol_blk, plen); - - /* Generate P-state tables */ - - /* Generate C-state tables */ - - /* Generate T-state tables */ - - acpigen_pop_len(); - } -} - -unsigned long acpi_madt_irq_overrides(unsigned long current) -{ - int sci_irq = acpi_sci_irq(); - acpi_madt_irqoverride_t *irqovr; - uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL; - - /* INT_SRC_OVR */ - irqovr = (acpi_madt_irqoverride_t *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); - - if (sci_irq >= 20) - sci_flags |= MP_IRQ_POLARITY_LOW; + if (sci >= 20) + return MP_IRQ_POLARITY_LOW; else - sci_flags |= MP_IRQ_POLARITY_HIGH; - - irqovr = (acpi_madt_irqoverride_t *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, (u8)sci_irq, sci_irq, - sci_flags); - - return current; + return MP_IRQ_POLARITY_HIGH; } unsigned long southcluster_write_acpi_tables(device_t device, diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h index dd2be4d..588994d 100644 --- a/src/soc/intel/denverton_ns/include/soc/acpi.h +++ b/src/soc/intel/denverton_ns/include/soc/acpi.h @@ -23,12 +23,12 @@ void acpi_create_intel_hpet(acpi_hpet_t *hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); -void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); unsigned long southcluster_write_acpi_tables(device_t device, unsigned long current, struct acpi_rsdp *rsdp); void southcluster_inject_dsdt(device_t device); +void motherboard_fill_fadt(acpi_fadt_t *fadt); #endif /* _DENVERTON_NS_ACPI_H_ */ diff --git a/src/soc/intel/denverton_ns/include/soc/nvs.h b/src/soc/intel/denverton_ns/include/soc/nvs.h index cf10823..5a94b24 100644 --- a/src/soc/intel/denverton_ns/include/soc/nvs.h +++ b/src/soc/intel/denverton_ns/include/soc/nvs.h @@ -19,7 +19,7 @@ #ifndef _DENVERTON_NS_NVS_H_ #define _DENVERTON_NS_NVS_H_ -typedef struct { +typedef struct global_nvs_t { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -63,9 +63,8 @@ u32 tsegl; /* 0x58 - TSEG Length/Size */ u8 rsvd3[164]; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; -void acpi_create_gnvs(global_nvs_t *gnvs); #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h index e44d942..3f9cc4e 100644 --- a/src/soc/intel/denverton_ns/include/soc/pm.h +++ b/src/soc/intel/denverton_ns/include/soc/pm.h @@ -25,6 +25,12 @@ /* TODO: Check that */ #define GPE_MAX 127 +/* P-state configuration */ +#define PSS_MAX_ENTRIES 15 +#define PSS_RATIO_STEP 1 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + struct chipset_power_state { uint16_t pm1_sts; uint16_t pm1_en; diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index 4db3981..f5df21a 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -38,6 +38,17 @@ #define PMC_ACPI_CNT_SCIS_IRQ21 0x05 #define PMC_ACPI_CNT_SCIS_IRQ22 0x06 #define PMC_ACPI_CNT_SCIS_IRQ23 0x07 + +#define SCI_IRQ_ADJUST 0 +#define SCI_IRQ_SEL (0x07 << SCI_IRQ_ADJUST) +#define SCIS_IRQ9 0x00 +#define SCIS_IRQ10 0x01 +#define SCIS_IRQ11 0x02 +#define SCIS_IRQ20 0x04 +#define SCIS_IRQ21 0x05 +#define SCIS_IRQ22 0x06 +#define SCIS_IRQ23 0x07 + #define PMC_PWRM_BASE 0x48 /* MEM BAR */ #define MASK_PMC_PWRM_BASE 0xfffff000 /* 4K alignment */ #define PMC_GEN_PMCON_A 0xA0 -- To view, visit https://review.coreboot.org/25428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399 Gerrit-Change-Number: 25428 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: soc/intel/denverton_ns: Rewrite pmutil using pmclib
by Julien Viard de Galbert (Code Review) 29 Mar '18

29 Mar '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25427 Change subject: soc/intel/denverton_ns: Rewrite pmutil using pmclib ...................................................................... soc/intel/denverton_ns: Rewrite pmutil using pmclib Change-Id: If31e7102bf1b47c7ae94b86d981b762eda0a19e5 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/denverton_ns/include/soc/pm.h M src/soc/intel/denverton_ns/pmutil.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/denverton_ns/smm.c 5 files changed, 34 insertions(+), 184 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/25427/1 diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 6492248..b9ff969 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -202,6 +202,7 @@ { static const char *const pm1_sts_bits[] = { [0] = "TMROF", + [4] = "BM", [5] = "GBL", [8] = "PWRBTN", [10] = "RTC", diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h index 5978b3a..e44d942 100644 --- a/src/soc/intel/denverton_ns/include/soc/pm.h +++ b/src/soc/intel/denverton_ns/include/soc/pm.h @@ -42,18 +42,6 @@ struct chipset_power_state *fill_power_state(void); /* Power Management Utility Functions. */ -uint32_t clear_smi_status(void); -uint16_t clear_pm1_status(void); -uint32_t clear_tco_status(void); -uint32_t clear_gpe_status(void); void clear_pmc_status(void); -void enable_smi(uint32_t mask); -void disable_smi(uint32_t mask); -void enable_pm1(uint16_t events); -void enable_pm1_control(uint32_t mask); -void disable_pm1_control(uint32_t mask); -void enable_gpe(uint32_t mask); -void disable_gpe(uint32_t mask); -void disable_all_gpe(void); #endif /* _DENVERTON_NS_PM_H_ */ diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c index 6eb7db8..0d19644 100644 --- a/src/soc/intel/denverton_ns/pmutil.c +++ b/src/soc/intel/denverton_ns/pmutil.c @@ -19,29 +19,12 @@ #include <arch/io.h> #include <console/console.h> +#include <intelblocks/pmclib.h> #include <soc/iomap.h> #include <soc/soc_util.h> #include <soc/pm.h> -static void print_num_status_bits(int num_bits, uint32_t status, - const char * const bit_names[]) -{ - int i; - - if (!status) - return; - - for (i = num_bits - 1; i >= 0; i--) { - if (status & (1 << i)) { - if (bit_names[i]) - printk(BIOS_DEBUG, "%s ", bit_names[i]); - else - printk(BIOS_DEBUG, "BIT%d ", i); - } - } -} - -static uint32_t print_smi_status(uint32_t smi_sts) +const char *const *soc_smi_sts_array(size_t *a) { static const char * const smi_sts_bits[] = { [2] = "BIOS", @@ -67,93 +50,11 @@ [31] = "LEGACY_USB3", }; - if (!smi_sts) - return 0; - - printk(BIOS_DEBUG, "SMI_STS: "); - print_num_status_bits(ARRAY_SIZE(smi_sts_bits), smi_sts, smi_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return smi_sts; + *a = ARRAY_SIZE(smi_sts_bits); + return smi_sts_bits; } -static uint32_t reset_smi_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint32_t smi_sts = inl((uint16_t)(pmbase + SMI_STS)); - outl(smi_sts, (uint16_t)(pmbase + SMI_STS)); - return smi_sts; -} - -uint32_t clear_smi_status(void) { return print_smi_status(reset_smi_status()); } - -void enable_smi(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN)); - smi_en |= mask; - outl(smi_en, (uint16_t)(pmbase + SMI_EN)); -} - -void disable_smi(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN)); - smi_en &= ~mask; - outl(smi_en, (uint16_t)(pmbase + SMI_EN)); -} - -void enable_pm1_control(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT)); - pm1_cnt |= mask; - outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT)); -} - -void disable_pm1_control(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT)); - pm1_cnt &= ~mask; - outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT)); -} - -static uint16_t reset_pm1_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint16_t pm1_sts = inw((uint16_t)(pmbase + PM1_STS)); - outw(pm1_sts, (uint16_t)(pmbase + PM1_STS)); - return pm1_sts; -} - -static uint16_t print_pm1_status(uint16_t pm1_sts) -{ - static const char * const pm1_sts_bits[] = { - [0] = "TMROF", [4] = "BM", [5] = "GBL", - [8] = "PWRBTN", [10] = "RTC", [11] = "PRBTNOR", - [15] = "WAK", - }; - - if (!pm1_sts) - return 0; - - printk(BIOS_SPEW, "PM1_STS: "); - print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits); - printk(BIOS_SPEW, "\n"); - - return pm1_sts; -} - -uint16_t clear_pm1_status(void) { return print_pm1_status(reset_pm1_status()); } - -void enable_pm1(uint16_t events) -{ - uint16_t pmbase = get_pmbase(); - outw(events, (uint16_t)(pmbase + PM1_EN)); -} - -static uint32_t print_tco_status(uint32_t tco_sts) +const char *const *soc_tco_sts_array(size_t *a) { static const char * const tco_sts_bits[] = { [0] = "NMI2SMI", [1] = "OS_TCO_SMI", @@ -164,17 +65,11 @@ [17] = "SECOND_TO", [20] = "SMLINK_SLV_SMI", }; - if (!tco_sts) - return 0; - - printk(BIOS_DEBUG, "TCO_STS: "); - print_num_status_bits(ARRAY_SIZE(tco_sts_bits), tco_sts, tco_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return tco_sts; + *a = ARRAY_SIZE(tco_sts_bits); + return tco_sts_bits; } -static uint32_t reset_tco_status(void) +uint32_t soc_reset_tco_status(void) { uint16_t tcobase = get_tcobase(); uint32_t tco_sts = inl((uint16_t)(tcobase + TCO1_STS)); @@ -184,35 +79,7 @@ return tco_sts & tco_en; } -uint32_t clear_tco_status(void) { return print_tco_status(reset_tco_status()); } - -void enable_gpe(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD))); - gpe0_en |= mask; - outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD))); -} - -void disable_gpe(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD))); - gpe0_en &= ~mask; - outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD))); -} - -void disable_all_gpe(void) { disable_gpe(~0); } - -static uint32_t reset_gpe_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS(GPE_STD))); - outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS(GPE_STD))); - return gpe_sts; -} - -static uint32_t print_gpe_sts(uint32_t gpe_sts) +const char *const *soc_std_gpe_sts_array(size_t *a) { static const char * const gpe_sts_bits[] = { [0] = "GPIO_0", [1] = "GPIO_1", @@ -233,16 +100,8 @@ [30] = "GPIO_30", [31] = "GPIO_31", }; - if (!gpe_sts) - return gpe_sts; - - printk(BIOS_DEBUG, "GPE0a_STS: "); - print_num_status_bits(ARRAY_SIZE(gpe_sts_bits), gpe_sts, gpe_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return gpe_sts; + *a = ARRAY_SIZE(gpe_sts_bits); + return gpe_sts_bits; } -uint32_t clear_gpe_status(void) { return print_gpe_sts(reset_gpe_status()); } - void clear_pmc_status(void) { /* TODO */ } diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index e434c1c..6fb3ba1 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -25,6 +25,7 @@ #include <device/pci_def.h> #include <elog.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/pmclib.h> #include <spi-generic.h> #include <soc/iomap.h> #include <soc/soc_util.h> @@ -52,7 +53,7 @@ return 0; } -void southbridge_smi_set_eos(void) { enable_smi(EOS); } +void southbridge_smi_set_eos(void) { pmc_enable_smi(EOS); } global_nvs_t *smm_get_gnvs(void) { return gnvs; } @@ -98,7 +99,7 @@ uint16_t pmbase = get_pmbase(); /* First, disable further SMIs */ - disable_smi(SLP_SMI_EN); + pmc_disable_smi(SLP_SMI_EN); /* Figure out SLP_TYP */ reg32 = inl((uint16_t)(pmbase + PM1_CNT)); @@ -131,7 +132,7 @@ printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); /* Disable all GPE */ - disable_all_gpe(); + pmc_disable_all_gpe(); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); @@ -145,7 +146,7 @@ * event again. We need to set BIT13 (SLP_EN) though to make the * sleep happen. */ - enable_pm1_control(SLP_EN); + pmc_enable_pm1_control(SLP_EN); /* Make sure to stop executing code here for S3/S4/S5 */ if (slp_typ > 1) @@ -158,7 +159,7 @@ reg32 = inl((uint16_t)(pmbase + PM1_CNT)); if (reg32 & SCI_EN) { /* The OS is not an ACPI OS, so we set the state to S0 */ - disable_pm1_control(SLP_EN | SLP_TYP); + pmc_disable_pm1_control(SLP_EN | SLP_TYP); } } @@ -237,11 +238,11 @@ printk(BIOS_DEBUG, "P-state control\n"); break; case APM_CNT_ACPI_DISABLE: - disable_pm1_control(SCI_EN); + pmc_disable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case APM_CNT_ACPI_ENABLE: - enable_pm1_control(SCI_EN); + pmc_enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; case APM_CNT_FINALIZE: @@ -268,23 +269,23 @@ static void southbridge_smi_pm1(void) { - uint16_t pm1_sts = clear_pm1_status(); + uint16_t pm1_sts = pmc_clear_pm1_status(); /* While OSPM is not active, poweroff immediately * on a power button event. */ if (pm1_sts & PWRBTN_STS) { // power button pressed - disable_pm1_control(-1UL); - enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); + pmc_disable_pm1_control(-1UL); + pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); } } -static void southbridge_smi_gpe0(void) { clear_gpe_status(); } +static void southbridge_smi_gpe0(void) { pmc_clear_all_gpe_status(); } static void southbridge_smi_tco(void) { - uint32_t tco_sts = clear_tco_status(); + uint32_t tco_sts = pmc_clear_tco_status(); /* Any TCO event? */ if (!tco_sts) @@ -354,7 +355,7 @@ /* We need to clear the SMI status registers, or we won't see what's * happening in the following calls. */ - smi_sts = clear_smi_status(); + smi_sts = pmc_clear_smi_status(); /* Call SMI sub handler for each of the status bits */ for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) { diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c index 732aed4..078ffd2 100644 --- a/src/soc/intel/denverton_ns/smm.c +++ b/src/soc/intel/denverton_ns/smm.c @@ -24,6 +24,7 @@ #include <cpu/x86/smm.h> #include <string.h> +#include <intelblocks/pmclib.h> #include <soc/iomap.h> #include <soc/soc_util.h> #include <soc/pm.h> @@ -49,10 +50,10 @@ } /* Dump and clear status registers */ - clear_smi_status(); - clear_pm1_status(); - clear_tco_status(); - clear_gpe_status(); + pmc_clear_smi_status(); + pmc_clear_pm1_status(); + pmc_clear_tco_status(); + pmc_clear_all_gpe_status(); clear_pmc_status(); } @@ -61,8 +62,8 @@ printk(BIOS_DEBUG, "Enabling SMIs.\n"); /* Configure events Disable pcie wake. */ - enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); - disable_gpe(PME_B0_EN); + pmc_enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); + pmc_disable_std_gpe(PME_B0_EN); /* Enable SMI generation: * - on APMC writes (io 0xb2) @@ -72,7 +73,7 @@ * - on TCO events * - on microcontroller writes (io 0x62/0x66) */ - enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); + pmc_enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); } void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -- To view, visit https://review.coreboot.org/25427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If31e7102bf1b47c7ae94b86d981b762eda0a19e5 Gerrit-Change-Number: 25427 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: soc/intel/denverton: Enable common block PMC
by Julien Viard de Galbert (Code Review) 29 Mar '18

29 Mar '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25426 Change subject: soc/intel/denverton: Enable common block PMC ...................................................................... soc/intel/denverton: Enable common block PMC Mainly updating headers to build. Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/include/soc/iomap.h M src/soc/intel/denverton_ns/include/soc/pm.h M src/soc/intel/denverton_ns/include/soc/pmc.h M src/soc/intel/denverton_ns/pmutil.c 7 files changed, 28 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/25426/1 diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index cf87d05..6492248 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -454,6 +454,7 @@ return ps->prev_sleep_state; } +#ifdef ETR /* * If possible, lock 0xcf9. Once the register is locked, it can't be changed. * This lock is reset on cold boot, hard reset, soft reset and Sx. @@ -486,6 +487,7 @@ reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST; write32((void *)etr, reg); } +#endif int vboot_platform_is_resuming(void) { diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 35296d5..303b1e5 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -46,6 +46,8 @@ select SMP select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CPU + select SOC_INTEL_COMMON_BLOCK_PMC + select ACPI_INTEL_HARDWARE_SLEEP_VALUES # select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 7386db3..433d611 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -129,7 +129,7 @@ fadt->pm1b_cnt_blk = 0x0; fadt->pm2_cnt_blk = pmbase + PM2_CNT; fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS; + fadt->gpe0_blk = pmbase + GPE0_STS(0); fadt->gpe1_blk = 0; /* Control Registers - Length */ diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h index 29b231f..a7548d4 100644 --- a/src/soc/intel/denverton_ns/include/soc/iomap.h +++ b/src/soc/intel/denverton_ns/include/soc/iomap.h @@ -29,6 +29,7 @@ /* Southbridge internal device IO BARs (Set to match FSP settings) */ #define DEFAULT_PMBASE 0x1800 #define DEFAULT_ACPI_BASE DEFAULT_PMBASE +#define ACPI_BASE_ADDRESS DEFAULT_PMBASE #define DEFAULT_TCO_BASE 0x400 /* Southbridge internal device MEM BARs (Set to match FSP settings) */ diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h index 2dc8781..5978b3a 100644 --- a/src/soc/intel/denverton_ns/include/soc/pm.h +++ b/src/soc/intel/denverton_ns/include/soc/pm.h @@ -20,10 +20,10 @@ #include <arch/io.h> #include <soc/pmc.h> +#include <arch/acpi.h> -#define SLEEP_STATE_S0 0 -#define SLEEP_STATE_S3 3 -#define SLEEP_STATE_S5 5 +/* TODO: Check that */ +#define GPE_MAX 127 struct chipset_power_state { uint16_t pm1_sts; @@ -31,8 +31,8 @@ uint32_t pm1_cnt; uint16_t tco1_sts; uint16_t tco2_sts; - uint32_t gpe0_sts[4]; - uint32_t gpe0_en[4]; + uint32_t gpe0_sts[GPE0_REG_MAX]; + uint32_t gpe0_en[GPE0_REG_MAX]; uint32_t gen_pmcon_a; uint32_t gen_pmcon_b; uint32_t gblrst_cause[2]; diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index edb5c55..4db3981 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -120,7 +120,10 @@ #define GPE_CTRL 0x40 #define SWGPE_CTRL (1 << 17) #define PM2_CNT 0x50 -#define GPE0_STS 0x80 +#define GPE0_REG_MAX 4 +#define GPE0_REG_SIZE 32 +#define GPE0_STS(x) (0x80 + (x * 4)) +#define GPE_STD 0 #define GPIO31_STS (1 << 31) #define GPIO30_STS (1 << 30) #define GPIO29_STS (1 << 29) @@ -166,7 +169,7 @@ #define IE_SCI_STS (1 << 3) #define SWGPE_STS (1 << 2) #define HOT_PLUG_STS (1 << 1) -#define GPE0_EN 0x90 +#define GPE0_EN(x) (0x90 + (x * 4)) #define GPIO31_EN (1 << 31) #define GPIO30_EN (1 << 30) #define GPIO29_EN (1 << 29) @@ -236,6 +239,12 @@ #define TCO2_CNT 0x0a #define TCO_TMR 0x12 +/* Memory mapped IO registers behind PMC_BASE_ADDRESS */ +#define PRSTS 0x10 +#define GPIO_GPE_CFG 0x120 +#define GPE0_DWX_MASK 0x7 +#define GPE0_DW_SHIFT(x) (4 + 4*(x)) + /* I/O ports */ #define RST_CNT 0xcf9 #define FULL_RST (1 << 3) diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c index 542997c..6eb7db8 100644 --- a/src/soc/intel/denverton_ns/pmutil.c +++ b/src/soc/intel/denverton_ns/pmutil.c @@ -189,17 +189,17 @@ void enable_gpe(uint32_t mask) { uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN)); + uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD))); gpe0_en |= mask; - outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN)); + outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD))); } void disable_gpe(uint32_t mask) { uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN)); + uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD))); gpe0_en &= ~mask; - outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN)); + outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD))); } void disable_all_gpe(void) { disable_gpe(~0); } @@ -207,8 +207,8 @@ static uint32_t reset_gpe_status(void) { uint16_t pmbase = get_pmbase(); - uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS)); - outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS)); + uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS(GPE_STD))); + outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS(GPE_STD))); return gpe_sts; } -- To view, visit https://review.coreboot.org/25426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd Gerrit-Change-Number: 25426 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: soc/intel/skylake: ME status value is over status array boundary
by build bot (Jenkins) (Code Review) 29 Mar '18

29 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25425 ) Change subject: soc/intel/skylake: ME status value is over status array boundary ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69194/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23543/ : SUCCESS -- To view, visit https://review.coreboot.org/25425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5de569c62b94b0595d3d3ea254f50e312e8c11a4 Gerrit-Change-Number: 25425 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Mar 2018 11:56:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: soc/intel/skylake: ME status value is over status array boundary
by Kane Chen (Code Review) 29 Mar '18

29 Mar '18

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/25425 Change subject: soc/intel/skylake: ME status value is over status array boundary ...................................................................... soc/intel/skylake: ME status value is over status array boundary me_progress_rom_values array provides detailed information maps to ME HFSTS2 register value. There is a chance that ME status value might be over the size of me_progress_rom_values. This commit adds a check before access the array. BUG=b:77247550 Change-Id: I5de569c62b94b0595d3d3ea254f50e312e8c11a4 Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/soc/intel/skylake/me.c 1 file changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/25425/1 diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index 9a721bc..a23172e 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -346,8 +346,14 @@ printk(BIOS_DEBUG, "ME: Progress Phase State : "); switch (hfs2.fields.progress_code) { case ME_HFS2_PHASE_ROM: /* ROM Phase */ - printk(BIOS_DEBUG, "%s", - me_progress_rom_values[hfs2.fields.current_state]); + if (hfs2.fields.current_state + < ARRAY_SIZE(me_progress_rom_values) + && me_progress_rom_values[hfs2.fields.current_state]) + printk(BIOS_DEBUG, "%s", + me_progress_rom_values[ + hfs2.fields.current_state]); + else + printk(BIOS_DEBUG, "0x%02x", hfs2.fields.current_state); break; case ME_HFS2_PHASE_UKERNEL: /* uKernel Phase */ -- To view, visit https://review.coreboot.org/25425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5de569c62b94b0595d3d3ea254f50e312e8c11a4 Gerrit-Change-Number: 25425 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com>

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Change in coreboot[master]: [WIP] driver/option_table: add option table interface
by build bot (Jenkins) (Code Review) 29 Mar '18

29 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25397 ) Change subject: [WIP] driver/option_table: add option table interface ...................................................................... Patch Set 3: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/69193/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/23542/ : SUCCESS -- To view, visit https://review.coreboot.org/25397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I19b0215170e940c4973e60cbad3d7186a3063cc2 Gerrit-Change-Number: 25397 Gerrit-PatchSet: 3 Gerrit-Owner: Marcello Sylvester Bauer <marcello.bauer(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Mar 2018 11:44:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [wip] driver/option_table: add option table interface
by build bot (Jenkins) (Code Review) 29 Mar '18

29 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25397 ) Change subject: [wip] driver/option_table: add option table interface ...................................................................... Patch Set 2: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/69192/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/23541/ : SUCCESS -- To view, visit https://review.coreboot.org/25397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I19b0215170e940c4973e60cbad3d7186a3063cc2 Gerrit-Change-Number: 25397 Gerrit-PatchSet: 2 Gerrit-Owner: Marcello Sylvester Bauer <marcello.bauer(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Mar 2018 11:30:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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