coreboot-gerrit March 2018

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Change in coreboot[master]: soc/intel/denverton_ns: Lock SPIBAR
by Julien Viard de Galbert (Code Review) 29 Mar '18

29 Mar '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25441 Change subject: soc/intel/denverton_ns: Lock SPIBAR ...................................................................... soc/intel/denverton_ns: Lock SPIBAR Allow flash access when "Security Override" is set. Don't lock when relax_security is set. Change-Id: I6934918d0c70245f03a1642f9a05e0110a205bc9 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/denverton_ns/lpc.c 2 files changed, 58 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/25441/1 diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index a389e34..324006d 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -37,7 +37,7 @@ #define SPIBAR_DLOCK 0x0c #define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4) #define SPIBAR_FPR_BASE 0x84 -#define SPIBAR_FPR(n) 0x84 + (4 * n)) +#define SPIBAR_FPR(n) (0x84 + (4 * n)) #define SPIBAR_PREOP 0xA4 #define SPIBAR_OPTYPE 0xA6 #define SPIBAR_OPMENU_LOWER 0xA8 @@ -71,6 +71,7 @@ #define SPIBAR_HSFSTS_FLOCKDN (1 << 15) #define SPIBAR_HSFSTS_FDV (1 << 14) #define SPIBAR_HSFSTS_FDOPSS (1 << 13) +#define SPIBAR_HSFSTS_PRR34_LOCKDN (1 << 12) #define SPIBAR_HSFSTS_WRSDIS (1 << 11) #define SPIBAR_HSFSTS_SAF_CE (1 << 8) #define SPIBAR_HSFSTS_SAF_ACTIVE (1 << 7) diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 1ac0961..8f2542a 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 - 2017 Intel Corporation. + * Copyright (C) 2018 Online SAS * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,6 +26,7 @@ #include <cpu/x86/smm.h> #include <bootstate.h> +#include <fsp/api.h> #include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> @@ -32,6 +34,10 @@ #include <soc/pcr.h> #include <soc/p2sb.h> #include <soc/acpi.h> +#include <fast_spi_def.h> +#include <intelblocks/fast_spi.h> +#include <spi_flash.h> +#include <spi-generic.h> #include "chip.h" @@ -326,8 +332,58 @@ .device = LPC_DEVID, }; +static void spi_lock_bar(bool relax_security) +{ + void *spibar = fast_spi_get_bar(); + uint32_t reg32, hsfs; + /* Check SPIBAR */ + hsfs = read32(spibar + SPIBAR_HSFSTS_CTL); + if (!(hsfs & SPIBAR_HSFSTS_FDOPSS)) { + /* When the flash security override strap is set, allow flashrom + to update the flash, this is done by clearing the protection + and locking the configuration to ensure FSP notify will not + change it again */ + int i; + struct device *dev; + printk(BIOS_CRIT, "FLASH SECURITY OVERRIDE SET:" + "DISABLE FLASH PROTECTIONS!\n"); + + /* disable protections FPR0-4 + GPR0 */ + for (i = 0; i < 6; i++) + write32(spibar + SPIBAR_FPR(i), 0); + + /* Disable WPD and EISS */ + dev = dev_find_slot(0, PCI_DEVFN(SPI_DEV, SPI_FUNC)); + if (dev != NULL) { + reg32 = pci_read_config32(dev, SPIBAR_BIOS_CONTROL); + reg32 &= ~(SPIBAR_BIOS_CONTROL_EISS | + SPIBAR_BIOS_CONTROL_WPD); + /* lock to ensure FSP cannot change it */ + if (!relax_security) + reg32 |= SPIBAR_BIOS_CONTROL_LOCK_ENABLE | + SPIBAR_BIOS_CONTROL_BILD; + pci_write_config32(dev, SPIBAR_BIOS_CONTROL, reg32); + } + } + + if (!relax_security) { + /* Lock SPIBAR */ + hsfs |= SPIBAR_HSFSTS_FLOCKDN | SPIBAR_HSFSTS_PRR34_LOCKDN; + reg32 = read32(spibar + SPIBAR_DLOCK); + reg32 |= 0x11f0f; + write32(spibar + SPIBAR_DLOCK, reg32); + + write32(spibar + SPIBAR_HSFSTS_CTL, hsfs); + } + +} + static void finalize_chipset(void *unused) { + bool relax_security = fsp_relax_security(); + + spi_lock_bar(relax_security); + printk(BIOS_DEBUG, "Finalizing SMM.\n"); outb(APM_CNT_FINALIZE, APM_CNT); } -- To view, visit https://review.coreboot.org/25441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6934918d0c70245f03a1642f9a05e0110a205bc9 Gerrit-Change-Number: 25441 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: soc/intel/denverton_ns: Implement AES-NI Lock
by Julien Viard de Galbert (Code Review) 29 Mar '18

29 Mar '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25440 Change subject: soc/intel/denverton_ns: Implement AES-NI Lock ...................................................................... soc/intel/denverton_ns: Implement AES-NI Lock Change-Id: I6cf3484e46eebd3dc753d0903ea8555712b99b7e Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/denverton_ns/include/soc/msr.h 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/25440/1 diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index ede4dae..d22cc58 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -107,6 +107,13 @@ msr.lo |= FAST_STRINGS_ENABLE_BIT; wrmsr(IA32_MISC_ENABLE, msr); + /* Lock AES-NI only if supported */ + if (cpuid_ecx(1) & (1 << 25)) { + msr = rdmsr(MSR_FEATURE_CONFIG); + msr.lo |= FEATURE_CONFIG_LOCK; /* Lock AES-NI */ + wrmsr(MSR_FEATURE_CONFIG, msr); + } + /* Enable Turbo */ enable_turbo(); diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 05ccc65..cc2e26e 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -29,6 +29,8 @@ #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_FEATURE_CONFIG 0x13c +#define FEATURE_CONFIG_RESERVED_MASK 0x3ULL +#define FEATURE_CONFIG_LOCK (1 << 0) #define IA32_MCG_CAP 0x179 #define IA32_MCG_CAP_COUNT_MASK 0xff #define IA32_MCG_CAP_CTL_P_BIT 8 -- To view, visit https://review.coreboot.org/25440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6cf3484e46eebd3dc753d0903ea8555712b99b7e Gerrit-Change-Number: 25440 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: soc/intel/denverton_ns: Initialize thermal configuration
by Julien Viard de Galbert (Code Review) 29 Mar '18

29 Mar '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25439 Change subject: soc/intel/denverton_ns: Initialize thermal configuration ...................................................................... soc/intel/denverton_ns: Initialize thermal configuration Change-Id: I7e1b924154256f8f82ded3d0fa155b3e836d9375 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/denverton_ns/cpu.c 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/25439/1 diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 4434964..ede4dae 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -67,6 +67,29 @@ write_cr4(read_cr4() | CR4_MCE); } +static void configure_thermal_core(void) +{ + msr_t msr; + struct cpuid_result cpuid_regs; + + /* Disable Thermal interrupts */ + msr.lo = 0; + msr.hi = 0; + wrmsr(IA32_THERM_INTERRUPT, msr); + + /* Disable Thermal interrupts */ + msr.lo = 0; + msr.hi = 0; + wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); + + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo &= (1 << 3); /* Clear TM enable */ + cpuid_regs = cpuid(1); + if (cpuid_regs.edx & (1 << 29)) + msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ + wrmsr(IA32_MISC_ENABLE, msr); +} + static void denverton_core_init(device_t cpu) { msr_t msr; @@ -76,6 +99,9 @@ /* Clear out pending MCEs */ dnv_configure_mca(); + /* Configure Thermal Sensors */ + configure_thermal_core(); + /* Enable Fast Strings */ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= FAST_STRINGS_ENABLE_BIT; -- To view, visit https://review.coreboot.org/25439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7e1b924154256f8f82ded3d0fa155b3e836d9375 Gerrit-Change-Number: 25439 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: mb/scaleway/tagada: Use bmcInfo to enable Relaxed Security Mode
by Julien Viard de Galbert (Code Review) 29 Mar '18

29 Mar '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25438 Change subject: mb/scaleway/tagada: Use bmcInfo to enable Relaxed Security Mode ...................................................................... mb/scaleway/tagada: Use bmcInfo to enable Relaxed Security Mode Change-Id: Id3a51452d587556c3fd671a0e28a65e940d6e8cb Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/mainboard/scaleway/tagada/bmcinfo.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/25438/1 diff --git a/src/mainboard/scaleway/tagada/bmcinfo.c b/src/mainboard/scaleway/tagada/bmcinfo.c index 5ca7369..44fb15a 100644 --- a/src/mainboard/scaleway/tagada/bmcinfo.c +++ b/src/mainboard/scaleway/tagada/bmcinfo.c @@ -21,6 +21,7 @@ #include <console/console.h> #include <console/uart.h> +#include <fsp/api.h> #include "bmcinfo.h" @@ -207,3 +208,9 @@ return bmcinfo_coreboot_verbosity_level(); } #endif + +/* Override fsp_relax_security */ +bool fsp_relax_security(void) +{ + return bmcinfo_relax_security(); +} -- To view, visit https://review.coreboot.org/25438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id3a51452d587556c3fd671a0e28a65e940d6e8cb Gerrit-Change-Number: 25438 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: FSP 2.0: Add fsp_relax_security
by Julien Viard de Galbert (Code Review) 29 Mar '18

29 Mar '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25437 Change subject: FSP 2.0: Add fsp_relax_security ...................................................................... FSP 2.0: Add fsp_relax_security Change-Id: I972e7387c2612ee0053df21afb55b0b264961174 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/notify.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/25437/1 diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 123db30..66e4291 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -62,6 +62,10 @@ uint8_t fsp_memory_mainboard_version(void); uint8_t fsp_memory_soc_version(void); +/* The following function is used to allow not calling FSP notify in + READY_TO_BOOT and END_OF_FIRMWARE phases. */ +bool fsp_relax_security(void); + /* Callback after processing FSP notify */ void platform_fsp_notify_status(enum fsp_notify_phase phase); diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 34a4262..3d18e83 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -67,10 +67,21 @@ platform_fsp_notify_status(phase); } +__attribute__((weak)) bool fsp_relax_security(void) +{ + return false; +} + static void fsp_notify_dummy(void *arg) { enum fsp_notify_phase phase = (uint32_t)arg; + if ((phase == READY_TO_BOOT) && fsp_relax_security()) { + printk(BIOS_CRIT, "Relax Security Mode," + " do not use in production!\n"); + return; + } + /* Display the MTRRs */ if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) soc_display_mtrrs(); -- To view, visit https://review.coreboot.org/25437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I972e7387c2612ee0053df21afb55b0b264961174 Gerrit-Change-Number: 25437 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes
by Julien Viard de Galbert (Code Review) 29 Mar '18

29 Mar '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25436 Change subject: mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes ...................................................................... mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes Change-Id: Ic3ed97fc2b54d4974ec0b41b9f207fe3d49d2cce Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- A src/mainboard/scaleway/tagada/gpio_defs.h M src/mainboard/scaleway/tagada/hsio.c M src/mainboard/scaleway/tagada/hsio.h 3 files changed, 103 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/25436/1 diff --git a/src/mainboard/scaleway/tagada/gpio_defs.h b/src/mainboard/scaleway/tagada/gpio_defs.h new file mode 100644 index 0000000..6c1ac1c --- /dev/null +++ b/src/mainboard/scaleway/tagada/gpio_defs.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 - 2018 Online SAS + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _MAINBOARD_GPIO_DEFS_H +#define _MAINBOARD_GPIO_DEFS_H + +#include <soc/gpio_defs.h> + +// _GPIO_0 : LFFF: DVT_GPIO<0> : BOOTED +#define GPIO_GPIO_0 0 +#define R_PAD_CFG_DW0_GPIO_0 0x4d8 +#define PID_GPIO_0 PID_NorthCommunity + +// _GPIO_4 : LFFF: M2A_CFGn : M2A_SATAn +#define GPIO_GPIO_4 4 +#define R_PAD_CFG_DW0_GPIO_4 0x568 +#define PID_GPIO_4 PID_SouthCommunity + +// _GPIO_5 : LFFF: M2B_CFGn : M2B_SATAn +#define GPIO_GPIO_5 5 +#define R_PAD_CFG_DW0_GPIO_5 0x570 +#define PID_GPIO_5 PID_SouthCommunity + + +// _GPIO_8 : LFFF: DVT_GPIO<1> : Baud select +#define GPIO_GPIO_8 8 +#define R_PAD_CFG_DW0_GPIO_8 0x5c8 +#define PID_GPIO_8 PID_SouthCommunity + +// _GPIO_9 : LFFF: DVT_GPIO<2> : BIOS Verbose +#define GPIO_GPIO_9 9 +#define R_PAD_CFG_DW0_GPIO_9 0x5d0 +#define PID_GPIO_9 PID_SouthCommunity + +#endif /* _MAINBOARD_GPIO_DEFS_H */ + diff --git a/src/mainboard/scaleway/tagada/hsio.c b/src/mainboard/scaleway/tagada/hsio.c index 8e8e03e..dca80ac 100644 --- a/src/mainboard/scaleway/tagada/hsio.c +++ b/src/mainboard/scaleway/tagada/hsio.c @@ -14,13 +14,66 @@ * GNU General Public License for more details. */ +#include <arch/io.h> +#include <console/console.h> #include <hsio.h> +#include <gpio_defs.h> #include <soc/fiamux.h> +#ifdef __RAMSTAGE__ +static void update_hsio_info_for_m2_slots(size_t num_of_entry, + BL_HSIO_INFORMATION *config) +{ + uint32_t reg32; + bool m2a_pcie, m2b_pcie; + uint8_t entry; + + /* Detects modules type */ + // _GPIO_4 : LFFF: M2A_CFGn : M2A_SATAn : 0 SATA, 1 PCIe + reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIO_4, + R_PAD_CFG_DW0_GPIO_4)); + m2a_pcie = (reg32 & B_PCH_GPIO_RX_STATE)?1:0; + // _GPIO_5 : LFFF: M2A_CFGn : M2A_SATAn : 0 SATA, 1 PCIe + reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIO_5, + R_PAD_CFG_DW0_GPIO_5)); + m2b_pcie = (reg32 & B_PCH_GPIO_RX_STATE)?1:0; + + printk(BIOS_DEBUG, "GPIO values from M2 slots A:%d B:%d " + "(0=SATA, 1=PCIe or not populated)\n", + m2a_pcie, m2b_pcie); + + // HSIO default config is for PCIe, only update for SATA + // (also secondary PCIe lines are already set depending on SKU) + for (entry = 0; entry < num_of_entry; entry++) { + BL_ME_FIA_MUX_CONFIG *mux_config = + &(config[entry].FiaConfig.MuxConfiguration); + BL_ME_FIA_SATA_CONFIG *sata_config = + &(config[entry].FiaConfig.SataLaneConfiguration); + if (!m2a_pcie) { + // change Lane 14 config + mux_config->BL_MeFiaMuxLaneMuxSel.Lane14MuxSel = + BL_ME_FIA_MUX_LANE_SATA; + sata_config->BL_MeFiaSataLaneSataSel.Lane14SataSel = + BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED; + } + if (!m2b_pcie) { + // change Lane 12 config + mux_config->BL_MeFiaMuxLaneMuxSel.Lane12MuxSel = + BL_ME_FIA_MUX_LANE_SATA; + sata_config->BL_MeFiaSataLaneSataSel.Lane12SataSel = + BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED; + } + } +} +#endif + size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config) { size_t num; num = ARRAY_SIZE(tagada_hsio_config); +#ifdef __RAMSTAGE__ + update_hsio_info_for_m2_slots(num, tagada_hsio_config); +#endif (*p_hsio_config) = (BL_HSIO_INFORMATION *)tagada_hsio_config; return num; } diff --git a/src/mainboard/scaleway/tagada/hsio.h b/src/mainboard/scaleway/tagada/hsio.h index e49fefd..6289dae 100644 --- a/src/mainboard/scaleway/tagada/hsio.h +++ b/src/mainboard/scaleway/tagada/hsio.h @@ -21,7 +21,7 @@ #include <fsp/util.h> #ifndef __ACPI__ -const BL_HSIO_INFORMATION tagada_hsio_config[] = { +DEVTREE_CONST BL_HSIO_INFORMATION tagada_hsio_config[] = { /* * Supported Lanes: * 20 -- To view, visit https://review.coreboot.org/25436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic3ed97fc2b54d4974ec0b41b9f207fe3d49d2cce Gerrit-Change-Number: 25436 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: soc/intel/denverton_ns: Enable MC Exception
by Julien Viard de Galbert (Code Review) 29 Mar '18

29 Mar '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25434 Change subject: soc/intel/denverton_ns: Enable MC Exception ...................................................................... soc/intel/denverton_ns: Enable MC Exception Change-Id: I9773c61d06bb6c68612e498a35b5ad22cd5a8a6e Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/denverton_ns/cpu.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/25434/1 diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 6c1298e..4434964 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -59,6 +59,12 @@ of these banks are core vs package scope. For now every CPU clears every bank. */ mca_configure(); + + /* TODO install a fallback MC handler for each core in case OS does + not provide one. Is it really needed ? */ + + /* Enable the machine check exception */ + write_cr4(read_cr4() | CR4_MCE); } static void denverton_core_init(device_t cpu) -- To view, visit https://review.coreboot.org/25434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9773c61d06bb6c68612e498a35b5ad22cd5a8a6e Gerrit-Change-Number: 25434 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: mb/scaleway/tagada/hsio.c: Reindent wit tabs
by Julien Viard de Galbert (Code Review) 29 Mar '18

29 Mar '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25435 Change subject: mb/scaleway/tagada/hsio.c: Reindent wit tabs ...................................................................... mb/scaleway/tagada/hsio.c: Reindent wit tabs Change-Id: I846ecf29031253b3647dbd53964d29d1ed613913 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/mainboard/scaleway/tagada/hsio.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/25435/1 diff --git a/src/mainboard/scaleway/tagada/hsio.c b/src/mainboard/scaleway/tagada/hsio.c index a8a2035..8e8e03e 100644 --- a/src/mainboard/scaleway/tagada/hsio.c +++ b/src/mainboard/scaleway/tagada/hsio.c @@ -19,8 +19,8 @@ size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config) { - size_t num; - num = ARRAY_SIZE(tagada_hsio_config); - (*p_hsio_config) = (BL_HSIO_INFORMATION *)tagada_hsio_config; - return num; + size_t num; + num = ARRAY_SIZE(tagada_hsio_config); + (*p_hsio_config) = (BL_HSIO_INFORMATION *)tagada_hsio_config; + return num; } -- To view, visit https://review.coreboot.org/25435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I846ecf29031253b3647dbd53964d29d1ed613913 Gerrit-Change-Number: 25435 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: soc/intel/denverton_ns: Configure MCA
by Julien Viard de Galbert (Code Review) 29 Mar '18

29 Mar '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25433 Change subject: soc/intel/denverton_ns: Configure MCA ...................................................................... soc/intel/denverton_ns: Configure MCA Change-Id: I101eb4f008a13af92bac5ed738a8d1f1f8c65eba Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/denverton_ns/include/soc/msr.h 2 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/25433/1 diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 12fda1c..6c1298e 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -35,12 +35,41 @@ static struct smm_relocation_attrs relo_attrs; +static void dnv_configure_mca(void) +{ + msr_t msr; + int num_banks; + struct cpuid_result cpuid_regs; + + /* Check feature flag in CPUID.(EAX=1):EDX[7]==1 MCE + * and CPUID.(EAX=1):EDX[14]==1 MCA*/ + cpuid_regs = cpuid(1); + if ((cpuid_regs.edx & (1<<7 | 1<<14)) != (1<<7 | 1<<14)) + return; + + msr = rdmsr(IA32_MCG_CAP); + num_banks = msr.lo & IA32_MCG_CAP_COUNT_MASK; + if (msr.lo & IA32_MCG_CAP_CTL_P_MASK) { + /* Enable all error logging */ + msr.lo = msr.hi = 0xffffffff; + wrmsr(IA32_MCG_CTL, msr); + } + + /* TODO(adurbin): This should only be done on a cold boot. Also, some + of these banks are core vs package scope. For now every CPU clears + every bank. */ + mca_configure(); +} + static void denverton_core_init(device_t cpu) { msr_t msr; printk(BIOS_DEBUG, "Init Denverton-NS SoC cores.\n"); + /* Clear out pending MCEs */ + dnv_configure_mca(); + /* Enable Fast Strings */ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= FAST_STRINGS_ENABLE_BIT; diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index d56cc65..05ccc65 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -29,6 +29,11 @@ #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_FEATURE_CONFIG 0x13c +#define IA32_MCG_CAP 0x179 +#define IA32_MCG_CAP_COUNT_MASK 0xff +#define IA32_MCG_CAP_CTL_P_BIT 8 +#define IA32_MCG_CAP_CTL_P_MASK (1 << IA32_MCG_CAP_CTL_P_BIT) +#define IA32_MCG_CTL 0x17b #define SMM_MCA_CAP_MSR 0x17d #define SMM_CPU_SVRSTR_BIT 57 #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) -- To view, visit https://review.coreboot.org/25433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I101eb4f008a13af92bac5ed738a8d1f1f8c65eba Gerrit-Change-Number: 25433 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: soc/intel/denverton_ns: Use cpulib in cpu.c
by Julien Viard de Galbert (Code Review) 29 Mar '18

29 Mar '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25432 Change subject: soc/intel/denverton_ns: Use cpulib in cpu.c ...................................................................... soc/intel/denverton_ns: Use cpulib in cpu.c Also remove duplicate code Change-Id: I45da6363a35cf6f5855906bb97ed023681d36df7 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/denverton_ns/cpu.c 1 file changed, 1 insertion(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/25432/1 diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index fba6627..12fda1c 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -24,6 +24,7 @@ #include <cpu/intel/turbo.h> #include <device/device.h> #include <device/pci.h> +#include <intelblocks/cpulib.h> #include <reg_script.h> #include <soc/msr.h> @@ -175,15 +176,6 @@ return num_cpus; } -static int cpu_config_tdp_levels(void) -{ - msr_t platform_info; - - /* Bits 34:33 indicate how many levels supported */ - platform_info = rdmsr(MSR_PLATFORM_INFO); - return (platform_info.hi >> 1) & 3; -} - static void set_max_turbo_freq(void) { msr_t msr, perf_ctl; -- To view, visit https://review.coreboot.org/25432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I45da6363a35cf6f5855906bb97ed023681d36df7 Gerrit-Change-Number: 25432 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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coreboot-gerrit March 2018