coreboot-gerrit March 2018

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Change in coreboot[master]: soc/intel/denverton_ns: Enable ACPI using intelblock
by build bot (Jenkins) (Code Review) 29 Mar '18

29 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25428 ) Change subject: soc/intel/denverton_ns: Enable ACPI using intelblock ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/69201/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/23550/ : SUCCESS -- To view, visit https://review.coreboot.org/25428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399 Gerrit-Change-Number: 25428 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Mar 2018 13:20:18 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/denverton_ns: Add ACPI T-States and P-States
by build bot (Jenkins) (Code Review) 29 Mar '18

29 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25430 ) Change subject: soc/intel/denverton_ns: Add ACPI T-States and P-States ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/69203/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/23552/ : SUCCESS -- To view, visit https://review.coreboot.org/25430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id9c7da474a81417a5cebd875023f7cd3d5a77796 Gerrit-Change-Number: 25430 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Mar 2018 13:20:02 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/denverton_ns: Rewrite pmutil using pmclib
by build bot (Jenkins) (Code Review) 29 Mar '18

29 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25427 ) Change subject: soc/intel/denverton_ns: Rewrite pmutil using pmclib ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69200/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23548/ : SUCCESS -- To view, visit https://review.coreboot.org/25427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If31e7102bf1b47c7ae94b86d981b762eda0a19e5 Gerrit-Change-Number: 25427 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Mar 2018 13:16:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/denverton_ns: Enable common code for CPU
by build bot (Jenkins) (Code Review) 29 Mar '18

29 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24927 ) Change subject: soc/intel/denverton_ns: Enable common code for CPU ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69198/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23547/ : SUCCESS -- To view, visit https://review.coreboot.org/24927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib215aa17dd20112946b74a1b63ce8a735388873c Gerrit-Change-Number: 24927 Gerrit-PatchSet: 2 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Mar 2018 13:14:08 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/denverton: Enable common block PMC
by build bot (Jenkins) (Code Review) 29 Mar '18

29 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25426 ) Change subject: soc/intel/denverton: Enable common block PMC ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69199/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23549/ : SUCCESS -- To view, visit https://review.coreboot.org/25426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd Gerrit-Change-Number: 25426 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Mar 2018 13:12:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/denverton_ns: Generate ACPI DMAR Table
by Julien Viard de Galbert (Code Review) 29 Mar '18

29 Mar '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25446 Change subject: soc/intel/denverton_ns: Generate ACPI DMAR Table ...................................................................... soc/intel/denverton_ns: Generate ACPI DMAR Table - Write ACPI DMAR Table if VT-d is enabled. - The entries are defined to follow FSP settings. Change-Id: I263b03b96280599266d4c5e193583ecdfe9697b7 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/include/soc/acpi.h M src/soc/intel/denverton_ns/include/soc/iomap.h M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/denverton_ns/include/soc/systemagent.h M src/soc/intel/denverton_ns/systemagent.c 6 files changed, 82 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/25446/1 diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 9b99f11..853a6ee 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -32,6 +32,7 @@ #include <soc/soc_util.h> #include <soc/pmc.h> #include <soc/systemagent.h> +#include <soc/pci_devs.h> #define MWAIT_RES(state, sub_state) \ { \ @@ -335,3 +336,59 @@ } __attribute__((weak)) void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {} + +static unsigned long acpi_fill_dmar(unsigned long current) +{ + uint32_t vtbar; + unsigned long tmp = current; + + vtbar = read32((void *)(DEFAULT_MCHBAR + MCH_VTBAR_OFFSET)) & + MCH_VTBAR_MASK; + printk(BIOS_DEBUG, "DEFVTBAR:0x%x\n", vtbar); + if (!vtbar) + return current; + + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, vtbar); + + current += acpi_create_dmar_drhd_ds_ioapic(current, + 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); + current += acpi_create_dmar_drhd_ds_msi_hpet(current, + 0, PCH_HPET_PCI_BUS, PCH_HPET_PCI_SLOT, 0); + + acpi_dmar_drhd_fixup(tmp, current); + + /* Create RMRR; see "VTD PLATFORM CONFIGURATION" in fsp log */ + tmp = current; + current += acpi_create_dmar_rmrr(current, 0, + RMRR_USB_BASE_ADDRESS, + RMRR_USB_LIMIT_ADDRESS); + /* reusing drdh functions for rmrr. + * Should be Device Scope? + * IE remove _drhd */ + current += acpi_create_dmar_drhd_ds_pci(current, + 0, XHCI_DEV, XHCI_FUNC); + acpi_dmar_rmrr_fixup(tmp, current); + + return current; +} + +unsigned long systemagent_write_acpi_tables(struct device *const dev, + unsigned long current, + struct acpi_rsdp *const rsdp) +{ + /* Create DMAR table only if we have VT-d capability. */ + const u32 capid0_a = pci_read_config32(dev, CAPID0_A); + if (capid0_a & VTD_DISABLE) + return current; + + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + + return current; +} + diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h index 588994d..f11a1a2 100644 --- a/src/soc/intel/denverton_ns/include/soc/acpi.h +++ b/src/soc/intel/denverton_ns/include/soc/acpi.h @@ -30,5 +30,8 @@ struct acpi_rsdp *rsdp); void southcluster_inject_dsdt(device_t device); void motherboard_fill_fadt(acpi_fadt_t *fadt); +unsigned long systemagent_write_acpi_tables(struct device *const dev, + unsigned long start, + struct acpi_rsdp *const rsdp); #endif /* _DENVERTON_NS_ACPI_H_ */ diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h index a7548d4..8b25547 100644 --- a/src/soc/intel/denverton_ns/include/soc/iomap.h +++ b/src/soc/intel/denverton_ns/include/soc/iomap.h @@ -38,4 +38,8 @@ #define DEFAULT_HPET_ADDR CONFIG_HPET_ADDRESS #define DEFAULT_SPI_BASE 0xfed01000 +/* "VTD PLATFORM CONFIGURATION" (Set to match FSP settings) */ +#define RMRR_USB_BASE_ADDRESS 0x3e2e0000 +#define RMRR_USB_LIMIT_ADDRESS 0x3e2fffff + #endif /* _DENVERTON_NS_IOMAP_H_ */ diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index b10a905..134586d 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -202,4 +202,12 @@ #define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) +/* VT-d support value to match FSP settings */ +/* "PCH IOAPIC Config" */ +#define PCH_IOAPIC_PCI_BUS 0xF0 +#define PCH_IOAPIC_PCI_SLOT 31 +/* "PCH HPET Config" */ +#define PCH_HPET_PCI_BUS 0 +#define PCH_HPET_PCI_SLOT 0 + #endif /* _DENVERTON_NS_PCI_DEVS_H_ */ diff --git a/src/soc/intel/denverton_ns/include/soc/systemagent.h b/src/soc/intel/denverton_ns/include/soc/systemagent.h index a02aea3..4189d64 100644 --- a/src/soc/intel/denverton_ns/include/soc/systemagent.h +++ b/src/soc/intel/denverton_ns/include/soc/systemagent.h @@ -47,6 +47,9 @@ #define TOLUD 0xbc /* Top of Low Used Memory */ #define MASK_TOLUD 0xFFF00000 +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) + /* SideBand B-UNIT */ #define B_UNIT 3 @@ -73,6 +76,9 @@ #define MCH_BMISC_RESDRAM \ 0x01 /* Bit 0: 1 - reads targeting E-segment are routed to DRAM. */ +#define MCH_VTBAR_OFFSET 0x6c80 +#define MCH_VTBAR_MASK 0xfffff000 + #define MCH_BAR_BIOS_RESET_CPL 0x7078 #define RST_CPL_BIT (1 << 0) #define PCODE_INIT_DONE (1 << 8) diff --git a/src/soc/intel/denverton_ns/systemagent.c b/src/soc/intel/denverton_ns/systemagent.c index 0fcac3b..6d40ac9 100644 --- a/src/soc/intel/denverton_ns/systemagent.c +++ b/src/soc/intel/denverton_ns/systemagent.c @@ -34,6 +34,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/systemagent.h> +#include <soc/acpi.h> #define _1ms 1 #define WAITING_STEP 100 @@ -341,6 +342,9 @@ .enable_resources = &pci_dev_enable_resources, .init = &systemagent_init, .ops_pci = &soc_pci_ops, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .write_acpi_tables = systemagent_write_acpi_tables, +#endif }; /* IDs for System Agent device of Intel Denverton SoC */ -- To view, visit https://review.coreboot.org/25446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I263b03b96280599266d4c5e193583ecdfe9697b7 Gerrit-Change-Number: 25446 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: arch/x86/acpi: Add DMAR RMRR helper functions
by Julien Viard de Galbert (Code Review) 29 Mar '18

29 Mar '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25445 Change subject: arch/x86/acpi: Add DMAR RMRR helper functions ...................................................................... arch/x86/acpi: Add DMAR RMRR helper functions Change-Id: Id4e7d95d2d13a7f7b49fcb6f6b9e8ccd6ae12a9e Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/arch/x86/acpi.c M src/arch/x86/include/arch/acpi.h 2 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/25445/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 601b6f0..7d66285 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -9,6 +9,7 @@ * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, * Raptor Engineering * Copyright (C) 2016-2017 Siemens AG + * Copyright (C) 2018 Online SAS * * ACPI FADT, FACS, and DSDT table support added by * Nick Barker <nick.barker9(a)btinternet.com>, and those portions @@ -461,6 +462,20 @@ return drhd->length; } +unsigned long acpi_create_dmar_rmrr(unsigned long current, u16 segment, + u32 bar, u64 limit) +{ + dmar_rmrr_entry_t *rmrr = (dmar_rmrr_entry_t *)current; + memset(rmrr, 0, sizeof(*rmrr)); + rmrr->type = DMAR_RMRR; + rmrr->length = sizeof(*rmrr); /* will be fixed up later */ + rmrr->segment = segment; + rmrr->bar = bar; + rmrr->limit = limit; + + return rmrr->length; +} + unsigned long acpi_create_dmar_atsr(unsigned long current, u8 flags, u16 segment) { @@ -480,6 +495,12 @@ drhd->length = current - base; } +void acpi_dmar_rmrr_fixup(unsigned long base, unsigned long current) +{ + dmar_rmrr_entry_t *rmrr = (dmar_rmrr_entry_t *)base; + rmrr->length = current - base; +} + void acpi_dmar_atsr_fixup(unsigned long base, unsigned long current) { dmar_atsr_entry_t *atsr = (dmar_atsr_entry_t *)base; diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 5418420..a1ed338 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -331,6 +331,15 @@ u64 bar; } __packed dmar_entry_t; +typedef struct dmar_rmrr_entry { + u16 type; + u16 length; + u16 reserved; + u16 segment; + u64 bar; + u64 limit; +} __packed dmar_rmrr_entry_t; + typedef struct dmar_atsr_entry { u16 type; u16 length; @@ -715,9 +724,12 @@ unsigned long (*acpi_fill_dmar)(unsigned long)); unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, u16 segment, u32 bar); +unsigned long acpi_create_dmar_rmrr(unsigned long current, u16 segment, + u32 bar, u64 limit); unsigned long acpi_create_dmar_atsr(unsigned long current, u8 flags, u16 segment); void acpi_dmar_drhd_fixup(unsigned long base, unsigned long current); +void acpi_dmar_rmrr_fixup(unsigned long base, unsigned long current); void acpi_dmar_atsr_fixup(unsigned long base, unsigned long current); unsigned long acpi_create_dmar_drhd_ds_pci_br(unsigned long current, u8 bus, u8 dev, u8 fn); -- To view, visit https://review.coreboot.org/25445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id4e7d95d2d13a7f7b49fcb6f6b9e8ccd6ae12a9e Gerrit-Change-Number: 25445 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: soc/intel/denverton + mb: Change UART IRQ line in conflict with ME
by Julien Viard de Galbert (Code Review) 29 Mar '18

29 Mar '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25444 Change subject: soc/intel/denverton + mb: Change UART IRQ line in conflict with ME ...................................................................... soc/intel/denverton + mb: Change UART IRQ line in conflict with ME Change the UART IRQ line from A/16 to G/22 The IRQ conflict was trigered by using the tools spsInfo or spsManuf. Change-Id: I0c59ff80ef19b54c2de1a6a8205afe6482adfdff Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/mainboard/intel/harcuvar/devicetree.cb M src/mainboard/scaleway/tagada/devicetree.cb M src/soc/intel/denverton_ns/acpi/lpc.asl 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/25444/1 diff --git a/src/mainboard/intel/harcuvar/devicetree.cb b/src/mainboard/intel/harcuvar/devicetree.cb index 7fce211..e6c4aa2 100644 --- a/src/mainboard/intel/harcuvar/devicetree.cb +++ b/src/mainboard/intel/harcuvar/devicetree.cb @@ -35,7 +35,7 @@ register "ir07_routing" = "0x3210" # IR07, Dev9/10/11/12 register "ir08_routing" = "0x7654" # IR08, Dev14/15/16/17 register "ir09_routing" = "0x3213" # IR09, Dev21 - register "ir10_routing" = "0x3210" # IR10, Dev26/18 + register "ir10_routing" = "0x3216" # IR10, Dev26/18 register "ir11_routing" = "0x3215" # IR11, Dev20 register "ir12_routing" = "0x3210" # IR12, Dev27 # configure interrupt polarity control diff --git a/src/mainboard/scaleway/tagada/devicetree.cb b/src/mainboard/scaleway/tagada/devicetree.cb index acf56a0..f878e95 100644 --- a/src/mainboard/scaleway/tagada/devicetree.cb +++ b/src/mainboard/scaleway/tagada/devicetree.cb @@ -35,7 +35,7 @@ register "ir07_routing" = "0x3210" # IR07, Dev9/10/11/12 register "ir08_routing" = "0x7654" # IR08, Dev14/15/16/17 register "ir09_routing" = "0x3213" # IR09, Dev21 - register "ir10_routing" = "0x3210" # IR10, Dev26/18 + register "ir10_routing" = "0x3216" # IR10, Dev26/18 register "ir11_routing" = "0x3215" # IR11, Dev20 register "ir12_routing" = "0x3210" # IR12, Dev27 # configure interrupt polarity control diff --git a/src/soc/intel/denverton_ns/acpi/lpc.asl b/src/soc/intel/denverton_ns/acpi/lpc.asl index 262ac55..4ae3c35 100644 --- a/src/soc/intel/denverton_ns/acpi/lpc.asl +++ b/src/soc/intel/denverton_ns/acpi/lpc.asl @@ -153,7 +153,7 @@ Name(BUF0,ResourceTemplate() { IO(Decode16,0x03F8,0x03F8,0x01,0x08) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {22} }) Return(BUF0) -- To view, visit https://review.coreboot.org/25444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0c59ff80ef19b54c2de1a6a8205afe6482adfdff Gerrit-Change-Number: 25444 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: mb/scaleway/tagada: Don't change FIAMUX when Security Override is set
by Julien Viard de Galbert (Code Review) 29 Mar '18

29 Mar '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25443 Change subject: mb/scaleway/tagada: Don't change FIAMUX when Security Override is set ...................................................................... mb/scaleway/tagada: Don't change FIAMUX when Security Override is set This will not enable M.2 SATA drive if the ME config was lost (For instance after flashin a full flash factory image) This is required so that the system can boot without FIA MUX error during flash update procedure. Change-Id: I55a8bcdc30bc67af2d3e9ccb8844eac599727108 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/mainboard/scaleway/tagada/hsio.c 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/25443/1 diff --git a/src/mainboard/scaleway/tagada/hsio.c b/src/mainboard/scaleway/tagada/hsio.c index dca80ac..b48ef11 100644 --- a/src/mainboard/scaleway/tagada/hsio.c +++ b/src/mainboard/scaleway/tagada/hsio.c @@ -19,6 +19,8 @@ #include <hsio.h> #include <gpio_defs.h> #include <soc/fiamux.h> +#include <string.h> +#include <fast_spi_def.h> #ifdef __RAMSTAGE__ static void update_hsio_info_for_m2_slots(size_t num_of_entry, @@ -27,6 +29,14 @@ uint32_t reg32; bool m2a_pcie, m2b_pcie; uint8_t entry; + BL_FIA_MUX_CONFIG_HOB *fiamux_hob_data = get_fiamux_hob_data(); + uint16_t supported_hsio_lanes; + void *spibar = fast_spi_get_bar(); + uint32_t hsfs; + + /* Configure FIA MUX PCD */ + supported_hsio_lanes = + (uint16_t)fiamux_hob_data->FiaMuxConfig.SkuNumLanesAllowed; /* Detects modules type */ // _GPIO_4 : LFFF: M2A_CFGn : M2A_SATAn : 0 SATA, 1 PCIe @@ -45,6 +55,10 @@ // HSIO default config is for PCIe, only update for SATA // (also secondary PCIe lines are already set depending on SKU) for (entry = 0; entry < num_of_entry; entry++) { + /* only update the active config */ + if (config[entry].NumLanesSupported != supported_hsio_lanes) + continue; + BL_ME_FIA_CONFIG *fia_config = &(config[entry].FiaConfig); BL_ME_FIA_MUX_CONFIG *mux_config = &(config[entry].FiaConfig.MuxConfiguration); BL_ME_FIA_SATA_CONFIG *sata_config = @@ -63,6 +77,25 @@ sata_config->BL_MeFiaSataLaneSataSel.Lane12SataSel = BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED; } + + /* Check SPIBAR for security override + at least one M2 slot is populated with SATA + the configuration is different form ME current one */ + hsfs = read32(spibar + SPIBAR_HSFSTS_CTL); + if ((!(hsfs & SPIBAR_HSFSTS_FDOPSS)) + && (!m2a_pcie || !m2b_pcie) + && memcmp(fia_config, + &fiamux_hob_data->FiaMuxConfig.FiaMuxConfig, + sizeof(BL_ME_FIA_CONFIG))) { + /* update configuration to NOT change ME config + as it will fail with security override set. */ + memcpy(fia_config, + &fiamux_hob_data->FiaMuxConfig.FiaMuxConfig, + sizeof(BL_ME_FIA_CONFIG)); + printk(BIOS_CRIT, "FLASH SECURITY OVERRIDE SET: " + "M2 SATA Slots are not available!\n"); + + } } } #endif -- To view, visit https://review.coreboot.org/25443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I55a8bcdc30bc67af2d3e9ccb8844eac599727108 Gerrit-Change-Number: 25443 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock
by Julien Viard de Galbert (Code Review) 29 Mar '18

29 Mar '18

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25442 Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock ...................................................................... soc/intel/denverton_ns: Implement PCIe post config + lock Configure PCIe maximum payload size to fix Intel SSD Lock Down PCIe Configuration Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/denverton_ns/lpc.c 1 file changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/25442/1 diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 8f2542a..f52bbfe 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -378,12 +378,47 @@ } +static void spi_lock_pcie(void) +{ + int i; + struct device *dev; + uint16_t reg16; + for (i = 0; i < MAX_PCIE_PORT; i++) { + if (i < 4) + dev = dev_find_slot(0, PCI_DEVFN(PCIE_PORT1_DEV + i, + PCIE_PORT1_FUNC)); + else + dev = dev_find_slot(0, PCI_DEVFN(PCIE_PORT2_DEV + i, + PCIE_PORT1_FUNC)); + + if (dev == NULL) { + printk(BIOS_DEBUG, "PCIe Port%d NOT AVAILABLE!\n", i); + continue; + } + + reg16 = pci_read_config16(dev, 0x48); + printk(BIOS_DEBUG, "PCIe Port%d DEVCTL:0x%x\n", i, reg16); + /* Set MRRS & MPS to 128 bytes */ + reg16 &= ~(PCI_EXP_DEVCTL_READRQ | PCI_EXP_DEVCTL_PAYLOAD); + pci_write_config16(dev, 0x48, reg16); + + reg16 = pci_read_config16(dev, 0xEA); + printk(BIOS_DEBUG, "PCIe Port%d PLKCTL:0x%x\n", i, reg16); + reg16 |= 7; /* Lock bits */ + pci_write_config16(dev, 0xEA, reg16); + } + +} + static void finalize_chipset(void *unused) { bool relax_security = fsp_relax_security(); spi_lock_bar(relax_security); + if(!relax_security) + spi_lock_pcie(); + printk(BIOS_DEBUG, "Finalizing SMM.\n"); outb(APM_CNT_FINALIZE, APM_CNT); } -- To view, visit https://review.coreboot.org/25442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd Gerrit-Change-Number: 25442 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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