coreboot-gerrit March 2018

coreboot-gerrit@coreboot.org

1 participants
1399 discussions

Change in coreboot[master]: soc/cavium/cn81xx: Set cntfrq_el0
by Patrick Rudolph (Code Review) 29 Mar '18

29 Mar '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25450 Change subject: soc/cavium/cn81xx: Set cntfrq_el0 ...................................................................... soc/cavium/cn81xx: Set cntfrq_el0 Set cntfrq_el0 to provide correct timer frequency. Change-Id: I4b6d0b0cf646a066fc5a51552a1891eccbd91e5e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/cavium/cn8100_sff_evb/mainboard.c M src/soc/cavium/cn81xx/include/soc/timer.h M src/soc/cavium/cn81xx/timer.c 3 files changed, 16 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/25450/1 diff --git a/src/mainboard/cavium/cn8100_sff_evb/mainboard.c b/src/mainboard/cavium/cn8100_sff_evb/mainboard.c index 0887cde..d9df011 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/mainboard.c +++ b/src/mainboard/cavium/cn8100_sff_evb/mainboard.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <soc/clock.h> #include <soc/gpio.h> +#include <soc/timer.h> static void mainboard_print_info(void) { @@ -70,6 +71,9 @@ if (!uart_is_enabled(i)) uart_setup(i, 0); } + + /* Init timer */ + soc_timer_init(); } static void mainboard_enable(device_t dev) diff --git a/src/soc/cavium/cn81xx/include/soc/timer.h b/src/soc/cavium/cn81xx/include/soc/timer.h index 6d48831..f9e5961 100644 --- a/src/soc/cavium/cn81xx/include/soc/timer.h +++ b/src/soc/cavium/cn81xx/include/soc/timer.h @@ -17,4 +17,7 @@ void watchdog_disable(const size_t index); int watchdog_is_running(const size_t index); +/* Timer functions */ +void soc_timer_init(void); + #endif /* __SOC_CAVIUM_CN81XX_TIMER_H__ */ diff --git a/src/soc/cavium/cn81xx/timer.c b/src/soc/cavium/cn81xx/timer.c index ee8d639..ab8391b 100644 --- a/src/soc/cavium/cn81xx/timer.c +++ b/src/soc/cavium/cn81xx/timer.c @@ -17,6 +17,7 @@ #include <timer.h> #include <soc/addressmap.h> #include <assert.h> +#include <arch/clock.h> /* Global System Timers Unit (GTI) registers */ struct cn81xx_timer { @@ -89,6 +90,9 @@ mono_time_set_usecs(mt, timer_raw_value()); } +/* Setup counter to operate at 1MHz */ +static const size_t tickrate = 1000000; + /** * Init Global System Timers Unit (GTI). * Configure timer to run at 1MHz tick-rate. @@ -106,8 +110,6 @@ /* Use coprocessor clock source */ write32(&gti->cc_imp_ctl, 0); - /* Setup counter to operate at 1MHz */ - const size_t tickrate = 1000000; write32(&gti->cc_cntfid0, tickrate); write32(&gti->ctl_cntfrq, tickrate); write32(&gti->cc_cntrate, ((1ULL << 32) * tickrate) / sclk); @@ -119,6 +121,11 @@ //BDK_MSR(CNTPS_CTL_EL1, u); } +void soc_timer_init(void) +{ + set_cntfrq(tickrate); +} + /** * Setup the watchdog to expire in timeout_ms milliseconds. When the watchdog * expires, the chip three things happen: -- To view, visit https://review.coreboot.org/25450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4b6d0b0cf646a066fc5a51552a1891eccbd91e5e Gerrit-Change-Number: 25450 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

1 0

Change in coreboot[master]: include/string: Add strrchr
by Patrick Rudolph (Code Review) 29 Mar '18

29 Mar '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25447 Change subject: include/string: Add strrchr ...................................................................... include/string: Add strrchr Copy strrchr from libpayload. To be used by Cavium's BDK or FDT parsers. Change-Id: Iab7981c25113ed16f1b8130de4935d30c29d2fa5 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/include/string.h 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/25447/1 diff --git a/src/include/string.h b/src/include/string.h index 7597323..d2d7bb8 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -66,6 +66,26 @@ } #endif +/** + * Find a character in a string. + * + * @param s The string. + * @param c The character. + * @return A pointer to the last occurrence of the character in the + * string, or NULL if the character was not encountered within the string. + */ +static inline char *strrchr(const char *s, int c) +{ + char *p = (char *)s + strlen(s); + + for (; p >= s; p--) { + if (*p == c) + return p; + } + + return NULL; +} + static inline char *strncpy(char *to, const char *from, int count) { register char *ret = to; -- To view, visit https://review.coreboot.org/25447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iab7981c25113ed16f1b8130de4935d30c29d2fa5 Gerrit-Change-Number: 25447 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

1 0

Change in coreboot[master]: soc/cavium: Clean uart code
by Patrick Rudolph (Code Review) 29 Mar '18

29 Mar '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25448 Change subject: soc/cavium: Clean uart code ...................................................................... soc/cavium: Clean uart code * Don't init uart1 in bootblock. * Allow UART init with zero baudrate. * Init UART0..3 on Cavium's cn8100_sff_evb to fix kernel panic. Tested on CN8100_SFF_EVB. Change-Id: I1043b30318ec6210e2dd6b7ac313a41171d37f55 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/cavium/cn8100_sff_evb/bootblock.c M src/mainboard/cavium/cn8100_sff_evb/mainboard.c M src/soc/cavium/cn81xx/uart.c 3 files changed, 16 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/25448/1 diff --git a/src/mainboard/cavium/cn8100_sff_evb/bootblock.c b/src/mainboard/cavium/cn8100_sff_evb/bootblock.c index 4fe6e43..dcc9c90 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/bootblock.c +++ b/src/mainboard/cavium/cn8100_sff_evb/bootblock.c @@ -16,8 +16,6 @@ if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { if (!uart_is_enabled(0)) uart_setup(0, CONFIG_TTYS0_BAUD); - if (!uart_is_enabled(1)) - uart_setup(0, CONFIG_TTYS0_BAUD); } } diff --git a/src/mainboard/cavium/cn8100_sff_evb/mainboard.c b/src/mainboard/cavium/cn8100_sff_evb/mainboard.c index cc23cb5..b2b98dd 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/mainboard.c +++ b/src/mainboard/cavium/cn8100_sff_evb/mainboard.c @@ -15,10 +15,17 @@ */ #include <device/device.h> +#include <soc/uart.h> static void mainboard_init(device_t dev) { - /* FIXME: stub */ + size_t i; + + /* Init UARTs */ + for (i = 0; i < 4; i++) { + if (!uart_is_enabled(i)) + uart_setup(i, 0); + } } static void mainboard_enable(device_t dev) diff --git a/src/soc/cavium/cn81xx/uart.c b/src/soc/cavium/cn81xx/uart.c index b3cce8e..e2d0157 100644 --- a/src/soc/cavium/cn81xx/uart.c +++ b/src/soc/cavium/cn81xx/uart.c @@ -225,6 +225,14 @@ write64(&uart->uctl_ctl, ctl.u); /** + * Exit here if the UART is not going to be used in coreboot. + * The previous initialization steps are sufficient to make the Linux + * kernel not panic. + */ + if (!baudrate) + return 0; + + /** * 7. Initialize the integer and fractional baud rate divider registers * UARTIBRD and UARTFBRD as follows: * a. Baud Rate Divisor = UARTCLK/(16xBaud Rate) = BRDI + BRDF -- To view, visit https://review.coreboot.org/25448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1043b30318ec6210e2dd6b7ac313a41171d37f55 Gerrit-Change-Number: 25448 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

1 0

Change in coreboot[master]: soc/intel/denverton_ns: Generate ACPI DMAR Table
by build bot (Jenkins) (Code Review) 29 Mar '18

29 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25446 ) Change subject: soc/intel/denverton_ns: Generate ACPI DMAR Table ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/69219/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/23568/ : SUCCESS -- To view, visit https://review.coreboot.org/25446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I263b03b96280599266d4c5e193583ecdfe9697b7 Gerrit-Change-Number: 25446 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Mar 2018 13:34:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: arch/x86/acpi: Add DMAR RMRR helper functions
by build bot (Jenkins) (Code Review) 29 Mar '18

29 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25445 ) Change subject: arch/x86/acpi: Add DMAR RMRR helper functions ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/69218/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/23567/ : SUCCESS -- To view, visit https://review.coreboot.org/25445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id4e7d95d2d13a7f7b49fcb6f6b9e8ccd6ae12a9e Gerrit-Change-Number: 25445 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Mar 2018 13:34:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: soc/intel/denverton + mb: Change UART IRQ line in conflict with ME
by build bot (Jenkins) (Code Review) 29 Mar '18

29 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25444 ) Change subject: soc/intel/denverton + mb: Change UART IRQ line in conflict with ME ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/69217/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/23566/ : SUCCESS -- To view, visit https://review.coreboot.org/25444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0c59ff80ef19b54c2de1a6a8205afe6482adfdff Gerrit-Change-Number: 25444 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Mar 2018 13:33:43 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock
by build bot (Jenkins) (Code Review) 29 Mar '18

29 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25442 ) Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/69215/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/23564/ : SUCCESS -- To view, visit https://review.coreboot.org/25442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd Gerrit-Change-Number: 25442 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Mar 2018 13:33:32 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mb/scaleway/tagada: Don't change FIAMUX when Security Override is set
by build bot (Jenkins) (Code Review) 29 Mar '18

29 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25443 ) Change subject: mb/scaleway/tagada: Don't change FIAMUX when Security Override is set ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/69216/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/23565/ : SUCCESS -- To view, visit https://review.coreboot.org/25443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I55a8bcdc30bc67af2d3e9ccb8844eac599727108 Gerrit-Change-Number: 25443 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Mar 2018 13:33:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: soc/intel/denverton_ns: Implement AES-NI Lock
by build bot (Jenkins) (Code Review) 29 Mar '18

29 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25440 ) Change subject: soc/intel/denverton_ns: Implement AES-NI Lock ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/69213/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/23562/ : SUCCESS -- To view, visit https://review.coreboot.org/25440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6cf3484e46eebd3dc753d0903ea8555712b99b7e Gerrit-Change-Number: 25440 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Mar 2018 13:32:48 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: soc/intel/denverton_ns: Lock SPIBAR
by build bot (Jenkins) (Code Review) 29 Mar '18

29 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25441 ) Change subject: soc/intel/denverton_ns: Lock SPIBAR ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/69214/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/23563/ : SUCCESS -- To view, visit https://review.coreboot.org/25441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6934918d0c70245f03a1642f9a05e0110a205bc9 Gerrit-Change-Number: 25441 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Mar 2018 13:32:45 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

← Newer
1
...
6
7
8
9
10
11
12
...
140
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2018