coreboot-gerrit March 2018

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Change in coreboot[master]: Alkali: Add spd files
by build bot (Jenkins) (Code Review) 05 Mar '18

05 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25001 ) Change subject: Alkali: Add spd files ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22713/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68274/ : SUCCESS -- To view, visit https://review.coreboot.org/25001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8924ce97ea422ef1e9a5becb5ea2fda3bf77d8cf Gerrit-Change-Number: 25001 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Mar 2018 21:28:45 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge/Kconfig: Create a power restore option
by Richard Spiegel (Code Review) 05 Mar '18

05 Mar '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/25002 Change subject: soc/amd/stoneyridge/Kconfig: Create a power restore option ...................................................................... soc/amd/stoneyridge/Kconfig: Create a power restore option File soc/amd/stoneyridge/sm.c has a CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL that's not used at all and has no control. It's also not used in the build process. Remove the define from sm.c, create a true Kconfig definition and use it to define if power should be restored after a power failure/recovery. BUG=b:72873003 TEST=Build kahlee. Use serial output to check what is being programmed to RTC shadow. Build with and without selecting the Kconfig parameter. Then remove serial output and leave the parameter unselected (always S5 at power recovery). Change-Id: Iec82cb68cf1e2a820e610f12d8620488662232aa Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/sm.c M src/soc/amd/stoneyridge/southbridge.c 4 files changed, 17 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/25002/1 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index de1cb92..d29846a 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -382,4 +382,11 @@ int default 133 +config MAINBOARD_POWER_ON_AFTER_POWER_FAIL + bool + default n + help + If selected, after power fail power will be S0 if + previously at S0 else S5. + endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 3011af2..fae3089 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -48,6 +48,10 @@ #define PM_SERIRQ_MODE BIT(6) #define PM_SERIRQ_ENABLE BIT(7) +#define PM_RTC_SHADOW 0x5b /* state when power resumes */ +#define PM_S5_AT_POWER_RECOVERY 0x04 /* S5 */ +#define PM_RESTORE_ORIGINAL_POWER 0x07 /* S0 if previouusly at S0 */ + #define PM_EVT_BLK 0x60 #define WAK_STS BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */ #define PCIEXPWAK_STS BIT(14) diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/stoneyridge/sm.c index 9456cbf..1ea0560 100644 --- a/src/soc/amd/stoneyridge/sm.c +++ b/src/soc/amd/stoneyridge/sm.c @@ -32,10 +32,6 @@ #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - /* * The southbridge enables all USB controllers by default in SMBUS Control. * The southbridge enables SATA by default in SMBUS Control. diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 3d0cc74..ee4b58e 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -545,11 +545,17 @@ void southbridge_final(void *chip_info) { + uint8_t PM_RESTORED_POWER = PM_S5_AT_POWER_RECOVERY; + if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)) { agesawrapper_fchecfancontrolservice(); if (!IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)) enable_imc_thermal_zone(); } + if (IS_ENABLED(CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL)) + PM_RESTORED_POWER = PM_RESTORE_ORIGINAL_POWER; + printk(BIOS_DEBUG, "Power control 0x%02x\n", PM_RESTORED_POWER); + pm_write8(PM_RTC_SHADOW, PM_RESTORED_POWER); } /* -- To view, visit https://review.coreboot.org/25002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iec82cb68cf1e2a820e610f12d8620488662232aa Gerrit-Change-Number: 25002 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: Alkali: Add memory detection logic
by build bot (Jenkins) (Code Review) 05 Mar '18

05 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25000 ) Change subject: Alkali: Add memory detection logic ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22712/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68273/ : SUCCESS -- To view, visit https://review.coreboot.org/25000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ife6740ce0e8fe109ded7b954134171ba91895628 Gerrit-Change-Number: 25000 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Mar 2018 21:26:22 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Alkali: Add spd files
by Shelley Chen (Code Review) 05 Mar '18

05 Mar '18

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/25001 Change subject: Alkali: Add spd files ...................................................................... Alkali: Add spd files Add spd files for LPDDR3 BUG=b:73287172 BRANCH=None TEST=None Change-Id: I8924ce97ea422ef1e9a5becb5ea2fda3bf77d8cf Signed-off-by: Shelley Chen <shchen(a)chromium.org> --- A src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNN8GTALAR-NUD.spd.hex A src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNBJTALAR-NUD.spd.hex A src/mainboard/google/poppy/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex A src/mainboard/google/poppy/spd/micron_dimm_MT52L256M32D1PF-107.spd.hex A src/mainboard/google/poppy/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex M src/mainboard/google/poppy/variants/nami/Makefile.inc 6 files changed, 88 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/25001/1 diff --git a/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNN8GTALAR-NUD.spd.hex b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNN8GTALAR-NUD.spd.hex new file mode 100644 index 0000000..5c1332e --- /dev/null +++ b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNN8GTALAR-NUD.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 03 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 38 47 54 41 4C 41 52 2D 4E +55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNBJTALAR-NUD.spd.hex b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNBJTALAR-NUD.spd.hex new file mode 100644 index 0000000..7c7c8d2 --- /dev/null +++ b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNBJTALAR-NUD.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 42 4A 54 41 4C 41 52 2D 4E +55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex b/src/mainboard/google/poppy/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex new file mode 100644 index 0000000..8e6030b --- /dev/null +++ b/src/mainboard/google/poppy/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 1A 05 0A 03 11 01 08 09 00 00 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 B1 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 2B 1F +4D 54 35 32 4C 31 47 33 32 44 34 50 47 2D 31 30 +37 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/micron_dimm_MT52L256M32D1PF-107.spd.hex b/src/mainboard/google/poppy/spd/micron_dimm_MT52L256M32D1PF-107.spd.hex new file mode 100644 index 0000000..57b1870 --- /dev/null +++ b/src/mainboard/google/poppy/spd/micron_dimm_MT52L256M32D1PF-107.spd.hex @@ -0,0 +1,17 @@ +91 20 F1 03 05 19 05 03 03 11 01 08 09 00 00 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 10 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 E5 37 +4D 54 35 32 4C 32 35 36 4D 33 32 44 31 50 46 2D +31 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + diff --git a/src/mainboard/google/poppy/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex b/src/mainboard/google/poppy/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex new file mode 100644 index 0000000..fb90339 --- /dev/null +++ b/src/mainboard/google/poppy/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 00 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 A1 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 3A 64 +4D 54 35 32 4C 35 31 32 4D 33 32 44 32 50 46 2D +31 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/variants/nami/Makefile.inc b/src/mainboard/google/poppy/variants/nami/Makefile.inc index b943dab..8a65493 100644 --- a/src/mainboard/google/poppy/variants/nami/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nami/Makefile.inc @@ -7,6 +7,13 @@ SPD_SOURCES += hynix_dimm_H5AN4G6NBJR-UHC # 0b0011 SPD_SOURCES += hynix_dimm_H5ANAG6NAMR-UHC # 0b0100 +# Used when PCH_MEM_CONFIG4 = 1 (LPDDR3) +SECONDARY_SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107 # 0b0000 +SECONDARY_SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 # 0b0001 +SECONDARY_SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR-NUD # 0b0010 +SECONDARY_SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD # 0b0011 +SECONDARY_SPD_SOURCES += micron_dimm_MT52L1G32D4PG-107 # 0b0100 + bootblock-y += gpio.c romstage-y += memory.c -- To view, visit https://review.coreboot.org/25001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8924ce97ea422ef1e9a5becb5ea2fda3bf77d8cf Gerrit-Change-Number: 25001 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com>

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Change in coreboot[master]: Alkali: Add memory detection logic
by Shelley Chen (Code Review) 05 Mar '18

05 Mar '18

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/25000 Change subject: Alkali: Add memory detection logic ...................................................................... Alkali: Add memory detection logic Alkali will use LPDDR3, so need to have Nami support both DDR4 and LPDDR3. We do this with the PCH_MEM_CONFIG4 GPIO. BUG=b:73514687 BRANCH=None TEST=None Change-Id: Ife6740ce0e8fe109ded7b954134171ba91895628 Signed-off-by: Shelley Chen <shchen(a)chromium.org> --- M src/mainboard/google/poppy/variants/nami/include/variant/gpio.h M src/mainboard/google/poppy/variants/nami/memory.c 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/25000/1 diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/gpio.h b/src/mainboard/google/poppy/variants/nami/include/variant/gpio.h index 3dfe92f..98450f6 100644 --- a/src/mainboard/google/poppy/variants/nami/include/variant/gpio.h +++ b/src/mainboard/google/poppy/variants/nami/include/variant/gpio.h @@ -30,6 +30,7 @@ #define GPIO_MEM_CONFIG_1 GPP_C13 #define GPIO_MEM_CONFIG_2 GPP_C14 #define GPIO_MEM_CONFIG_3 GPP_C15 +#define GPIO_MEM_CONFIG_4 GPP_E15 /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK diff --git a/src/mainboard/google/poppy/variants/nami/memory.c b/src/mainboard/google/poppy/variants/nami/memory.c index dec7626..e6c169c 100644 --- a/src/mainboard/google/poppy/variants/nami/memory.c +++ b/src/mainboard/google/poppy/variants/nami/memory.c @@ -14,6 +14,8 @@ */ #include <baseboard/variants.h> +#include <gpio.h> +#include <variant/gpio.h> #include <string.h> /* Rcomp resistor */ @@ -31,8 +33,17 @@ void variant_memory_params(struct memory_params *p) { + int pch_mem_config4 = gpio_get(GPIO_MEM_CONFIG_4); + + /* default to DDR4 */ memset(p, 0, sizeof(*p)); p->type = MEMORY_DDR4; + p->use_sec_spd = 0; + if (pch_mem_config4 == 1) { + /* set to LPDDR3 */ + p->type = MEMORY_LPDDR3; + p->use_sec_spd = 1; + } /* Rcomp resistor values are different for SDP and DDP. */ if (ddp_bitmap & MEM_ID(variant_memory_sku())) { -- To view, visit https://review.coreboot.org/25000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ife6740ce0e8fe109ded7b954134171ba91895628 Gerrit-Change-Number: 25000 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com>

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Change in coreboot[master]: mb/google/zoombini/variants/meowth: enable SAR power
by build bot (Jenkins) (Code Review) 05 Mar '18

05 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24962 ) Change subject: mb/google/zoombini/variants/meowth: enable SAR power ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68271/ : SUCCESS -- To view, visit https://review.coreboot.org/24962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2ea44b03336b901af68f9092f3386b42d8516b72 Gerrit-Change-Number: 24962 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Mar 2018 18:20:29 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy: Allow use of optional secondary SPD
by build bot (Jenkins) (Code Review) 05 Mar '18

05 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24972 ) Change subject: mb/google/poppy: Allow use of optional secondary SPD ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22710/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68270/ : SUCCESS -- To view, visit https://review.coreboot.org/24972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3add65ead99c510f2d6ec899fbf2cb9a06c79b0c Gerrit-Change-Number: 24972 Gerrit-PatchSet: 4 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Mar 2018 17:17:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy: Allow use of optional secondary SPD
by build bot (Jenkins) (Code Review) 05 Mar '18

05 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24972 ) Change subject: mb/google/poppy: Allow use of optional secondary SPD ...................................................................... Patch Set 3: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/68269/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/22673/ : SUCCESS -- To view, visit https://review.coreboot.org/24972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3add65ead99c510f2d6ec899fbf2cb9a06c79b0c Gerrit-Change-Number: 24972 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Mar 2018 17:13:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: src/soc/amd/stoneyridge: cleanup southbridge.c
by Martin Roth (Code Review) 05 Mar '18

05 Mar '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/24998 ) Change subject: src/soc/amd/stoneyridge: cleanup southbridge.c ...................................................................... Patch Set 1: (8 comments) https://review.coreboot.org/#/c/24998/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/24998/1//COMMIT_MSG@10 PS1, Line 10: Add code to enable decode of FCH ACPI : MMIO regions. Factor out to functions, device power-on : code for AMBA and UART. Add FCH I2C device power-on code. Add code for : FCH to decode TPM memory and IO regions. A lot of these changes aren't really cleanup. Most of them should go in individual commits. Also typically you'd want to make this into a list format: * Limit dependency on vendorcode header files and add appropriate definitions to southbridge.h. * Factor out to functions, device power-on code for AMBA and UART. https://review.coreboot.org/#/c/24998/1/src/soc/amd/stoneyridge/include/soc… File src/soc/amd/stoneyridge/include/soc/southbridge.h: https://review.coreboot.org/#/c/24998/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 34: /* FCH ACPI MMIO register base addresses */ : #define ACPI_MMIO_BASE 0xFED80000ul : #define FCH_ACPI_MMIO_SMBUS_PCI_BASE ACPI_MMIO_BASE + 0x000 : #define FCH_ACPI_MMIO_SMI_BASE ACPI_MMIO_BASE + 0x200 : #define FCH_ACPI_MMIO_PMIO_BASE ACPI_MMIO_BASE + 0x300 : #define FCH_ACPI_MMIO_PMIO2_BASE ACPI_MMIO_BASE + 0x400 : #define FCH_ACPI_MMIO_BIOS_RAM_BASE ACPI_MMIO_BASE + 0x500 : #define FCH_ACPI_MMIO_CMOS_RAM_BASE ACPI_MMIO_BASE + 0x600 : #define FCH_ACPI_MMIO_CMOS_BASE ACPI_MMIO_BASE + 0x700 : #define FCH_ACPI_MMIO_ASF_BASE ACPI_MMIO_BASE + 0x900 : #define FCH_ACPI_MMIO_SMBUS_BASE ACPI_MMIO_BASE + 0xA00 : #define FCH_ACPI_MMIO_WATCHDOG_BASE ACPI_MMIO_BASE + 0xB00 : #define FCH_ACPI_MMIO_HPET_BASE ACPI_MMIO_BASE + 0xC00 : #define FCH_ACPI_MMIO_IOMUX_BASE ACPI_MMIO_BASE + 0xD00 : #define FCH_ACPI_MMIO_MISC_BASE ACPI_MMIO_BASE + 0xE00 : #define FCH_ACPI_MMIO_GFX_DAC_BASE ACPI_MMIO_BASE + 0x1400 : #define FCH_ACPI_MMIO_GPIO_BANK0_BASE ACPI_MMIO_BASE + 0x1500 : #define FCH_ACPI_MMIO_GPIO_BANK1_BASE ACPI_MMIO_BASE + 0x1600 : #define FCH_ACPI_MMIO_GPIO_BANK2_BASE ACPI_MMIO_BASE + 0x1700 : #define FCH_ACPI_MMIO_XHCI_BASE ACPI_MMIO_BASE + 0x1C00 : #define FCH_ACPI_MMIO_ACDC_BASE ACPI_MMIO_BASE + 0x1D00 : #define FCH_ACPI_MMIO_AOAC_BASE ACPI_MMIO_BASE + 0x1E00 All of these should go in stoneyridge/include/soc/iomap.h. Some of these are already defined: #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 #define APU_SMI_BASE 0xfed80200 #define PM_MMIO_BASE 0xfed80300 #define BIOSRAM_MMIO_BASE 0xfed80500 #define XHCI_ACPI_PM_MMIO_BASE 0xfed81c00 #define APU_UART0_BASE 0xfedc6000 #define APU_UART1_BASE 0xfedc8000 https://review.coreboot.org/#/c/24998/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 368: Tabs instead of spaces please https://review.coreboot.org/#/c/24998/1/src/soc/amd/stoneyridge/southbridge… File src/soc/amd/stoneyridge/southbridge.c: https://review.coreboot.org/#/c/24998/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 300: void configure_stoneyridge_i2c(void) Add in a separate commit please. https://review.coreboot.org/#/c/24998/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 310: /* Wait for the I2C devices to indicate power and clock OK */ : do { : udelay(100); : status = is_aoac_device_enabled(AOAC_D3_STATE_I2C0); : status &= is_aoac_device_enabled(AOAC_D3_STATE_I2C1); : status &= is_aoac_device_enabled(AOAC_D3_STATE_I2C2); : status &= is_aoac_device_enabled(AOAC_D3_STATE_I2C3); : } while (!(status)); Do we need to delay here? Are these devices used immediately? https://review.coreboot.org/#/c/24998/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 320: void sb_acpi_mmio_decode(void) : { : u8 byte; : : /* Enable ACPI MMIO range 0xFED80000 - 0xFED81FFF */ : outb(PM_ISA_CONTROL, PM_INDEX); : byte = inb(PM_DATA); : byte |= MMIO_EN; : outb(PM_ISA_CONTROL, PM_INDEX); : outb(byte, PM_DATA); : } While adding this is fine, i don't think it's needed here since it's one of the first chipset specific things we do in bootblock. It should also go into a separate commit. https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/amd/stoneyridge/… https://review.coreboot.org/#/c/24998/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 476: void sb_tpm_decode(void) : { : /* Enable TPM decoding to FCH */ : u32 value = pci_read_config32(SOC_LPC_DEV, : LPC_TRUSTED_PLATFORM_MODULE); : value |= (TPM_12_EN | TPM_LEGACY_EN); : pci_write_config32(SOC_LPC_DEV, LPC_TRUSTED_PLATFORM_MODULE, value); : } : : void sb_tpm_decode_spi(void) : { : /* Enable TPM decoding to FCH */ : sb_tpm_decode(); : : /* Make sure SPI base register is programmed */ : sb_spibase(); : : /* Route TPM accesses to SPI */ Can we do these in a separate commit? https://review.coreboot.org/#/c/24998/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 551: sb_set_spi100(SPI_SPEED_33M, : SPI_SPEED_33M, : SPI_SPEED_16M, : SPI_SPEED_16M); Can we do this in a separate commit? -- To view, visit https://review.coreboot.org/24998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I45c1d1d7edc864000282c7ca4e2b8f2a14ea9eac Gerrit-Change-Number: 24998 Gerrit-PatchSet: 1 Gerrit-Owner: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marshall Dawson <marshall.dawson(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Mar 2018 16:49:42 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/haswell; sb/intel/lynxpoint: Enable VT-d and X2APIC
by build bot (Jenkins) (Code Review) 05 Mar '18

05 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24983 ) Change subject: nb/intel/haswell;sb/intel/lynxpoint: Enable VT-d and X2APIC ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68268/ : SUCCESS -- To view, visit https://review.coreboot.org/24983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib8f2fed9ae08491779e76f7d1ddc1bd3eed45ac7 Gerrit-Change-Number: 24983 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Mar 2018 16:25:45 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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