coreboot-gerrit February 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/fsp_baytrail: Fix vboot and TPM support
by Philipp Deppenwiese (Code Review) 16 Feb '18

16 Feb '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/23798 Change subject: soc/fsp_baytrail: Fix vboot and TPM support ...................................................................... soc/fsp_baytrail: Fix vboot and TPM support * Add default for VBOOT_STARTS_IN_* romstage. * Remove unecessary TPM ACPI code which is normally done inside the tpm driver itself. Change-Id: Id33b7f2b9269593cd3e62f63752a660a144600da Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_baytrail/acpi/lpc.asl 2 files changed, 3 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/23798/1 diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 549ea55..601767b 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -47,6 +47,9 @@ # Microcode header files are delivered in FSP package select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN +config VBOOT + select VBOOT_STARTS_IN_ROMSTAGE + config SOC_INTEL_FSP_BAYTRAIL_MD bool default n diff --git a/src/soc/intel/fsp_baytrail/acpi/lpc.asl b/src/soc/intel/fsp_baytrail/acpi/lpc.asl index 17d6f43..00aac51 100644 --- a/src/soc/intel/fsp_baytrail/acpi/lpc.asl +++ b/src/soc/intel/fsp_baytrail/acpi/lpc.asl @@ -135,27 +135,4 @@ // Include mainboard's superio.asl file. #include "acpi/superio.asl" - -#if IS_ENABLED(CONFIG_LPC_TPM) - Device (TPM) // Trusted Platform Module - { - Name(_HID, EISAID("IFX0102")) - Name(_CID, 0x310cd041) - Name(_UID, 1) - - Method(_STA, 0) - { - If (TPMP) { - Return (0xf) - } - Return (0x0) - } - - Name(_CRS, ResourceTemplate() { - IO (Decode16, 0x2e, 0x2e, 0x01, 0x02) - IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10) - Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) - }) - } -#endif } -- To view, visit https://review.coreboot.org/23798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id33b7f2b9269593cd3e62f63752a660a144600da Gerrit-Change-Number: 23798 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: arch/riscv: Don't set up virtual memory
by build bot (Jenkins) (Code Review) 16 Feb '18

16 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23772 ) Change subject: arch/riscv: Don't set up virtual memory ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67590/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22108/ : SUCCESS -- To view, visit https://review.coreboot.org/23772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4e69d15f8ee540d2f98c342bc4ec0c00fb48def0 Gerrit-Change-Number: 23772 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Feb 2018 13:10:07 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/nvidia/tegra210: add missing bl31 params
by build bot (Jenkins) (Code Review) 16 Feb '18

16 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23783 ) Change subject: soc/nvidia/tegra210: add missing bl31 params ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67586/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22104/ : SUCCESS -- To view, visit https://review.coreboot.org/23783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7a47647216a154894e6c2c1fd3b304e18e85c6a5 Gerrit-Change-Number: 23783 Gerrit-PatchSet: 2 Gerrit-Owner: Andre Heider <a.heider(a)gmail.com> Gerrit-Reviewer: Andre Heider <a.heider(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Feb 2018 13:08:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/nvidia/tegra210: set up the clock of the chosen UART
by build bot (Jenkins) (Code Review) 16 Feb '18

16 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23796 ) Change subject: soc/nvidia/tegra210: set up the clock of the chosen UART ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67589/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22107/ : SUCCESS -- To view, visit https://review.coreboot.org/23796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ife209d42af83459136a019c21c2a069396ab36db Gerrit-Change-Number: 23796 Gerrit-PatchSet: 1 Gerrit-Owner: Andre Heider <a.heider(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Feb 2018 12:58:35 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/nvidia/tegra210: define missing UART clocks sources
by Jonathan Neuschäfer (Code Review) 16 Feb '18

16 Feb '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/23794 ) Change subject: soc/nvidia/tegra210: define missing UART clocks sources ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/23794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7243812fba6f30f1db4db868b258794e7b248be8 Gerrit-Change-Number: 23794 Gerrit-PatchSet: 1 Gerrit-Owner: Andre Heider <a.heider(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Feb 2018 12:57:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/nvidia/tegra210: add missing bl31 params
by Jonathan Neuschäfer (Code Review) 16 Feb '18

16 Feb '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/23783 ) Change subject: soc/nvidia/tegra210: add missing bl31 params ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/23783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7a47647216a154894e6c2c1fd3b304e18e85c6a5 Gerrit-Change-Number: 23783 Gerrit-PatchSet: 2 Gerrit-Owner: Andre Heider <a.heider(a)gmail.com> Gerrit-Reviewer: Andre Heider <a.heider(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Feb 2018 12:56:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/nvidia/tegra210: define missing UART clocks sources
by build bot (Jenkins) (Code Review) 16 Feb '18

16 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23794 ) Change subject: soc/nvidia/tegra210: define missing UART clocks sources ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67588/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22106/ : SUCCESS -- To view, visit https://review.coreboot.org/23794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7243812fba6f30f1db4db868b258794e7b248be8 Gerrit-Change-Number: 23794 Gerrit-PatchSet: 1 Gerrit-Owner: Andre Heider <a.heider(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Feb 2018 12:52:25 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/nvidia/tegra210: add missing bl31 params
by Andre Heider (Code Review) 16 Feb '18

16 Feb '18

Andre Heider has posted comments on this change. ( https://review.coreboot.org/23783 ) Change subject: soc/nvidia/tegra210: add missing bl31 params ...................................................................... Patch Set 2: I polished up and added the remaining patches in v2, this should hopefully give a better picture -- To view, visit https://review.coreboot.org/23783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7a47647216a154894e6c2c1fd3b304e18e85c6a5 Gerrit-Change-Number: 23783 Gerrit-PatchSet: 2 Gerrit-Owner: Andre Heider <a.heider(a)gmail.com> Gerrit-Reviewer: Andre Heider <a.heider(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Feb 2018 12:41:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: arch/riscv: Pass the bootrom-provided FDT to the payload
by Jonathan Neuschäfer (Code Review) 16 Feb '18

16 Feb '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/23797 Change subject: arch/riscv: Pass the bootrom-provided FDT to the payload ...................................................................... arch/riscv: Pass the bootrom-provided FDT to the payload The RISC-V boot protocol foresees that at every stage boundary (bootrom to boot loader, boot loader -> OS), register a0 contains the Hart ID and a1 contains the physical address of the Flattened Device Tree that the stage shall use. As a first step, pass the bootrom-provided FDT to the payload, unmodified. Change-Id: I468bc64a47153d564087235f1c7e2d10e3d7a658 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/arch/riscv/boot.c M src/arch/riscv/bootblock.S A src/arch/riscv/include/arch/boot.h M src/arch/riscv/payload.S M src/arch/riscv/stages.c 5 files changed, 78 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/23797/1 diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index b73f3ca..d7233fe 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -15,20 +15,35 @@ #include <program_loading.h> #include <vm.h> +#include <arch/boot.h> #include <arch/encoding.h> #include <rules.h> #include <console/console.h> +/* + * A pointer to the Flattened Device Tree passed to coreboot by the boot ROM. + * Presumably this FDT is also in ROM. + * + * This pointer is only used in ramstage! + */ +const void *rom_fdt; + void arch_prog_run(struct prog *prog) { void (*doit)(void *) = prog_entry(prog); - void riscvpayload(const char *configstring, void *payload); - const char *config = NULL; + void riscvpayload(const void *fdt, void *payload); if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { - printk(BIOS_SPEW, "Config string: '%s'\n", config); + /* + * FIXME: This is wrong and will crash. Linux can't (in early + * boot) access memory that's before its own loading address. + * We need to copy the FDT to a place where Linux can access it. + */ + const void *fdt = rom_fdt; + + printk(BIOS_SPEW, "FDT is at %p\n", fdt); printk(BIOS_SPEW, "OK, let's go\n"); - riscvpayload(config, doit); + riscvpayload(fdt, doit); } doit(prog_entry_arg(prog)); diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 43bca90..0b5a2b2 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -25,7 +25,14 @@ .globl _start _start: - + # The boot ROM may pass the following arguments to coreboot: + # a0: the value of mhartid + # a1: a pointer to the flattened devicetree + # + # Preserve only the FDT pointer. We can query mhartid ourselves at any + # time. + # + csrw mscratch, a1 # N.B. This only works on low 4G of the address space # and the stack must be page-aligned. diff --git a/src/arch/riscv/include/arch/boot.h b/src/arch/riscv/include/arch/boot.h new file mode 100644 index 0000000..24c1bed --- /dev/null +++ b/src/arch/riscv/include/arch/boot.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Jonathan Neuschäfer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ARCH_RISCV_INCLUDE_ARCH_BOOT_H +#define ARCH_RISCV_INCLUDE_ARCH_BOOT_H + +extern const void *rom_fdt; + +#endif diff --git a/src/arch/riscv/payload.S b/src/arch/riscv/payload.S index a189adf..1b8cb96 100644 --- a/src/arch/riscv/payload.S +++ b/src/arch/riscv/payload.S @@ -1,6 +1,9 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2016 Google Inc + * Copyright (C) 2018 Jonathan Neuschäfer + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -11,17 +14,22 @@ * GNU General Public License for more details. */ -// "return" to a payload pointed to by a1 with -// an M-mode pointer (or, to upper levels, physical address) -// to the config string in a0. +// "return" to a payload. a0: FDT, a1: entry point .global riscvpayload riscvpayload: - mv t0,a1 - csrw mepc, t0 - csrr t0, mstatus - li t1, ~(3<<11) - and t0, t0, t1 - li t2, (1<<11) - or t0, t0, t2 - csrw mstatus, t0 + /* Load the entry point */ + mv t0, a1 + csrw mepc, t0 + csrr t0, mstatus + + /* Set mstatus.MPP (the previous privilege mode) to supervisor mode */ + li t1, ~(3<<11) + and t0, t0, t1 + li t2, (1<<11) + or t0, t0, t2 + csrw mstatus, t0 + + /* Pass the right arguments and jump! */ + mv a1, a0 + csrr a0, mhartid mret diff --git a/src/arch/riscv/stages.c b/src/arch/riscv/stages.c index 053fd76..8075476 100644 --- a/src/arch/riscv/stages.c +++ b/src/arch/riscv/stages.c @@ -24,9 +24,20 @@ * linker script. */ +#include <arch/boot.h> +#include <arch/encoding.h> #include <arch/stages.h> +#include <rules.h> void stage_entry(void) { + /* + * Save the FDT pointer before entering ramstage, because mscratch + * might be overwritten in the trap handler, and there is code in + * ramstage that generates misaligned access faults. + */ + if (ENV_RAMSTAGE) + rom_fdt = (const void *)read_csr(mscratch); + main(); } -- To view, visit https://review.coreboot.org/23797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I468bc64a47153d564087235f1c7e2d10e3d7a658 Gerrit-Change-Number: 23797 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: soc/nvidia/tegra210: add console UART helper functions
by Andre Heider (Code Review) 16 Feb '18

16 Feb '18

Andre Heider has uploaded this change for review. ( https://review.coreboot.org/23795 Change subject: soc/nvidia/tegra210: add console UART helper functions ...................................................................... soc/nvidia/tegra210: add console UART helper functions These small helper functions aim at supporting the user setting CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx. Change-Id: I71423a0424927ff383bcbf194c9fbaa452d810a1 Signed-off-by: Andre Heider <a.heider(a)gmail.com> --- A src/soc/nvidia/tegra210/include/soc/console_uart.h 1 file changed, 113 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/23795/1 diff --git a/src/soc/nvidia/tegra210/include/soc/console_uart.h b/src/soc/nvidia/tegra210/include/soc/console_uart.h new file mode 100644 index 0000000..fc30481 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/console_uart.h @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Andre Heider <a.heider(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_CONSOLE_UART_H__ +#define __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_CONSOLE_UART_H__ + +#include <soc/clock.h> + +enum console_uart_id { + UART_ID_NONE = -1, + UART_ID_A = 0, + UART_ID_B = 1, + UART_ID_C = 2, + UART_ID_D = 3, + UART_ID_E = 4, +}; + +static inline enum console_uart_id console_uart_get_id(void) +{ + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTA)) + return UART_ID_A; + + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTB)) + return UART_ID_B; + + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTC)) + return UART_ID_C; + + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTD)) + return UART_ID_D; + + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTE)) + return UART_ID_E; + + return UART_ID_NONE; +} + +static inline void *console_uart_clk_rst_reg(void) +{ + switch (console_uart_get_id()) { + case UART_ID_NONE: + return NULL; + case UART_ID_A: + return CLK_RST_REG(clk_src_uarta); + case UART_ID_B: + return CLK_RST_REG(clk_src_uartb); + case UART_ID_C: + return CLK_RST_REG(clk_src_uartc); + case UART_ID_D: + return CLK_RST_REG(clk_src_uartd); + case UART_ID_E: + return CLK_RST_REG(clk_src_uarte); + } + + return NULL; +} + +static inline uint32_t console_uart_clk_src_dev_id(void) +{ + switch (console_uart_get_id()) { + case UART_ID_NONE: + return 0; + case UART_ID_A: + return CLK_SRC_DEV_ID(UARTA, PLLP); + case UART_ID_B: + return CLK_SRC_DEV_ID(UARTB, PLLP); + case UART_ID_C: + return CLK_SRC_DEV_ID(UARTC, PLLP); + case UART_ID_D: + return CLK_SRC_DEV_ID(UARTD, PLLP); + case UART_ID_E: + return CLK_SRC_DEV_ID(UARTE, PLLP); + } + + return 0; +} + +static inline void console_uart_clock_enable_clear_reset(void) +{ + switch (console_uart_get_id()) { + case UART_ID_NONE: + return; + case UART_ID_A: + clock_enable_clear_reset_l(CLK_L_UARTA); + break; + case UART_ID_B: + clock_enable_clear_reset_l(CLK_L_UARTB); + break; + case UART_ID_C: + clock_enable_clear_reset_h(CLK_H_UARTC); + break; + case UART_ID_D: + clock_enable_clear_reset_u(CLK_U_UARTD); + break; + case UART_ID_E: + clock_enable_clear_reset_u(CLK_U_UARTE); + break; + } +} + +#endif /* __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_CONSOLE_UART_H__ */ -- To view, visit https://review.coreboot.org/23795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I71423a0424927ff383bcbf194c9fbaa452d810a1 Gerrit-Change-Number: 23795 Gerrit-PatchSet: 1 Gerrit-Owner: Andre Heider <a.heider(a)gmail.com>

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coreboot-gerrit February 2018