coreboot-gerrit February 2018

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Change in coreboot[master]: soc/nvidia/tegra210: set up the clock of the chosen UART
by Andre Heider (Code Review) 16 Feb '18

16 Feb '18

Andre Heider has uploaded this change for review. ( https://review.coreboot.org/23796 Change subject: soc/nvidia/tegra210: set up the clock of the chosen UART ...................................................................... soc/nvidia/tegra210: set up the clock of the chosen UART Don't always set up UARTA, but instead honor CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx and set up the clock of the chosen UART. Now the matching clock for the used UART is set up (the UART driver uses CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS, which in return is already based on CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx). Change-Id: Ife209d42af83459136a019c21c2a069396ab36db Signed-off-by: Andre Heider <a.heider(a)gmail.com> --- M src/soc/nvidia/tegra210/clock.c 1 file changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/23796/1 diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c index cc8af55..ba1efdc 100644 --- a/src/soc/nvidia/tegra210/clock.c +++ b/src/soc/nvidia/tegra210/clock.c @@ -21,6 +21,7 @@ #include <soc/clk_rst.h> #include <soc/clock.h> #include <soc/clst_clk.h> +#include <soc/console_uart.h> #include <soc/flow.h> #include <soc/maincpu.h> #include <soc/pmc.h> @@ -489,12 +490,15 @@ */ void clock_early_uart(void) { - write32(CLK_RST_REG(clk_src_uarta), - CLK_SRC_DEV_ID(UARTA, PLLP) << CLK_SOURCE_SHIFT | + if (console_uart_get_id() == UART_ID_NONE) + return; + + write32(console_uart_clk_rst_reg(), + console_uart_clk_src_dev_id() << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_PLLP_KHZ, 1843)); - clock_enable_clear_reset_l(CLK_L_UARTA); + console_uart_clock_enable_clear_reset(); } /* Enable output clock (CLK1~3) for external peripherals. */ -- To view, visit https://review.coreboot.org/23796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ife209d42af83459136a019c21c2a069396ab36db Gerrit-Change-Number: 23796 Gerrit-PatchSet: 1 Gerrit-Owner: Andre Heider <a.heider(a)gmail.com>

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Change in coreboot[master]: soc/nvidia/tegra210: define missing UART clocks sources
by Andre Heider (Code Review) 16 Feb '18

16 Feb '18

Andre Heider has uploaded this change for review. ( https://review.coreboot.org/23794 Change subject: soc/nvidia/tegra210: define missing UART clocks sources ...................................................................... soc/nvidia/tegra210: define missing UART clocks sources These are required to honor CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx later on. Change-Id: I7243812fba6f30f1db4db868b258794e7b248be8 Signed-off-by: Andre Heider <a.heider(a)gmail.com> --- M src/soc/nvidia/tegra210/include/soc/clock.h 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/23794/1 diff --git a/src/soc/nvidia/tegra210/include/soc/clock.h b/src/soc/nvidia/tegra210/include/soc/clock.h index ba8715d..46e1e96 100644 --- a/src/soc/nvidia/tegra210/include/soc/clock.h +++ b/src/soc/nvidia/tegra210/include/soc/clock.h @@ -242,6 +242,14 @@ PLLC4_OUT1, PLLC4_OUT1_L, CLK_M, PLLC4_OUT0), CLK_SRC_DEVICE(UARTA, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2), + CLK_SRC_DEVICE(UARTB, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4, + PLLC4_OUT1, CLK_M, PLLC4_OUT2), + CLK_SRC_DEVICE(UARTC, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4, + PLLC4_OUT1, CLK_M, PLLC4_OUT2), + CLK_SRC_DEVICE(UARTD, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4, + PLLC4_OUT1, CLK_M, PLLC4_OUT2), + CLK_SRC_DEVICE(UARTE, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4, + PLLC4_OUT1, CLK_M, PLLC4_OUT2), CLK_SRC_DEVICE(i2s1, PLLA, UNUSED1, CLK_S, UNUSED3, PLLP, UNUSED5, CLK_M, UNUSED7), CLK_SRC_DEVICE(extperiph1, PLLA, CLK_S, PLLP, CLK_M, PLLE, UNUSED5, -- To view, visit https://review.coreboot.org/23794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7243812fba6f30f1db4db868b258794e7b248be8 Gerrit-Change-Number: 23794 Gerrit-PatchSet: 1 Gerrit-Owner: Andre Heider <a.heider(a)gmail.com>

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Change in coreboot[master]: soc/nvidia/tegra210: add missing bl31 params
by Andre Heider (Code Review) 16 Feb '18

16 Feb '18

Hello Julius Werner, Jonathan Neuschäfer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/23783 to look at the new patch set (#2). Change subject: soc/nvidia/tegra210: add missing bl31 params ...................................................................... soc/nvidia/tegra210: add missing bl31 params The ATF tegra210 platform supports more than the currently used 'tzdram_size' parameter, see plat/nvidia/tegra/include/tegra_private.h in the ATF tree. Add the missing parameters and set them accordingly. The passed UART id is based on CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx, so ATF now uses the same port for console output as coreboot. Successfully tested with UARTB. Change-Id: I7a47647216a154894e6c2c1fd3b304e18e85c6a5 Signed-off-by: Andre Heider <a.heider(a)gmail.com> --- M src/soc/nvidia/tegra210/arm_tf.c 1 file changed, 31 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/23783/2 -- To view, visit https://review.coreboot.org/23783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7a47647216a154894e6c2c1fd3b304e18e85c6a5 Gerrit-Change-Number: 23783 Gerrit-PatchSet: 2 Gerrit-Owner: Andre Heider <a.heider(a)gmail.com> Gerrit-Reviewer: Andre Heider <a.heider(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/cavium: Add rom header images
by build bot (Jenkins) (Code Review) 16 Feb '18

16 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23793 ) Change subject: soc/cavium: Add rom header images ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67585/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/22103/ : SUCCESS -- To view, visit https://review.coreboot.org/23793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icd9cdf882ccdac591bec7240f1c7694fe0c0ad4d Gerrit-Change-Number: 23793 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Feb 2018 12:22:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/cavium/bootblock: Get rid of register X1
by build bot (Jenkins) (Code Review) 16 Feb '18

16 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23792 ) Change subject: soc/cavium/bootblock: Get rid of register X1 ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67584/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/22102/ : SUCCESS -- To view, visit https://review.coreboot.org/23792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9324ea9de24ba4baaef9dde890c443dd0f921ad9 Gerrit-Change-Number: 23792 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Feb 2018 12:22:35 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/cavium: Add rom header images
by Patrick Rudolph (Code Review) 16 Feb '18

16 Feb '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/23793 Change subject: soc/cavium: Add rom header images ...................................................................... soc/cavium: Add rom header images Add HEX rom header images, required to boot NBL1FW. Change-Id: Icd9cdf882ccdac591bec7240f1c7694fe0c0ad4d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/cavium/cn81xx/Makefile.inc M src/soc/cavium/common/Makefile.inc A src/soc/cavium/common/rom_clib_s_nbl1fw.bin.hex A src/soc/cavium/common/rom_csib_s_nbl1fw.bin.hex 4 files changed, 53 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/23793/1 diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc index f835b09..c910b08 100644 --- a/src/soc/cavium/cn81xx/Makefile.inc +++ b/src/soc/cavium/cn81xx/Makefile.inc @@ -97,29 +97,4 @@ CPPFLAGS_common += -Isrc/soc/cavium/common/include/soc/bdk/ #CPPFLAGS_common += -Isrc/soc/cavium/common/include/soc/bdk/libdram -# FIXME: Generate the ROM code load information block structure. -# For NBL1FW the first 256 bytes are ignored and should be zeros. -# For TLB1FW the first 256 bytes should be randomized. -#FIXME: Generate bootblock more intelligently -$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin - @printf "Generating: $(subst $(obj)/,,$(@))\n" -# cp $< $@ -# @mkdir -p $(dir $@) -# @$(IBSTOOL) --from=$< --to=$@ --nontrusted - # Insert CLIB at 0x10000 and CSIB at 0x10100 -# dd if=/dev/zero bs=1k count=512 2>/dev/null | tr '\000' '\377' > $@ - dd if=rom_clib_s_nbl1fw.bin of=$@ bs=1 seek=$$((0x10000)) conv=notrunc - dd if=rom_csib_s_nbl1fw.bin of=$@ bs=1 seek=$$((0x10100)) conv=notrunc - # Insert header at 0x20000 -# According to OFFSET field description, first 256 bytes of NBL1FW are ignored. -# dd if=/dev/zero bs=1 count=256 2>/dev/null | tr '\000' '\377' > _pad256.bin - - # FIXME: 0x20000-0x20100 should be ignored, but Cavium's image populates it. - ## dd if=_pad256.bin of=$@ bs=1 seek=$$((0x20000)) conv=notrunc 2>/dev/null - # TODO inject length of firmware at offset 0x04 of header - ##dd if=$< of=$@ bs=1 seek=$$((0x20100)) conv=notrunc 2>/dev/null - dd if=$< of=$@ bs=1 seek=$$((0x20000)) conv=notrunc -# dd if=nbl1fw_header.bin of=$@ bs=1 seek=$$((0x20000)) conv=notrunc -# # TODO: Calculate CRC32 of image and inject at offset 0x10 of header - endif diff --git a/src/soc/cavium/common/Makefile.inc b/src/soc/cavium/common/Makefile.inc index feeeb6e..5f47a1d 100644 --- a/src/soc/cavium/common/Makefile.inc +++ b/src/soc/cavium/common/Makefile.inc @@ -45,4 +45,25 @@ CPPFLAGS_common += -Isrc/soc/cavium/common/include +ROM_HEADER_BIN := $(objgenerated)/rom_header.bin +ROM_HEADER_SOURCES += rom_clib_s_nbl1fw +ROM_HEADER_SOURCES += rom_csib_s_nbl1fw + +ROM_HEADER_DEPS := $(foreach f, $(ROM_HEADER_SOURCES), src/soc/cavium/common/$(f).bin.hex) + +# Include ROM header +$(ROM_HEADER_BIN): $(ROM_HEADER_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(ROM_HEADER_BIN) + @printf " GEN $(subst $(obj)/,,$(@))\n" + # Insert CLIB at 0x10000 and CSIB at 0x10100 + dd if=$(ROM_HEADER_BIN) of=$@ bs=1 seek=$$((0x10000)) conv=notrunc status=none + # Insert bootblock at 0x20000 + dd if=$(objcbfs)/bootblock.raw.bin of=$@ bs=1 seek=$$((0x20000)) conv=notrunc status=none + endif diff --git a/src/soc/cavium/common/rom_clib_s_nbl1fw.bin.hex b/src/soc/cavium/common/rom_clib_s_nbl1fw.bin.hex new file mode 100644 index 0000000..231c6a6 --- /dev/null +++ b/src/soc/cavium/common/rom_clib_s_nbl1fw.bin.hex @@ -0,0 +1,16 @@ +43 56 4d 5f 43 4c 49 42 00 00 00 00 00 00 00 00 +00 00 02 00 00 00 00 00 00 00 03 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/cavium/common/rom_csib_s_nbl1fw.bin.hex b/src/soc/cavium/common/rom_csib_s_nbl1fw.bin.hex new file mode 100644 index 0000000..f7a2021 --- /dev/null +++ b/src/soc/cavium/common/rom_csib_s_nbl1fw.bin.hex @@ -0,0 +1,16 @@ +43 56 4d 5f 43 53 49 42 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/23793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icd9cdf882ccdac591bec7240f1c7694fe0c0ad4d Gerrit-Change-Number: 23793 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: soc/cavium/bootblock: Get rid of register X1
by Patrick Rudolph (Code Review) 16 Feb '18

16 Feb '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/23792 Change subject: soc/cavium/bootblock: Get rid of register X1 ...................................................................... soc/cavium/bootblock: Get rid of register X1 The register X1 isn't used. Document it and remove it. Change-Id: I9324ea9de24ba4baaef9dde890c443dd0f921ad9 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/cavium/cn81xx/bootblock_custom.S M src/soc/cavium/common/bootblock.c M src/soc/cavium/common/include/soc/bootblock.h 3 files changed, 7 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/23792/1 diff --git a/src/soc/cavium/cn81xx/bootblock_custom.S b/src/soc/cavium/cn81xx/bootblock_custom.S index 69985b7..2f503c8 100644 --- a/src/soc/cavium/cn81xx/bootblock_custom.S +++ b/src/soc/cavium/cn81xx/bootblock_custom.S @@ -29,7 +29,11 @@ */ ic ialluis fmov d30, x0 /* Save X0 in FPR for use later */ - fmov d31, x1 /* Save X1 in FPR for use later */ + /** + * The BDK stores X1 for later use, but it turns out that we don't need + * this "feature". The idea is to hide the devicetree somewhere in + * flash, that only the ROM will find it and point to it using X1. + */ adr x1, _start /* x1 = _start location based on PC */ fmov d29, x1 /* Save PC in FPR for use later */ @@ -84,7 +88,7 @@ adr x0, _start /** - * Check if IROM has loaded the code to CONFIG_BOOTROM_OFFSET. + * Check if IROM has loaded the code to BOOTROM_OFFSET. * In case the offset is wrong, try to relocate. * Ideally the following code is never executed. * FIXME: Add region overlap check. @@ -248,8 +252,7 @@ bl arm64_init_cpu fmov x0, d30 /* The original X0, info from previous image */ - fmov x1, d31 /* The original X1, info from previous image */ - fmov x2, d29 /* The original PC we were loaded at */ + fmov x1, d29 /* The original PC we were loaded at */ /* Call C entry */ bl bootblock_main diff --git a/src/soc/cavium/common/bootblock.c b/src/soc/cavium/common/bootblock.c index c61a8d7..7b9d524 100644 --- a/src/soc/cavium/common/bootblock.c +++ b/src/soc/cavium/common/bootblock.c @@ -32,7 +32,6 @@ /* C code entry point for the boot block */ void bootblock_main(const uint64_t reg_x0, - const uint64_t reg_x1, const uint64_t reg_pc) { uint64_t base_timestamp = 0; @@ -57,8 +56,6 @@ printk(BIOS_ERR, "BOOTBLOCK: RST Boot Failure Code %lld\n", reg_x0); - - printk(BIOS_DEBUG, "BOOTBLOCK: FDT 0x%llX\n", reg_x1); } bootblock_soc_init(); diff --git a/src/soc/cavium/common/include/soc/bootblock.h b/src/soc/cavium/common/include/soc/bootblock.h index e347e86..bfb9745 100644 --- a/src/soc/cavium/common/include/soc/bootblock.h +++ b/src/soc/cavium/common/include/soc/bootblock.h @@ -14,7 +14,6 @@ void bootblock_mainboard_init(void); void bootblock_main(const uint64_t reg_x0, - const uint64_t reg_x1, const uint64_t reg_pc); -- To view, visit https://review.coreboot.org/23792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9324ea9de24ba4baaef9dde890c443dd0f921ad9 Gerrit-Change-Number: 23792 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: src/mainboard/ibase/mb899: Fix typo in comment
by build bot (Jenkins) (Code Review) 16 Feb '18

16 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23790 ) Change subject: src/mainboard/ibase/mb899: Fix typo in comment ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67580/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22098/ : SUCCESS -- To view, visit https://review.coreboot.org/23790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia79a42ed60e82a84b60f254a0895ec52c1fcda0b Gerrit-Change-Number: 23790 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Feb 2018 07:40:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/mainboard/ibase/mb899: Fix typo in comment
by Elyes HAOUAS (Code Review) 16 Feb '18

16 Feb '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23790 Change subject: src/mainboard/ibase/mb899: Fix typo in comment ...................................................................... src/mainboard/ibase/mb899: Fix typo in comment CR 24h Bit 0 is PNPCVS Change-Id: Ia79a42ed60e82a84b60f254a0895ec52c1fcda0b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/ibase/mb899/romstage.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/23790/1 diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 0d3b839..1b8bb95 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -66,7 +66,7 @@ dev = DUMMY_DEV; pnp_enter_conf_state(dev); - pnp_write_config(dev, 0x24, 0xc4); // PNPCSV + pnp_write_config(dev, 0x24, 0xc4); // PNPCVS pnp_write_config(dev, 0x29, 0x01); // GPIO settings pnp_write_config(dev, 0x2a, 0x40); // GPIO settings should be fc but gets set to 02 -- To view, visit https://review.coreboot.org/23790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia79a42ed60e82a84b60f254a0895ec52c1fcda0b Gerrit-Change-Number: 23790 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mb/google/{soraka, poppy, nautilus}: Set psys_pmax to 45W
by build bot (Jenkins) (Code Review) 16 Feb '18

16 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23757 ) Change subject: mb/google/{soraka,poppy,nautilus}: Set psys_pmax to 45W ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67579/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22097/ : SUCCESS -- To view, visit https://review.coreboot.org/23757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If6f624733830b462329b5f539c20e2aea664143e Gerrit-Change-Number: 23757 Gerrit-PatchSet: 9 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Feb 2018 07:15:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit February 2018