coreboot-gerrit February 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/cannonlake: Add missing GPIO pin definitions
by build bot (Jenkins) (Code Review) 15 Feb '18

15 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22482 ) Change subject: soc/intel/cannonlake: Add missing GPIO pin definitions ...................................................................... Patch Set 26: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67567/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22085/ : SUCCESS -- To view, visit https://review.coreboot.org/22482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I73b7803c73446660f5c25b1263e47bb50a955c56 Gerrit-Change-Number: 22482 Gerrit-PatchSet: 26 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Thu, 15 Feb 2018 23:23:54 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/fizz: Wait until display is ready
by build bot (Jenkins) (Code Review) 15 Feb '18

15 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23746 ) Change subject: mb/google/fizz: Wait until display is ready ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67569/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22087/ : SUCCESS -- To view, visit https://review.coreboot.org/23746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I90befe94f93e13904987acda50b2598d034b0031 Gerrit-Change-Number: 23746 Gerrit-PatchSet: 5 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Feb 2018 23:23:40 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: chromeec: Sync ec_commands.h for CBI tags
by build bot (Jenkins) (Code Review) 15 Feb '18

15 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23788 ) Change subject: chromeec: Sync ec_commands.h for CBI tags ...................................................................... Patch Set 1: No Builds Executed -- To view, visit https://review.coreboot.org/23788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I451ec9f6f9d7257915b7d4cb1e5adbee82d107de Gerrit-Change-Number: 23788 Gerrit-PatchSet: 1 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Feb 2018 23:15:40 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: chromeec: Sync ec_commands.h for CBI tags
by Daisuke Nojiri (Code Review) 15 Feb '18

15 Feb '18

Daisuke Nojiri has uploaded a new patch set (#2). ( https://review.coreboot.org/23788 ) Change subject: chromeec: Sync ec_commands.h for CBI tags ...................................................................... chromeec: Sync ec_commands.h for CBI tags This patch syncs ec_commands.h with the one in chromeec. BUG=b:70294260 BRANCH=none TEST=Verify SKU_ID and OEM_ID are correctly recognized on Fizz. Change-Id: I451ec9f6f9d7257915b7d4cb1e5adbee82d107de Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec_commands.h 2 files changed, 11 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/23788/2 -- To view, visit https://review.coreboot.org/23788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I451ec9f6f9d7257915b7d4cb1e5adbee82d107de Gerrit-Change-Number: 23788 Gerrit-PatchSet: 2 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org>

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Change in coreboot[master]: chromeec: Sync ec_commands.h for CBI tags
by Daisuke Nojiri (Code Review) 15 Feb '18

15 Feb '18

Daisuke Nojiri has uploaded this change for review. ( https://review.coreboot.org/23788 Change subject: chromeec: Sync ec_commands.h for CBI tags ...................................................................... chromeec: Sync ec_commands.h for CBI tags This patch syncs ec_commands.h with the one in chromeec. BUG=b:70294260 BRANCH=none TEST=Verify SKU_ID and OEM_ID are correctly recognized on Fizz. Change-Id: I451ec9f6f9d7257915b7d4cb1e5adbee82d107de Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec_commands.h 2 files changed, 11 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/23788/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index e8c50aa..a290f61 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -585,12 +585,12 @@ int google_chromeec_cbi_get_sku_id(uint32_t *id) { - return cbi_get_uint32(id, CBI_DATA_SKU_ID); + return cbi_get_uint32(id, CBI_TAG_SKU_ID); } int google_chromeec_cbi_get_oem_id(uint32_t *id) { - return cbi_get_uint32(id, CBI_DATA_OEM_ID); + return cbi_get_uint32(id, CBI_TAG_OEM_ID); } #ifndef __SMM__ diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index b333dde..cfd62e6 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -4383,14 +4383,11 @@ */ #define EC_CMD_SET_CROS_BOARD_INFO 0x0120 -enum cbi_data_type { - /* integer types */ - CBI_DATA_BOARD_VERSION = 0, - CBI_DATA_OEM_ID = 1, - CBI_DATA_SKU_ID = 2, - /* string types */ - CBI_FIRST_STRING_PARAM = 0x1000, - CBI_DATA_COUNT, +enum cbi_data_tag { + CBI_TAG_BOARD_VERSION = 0, + CBI_TAG_OEM_ID = 1, + CBI_TAG_SKU_ID = 2, + CBI_TAG_COUNT, }; /* @@ -4402,7 +4399,7 @@ #define CBI_GET_RELOAD (1 << 0) struct __ec_align4 ec_params_get_cbi { - uint32_t type; /* enum cbi_data_type */ + uint32_t type; /* enum cbi_data_tag */ uint32_t flag; /* CBI_GET_* */ }; @@ -4418,10 +4415,10 @@ #define CBI_SET_INIT (1 << 1) struct __ec_align1 ec_params_set_cbi { - uint32_t type; /* enum cbi_data_type */ + uint32_t tag; /* enum cbi_data_tag */ uint32_t flag; /* CBI_SET_* */ - uint32_t data; /* For numeric value */ - uint8_t raw[]; /* For string and raw data */ + uint32_t size; /* Data size */ + uint8_t data[]; /* For string and raw data */ }; /*****************************************************************************/ -- To view, visit https://review.coreboot.org/23788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I451ec9f6f9d7257915b7d4cb1e5adbee82d107de Gerrit-Change-Number: 23788 Gerrit-PatchSet: 1 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org>

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Change in coreboot[master]: Update chromeec submodule to upstream master
by build bot (Jenkins) (Code Review) 15 Feb '18

15 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23480 ) Change subject: Update chromeec submodule to upstream master ...................................................................... Patch Set 2: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/67565/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/22083/ : SUCCESS -- To view, visit https://review.coreboot.org/23480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3f7a1ceb1ea8c70d57a8f067023358b93df2670b Gerrit-Change-Number: 23480 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Feb 2018 22:01:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/mainboard/intel/glkrvp: Common code for ThunderPeak and Jefferson...
by Srinidhi N Kaushik (Code Review) 15 Feb '18

15 Feb '18

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/23787 Change subject: src/mainboard/intel/glkrvp: Common code for ThunderPeak and JeffersonPeak ...................................................................... src/mainboard/intel/glkrvp: Common code for ThunderPeak and JeffersonPeak This changeset will include common code for Thunderpeak and Jeffersonpeak based on auto detect. Change-Id: I875bb655b6ae87660b87a45fa52caf79f6e0d753 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> --- M src/mainboard/intel/glkrvp/mainboard.c M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c M src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h 4 files changed, 55 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/23787/1 diff --git a/src/mainboard/intel/glkrvp/mainboard.c b/src/mainboard/intel/glkrvp/mainboard.c index ac5e973..ab855e0 100644 --- a/src/mainboard/intel/glkrvp/mainboard.c +++ b/src/mainboard/intel/glkrvp/mainboard.c @@ -38,6 +38,12 @@ pads = variant_gpio_table(&num); gpio_configure_pads(pads, num); + /* Separate gpio table for cnvi bases wifi + * Will be adding one more table for pcie + * based wifi */ + pads = variant_cnvi_wifi_gpio_table(&num); + gpio_configure_pads(pads, num); + mainboard_ec_init(); } diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index 4b93947..5a83d47 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -9,13 +9,13 @@ register "pcie_rp1_clkreq_pin" = "3" # wifi/bt register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp4_clkreq_pin" = "1" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" # GPIO for PERST_0 # If the Board has PERST_0 signal, assign the GPIO # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF - register "prt0_gpio" = "GPIO_PRT0_UDEF" + register "prt0_gpio" = "GPIO_163" # GPIO for SD card detect register "sdcard_cd_gpio" = "GPIO_186" @@ -115,9 +115,9 @@ device pci 12.0 on end # - SATA device pci 13.0 off end # - PCIe-A 0 Slot 1 device pci 13.1 off end # - PCIe-A 1 - device pci 13.2 on end # - PCIe-A 2 Onboard Lan + device pci 13.2 off end # - PCIe-A 2 Onboard Lan device pci 13.3 off end # - PCIe-A 3 - device pci 14.0 off end # - PCIe-B 0 Slot2 + device pci 14.0 on end # - PCIe-B 0 Slot2 device pci 14.1 on end # - PCIe-B 1 Onboard M2 Slot(Wifi/BT) device pci 15.0 on end # - XHCI device pci 15.1 off end # - XDCI diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c index 9014aa5..974f183 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c @@ -22,6 +22,49 @@ * table found in EDS vol 1, but some pins aren't grouped functionally in * the table so those were moved for more logical grouping. */ + +static const struct pad_config cnvi_wifi_gpio_table[] = { + PAD_CFG_NF(GPIO_21, UP_20K, DEEP, NF2), /* CNV_MFUART2_RXD */ + PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), /*CNV_MFUART2_TXD */ + PAD_CFG_NF(GPIO_23, UP_20K, DEEP, NF2), /* CNV_GNSS_PABLANKIt */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_27, UP_20K, DEEP, NF2, TxLASTRxE, DISPUPD),/*RF_KILL_WiFi/WiFi_Disable */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_28, 1, DEEP, UP_20K, TxLASTRxE, DISPUPD),/* RF_KILL_BT/BT_Disable */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1),/*CNV_BRI_DT*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1),/*CNV_BRI_RSP*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1),/*CNV_RGI_DT*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_194, UP_20K, DEEP, NF1),/*CNV_RGI_RSP*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_195, NONE, DEEP, NF1),/*CNV_RF_RESET_B*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_196, NONE, DEEP, NF1),/*XTAL_CLKREQ*/ +}; + +const struct pad_config * __attribute__((weak)) +variant_cnvi_wifi_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(cnvi_wifi_gpio_table); + return cnvi_wifi_gpio_table; +} + +static const struct pad_config pcie_wifi_gpio_table[] = { + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_21, 1, DEEP, UP_20K, TxLASTRxE, ENPU),/*CNV_BRI_DT*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_22, 1, DEEP, UP_20K, TxDRxE, ENPU),/*CNV_BRI_DT*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_23, 1, DEEP, UP_20K, TxLASTRxE, ENPU),/*CNV_BRI_DT*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_27, 1, DEEP, NONE, IGNORE, DISPUPD),/*RF_KILL_WiFi/WiFi_Disable */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_28, 1, DEEP, UP_20K, TxLASTRxE, ENPU),/* RF_KILL_BT/BT_Disable */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_191, 1, DEEP, NONE, IGNORE, SAME),/*CNV_BRI_DT*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_192, 1, DEEP, UP_20K, IGNORE, ENPU ),/*CNV_BRI_RSP*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_193, 1, DEEP, NONE, IGNORE, SAME),/*CNV_RGI_DT*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_194, 1, DEEP, UP_20K, IGNORE, ENPU),/*CNV_RGI_RSP*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_195, 1, DEEP, NONE, IGNORE, SAME),/*CNV_RF_RESET_B*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_196, 1, DEEP, NONE, IGNORE, SAME),/*XTAL_CLKREQ*/ +}; + +const struct pad_config * __attribute__((weak)) +variant_pcie_wifi_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(pcie_wifi_gpio_table); + return pcie_wifi_gpio_table; +} + static const struct pad_config gpio_table[] = { /* NORTHWEST COMMUNITY GPIOS */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_0, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TCK */ @@ -45,14 +88,9 @@ PAD_CFG_GPI_APIC_IOS(GPIO_18, UP_20K, DEEP, LEVEL, NONE, IGNORE, SAME),/* Touch Pad Interrupt */ PAD_CFG_GPI_APIC_IOS(GPIO_19, UP_20K, DEEP, EDGE_SINGLE, NONE, TxDRxE, SAME),/*PMIC Interrupt*/ PAD_CFG_GPI_APIC_IOS(GPIO_20, UP_20K, DEEP, LEVEL, INVERT, IGNORE, SAME),/* Audio Codec Interrupt*/ - PAD_CFG_NF(GPIO_21, UP_20K, DEEP, NF2), /* CNV_MFUART2_RXD */ - PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), /* CNV_MFUART2_TXD */ - PAD_CFG_NF(GPIO_23, UP_20K, DEEP, NF2), /* CNV_GNSS_PABLANKIt */ PAD_CFG_GPO_GPIO_DRIVER(GPIO_24, 1, DEEP, DN_20K), PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_25, 1, DEEP, UP_20K, TxLASTRxE, SAME),/*WWAN /RF_KILL_GPS*/ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_26, UP_20K, DEEP, NF2, HIZCRx1, DISPUPD),/* NFC Interrupt */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_27, UP_20K, DEEP, NF2, TxLASTRxE, DISPUPD),/* RF_KILL_WiFi/WiFi_Disable */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_28, 1, DEEP, UP_20K, TxLASTRxE, DISPUPD),/* RF_KILL_BT/BT_Disable */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_29, 1, DEEP, UP_20K, HIZCRx0, DISPUPD),/* Codec Power Down: Ouput/ISH_GPIO_3*/ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_30, DN_20K, DEEP, NF1), /* ISH_GPIO_4 */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_31, DN_20K, DEEP, NF1), /* ISH_GPIO_5 */ @@ -229,12 +267,6 @@ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_210, 1, DEEP, UP_20K, HIZCRx0, DISPUPD), PAD_CFG_NF_IOSSTATE(GPIO_189, DN_20K, DEEP, NF1, HIZCRx0),/*OSC_CLK_OUT_0*/ PAD_CFG_NF_IOSSTATE(GPIO_190, DN_20K, DEEP, NF1, HIZCRx0),/*OSC_CLK_OUT_1*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1),/*CNV_BRI_DT*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1),/*CNV_BRI_RSP*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1),/*CNV_RGI_DT*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_194, UP_20K, DEEP, NF1),/*CNV_RGI_RSP*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_195, NONE, DEEP, NF1),/*CNV_RF_RESET_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_196, NONE, DEEP, NF1),/*XTAL_CLKREQ*/ PAD_CFG_NF(GPIO_197, DN_20K, DEEP, NF1),/*SDIO_CLK_FB*/ PAD_CFG_NF_IOSSTATE(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0),/*EMMC0_CLK*/ PAD_CFG_NF(GPIO_199, DN_20K, DEEP, NF1),/*EMMC0_CLK_FB*/ diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h index c278cde..62aa7a4 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h @@ -29,6 +29,8 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); const struct pad_config *variant_sleep_gpio_table(size_t *num); +const struct pad_config *variant_cnvi_wifi_gpio_table(size_t *num); +const struct pad_config *variant_pcie_wifi_gpio_table(size_t *num); /* Baseboard default swizzle. Can be reused if swizzle is same. */ extern const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle; -- To view, visit https://review.coreboot.org/23787 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I875bb655b6ae87660b87a45fa52caf79f6e0d753 Gerrit-Change-Number: 23787 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com>

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Change in coreboot[master]: soc/intel/common/block/gpio: Change group offset calculation
by build bot (Jenkins) (Code Review) 15 Feb '18

15 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22571 ) Change subject: soc/intel/common/block/gpio: Change group offset calculation ...................................................................... Patch Set 17: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67564/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22082/ : SUCCESS -- To view, visit https://review.coreboot.org/22571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I02ab1d878bc83d32222be074bd2db5e23adaf580 Gerrit-Change-Number: 22571 Gerrit-PatchSet: 17 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Thu, 15 Feb 2018 21:14:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/nvidia/tegra210: add missing bl31 params
by Julius Werner (Code Review) 15 Feb '18

15 Feb '18

Julius Werner has posted comments on this change. ( https://review.coreboot.org/23783 ) Change subject: soc/nvidia/tegra210: add missing bl31 params ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/23783/1/src/soc/nvidia/tegra210/arm_tf.c File src/soc/nvidia/tegra210/arm_tf.c: https://review.coreboot.org/#/c/23783/1/src/soc/nvidia/tegra210/arm_tf.c@45 PS1, Line 45: t210_plat_params.uart_id = 1; Shouldn't this depend on the CONSOLE_SERIAL_TEGRA210_UARTx Kconfigs? -- To view, visit https://review.coreboot.org/23783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7a47647216a154894e6c2c1fd3b304e18e85c6a5 Gerrit-Change-Number: 23783 Gerrit-PatchSet: 1 Gerrit-Owner: Andre Heider <a.heider(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Feb 2018 21:10:51 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/cannonlake: Add missing GPIO pin definitions
by build bot (Jenkins) (Code Review) 15 Feb '18

15 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22482 ) Change subject: soc/intel/cannonlake: Add missing GPIO pin definitions ...................................................................... Patch Set 25: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67563/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22081/ : SUCCESS -- To view, visit https://review.coreboot.org/22482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I73b7803c73446660f5c25b1263e47bb50a955c56 Gerrit-Change-Number: 22482 Gerrit-PatchSet: 25 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Thu, 15 Feb 2018 21:06:36 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit February 2018