coreboot-gerrit February 2018

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Change in coreboot[master]: sb/broadcom/bcm5785/early_setup.c: Fix coding style
by Elyes HAOUAS (Code Review) 03 Feb '18

03 Feb '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/23577 to look at the new patch set (#2). Change subject: sb/broadcom/bcm5785/early_setup.c: Fix coding style ...................................................................... sb/broadcom/bcm5785/early_setup.c: Fix coding style Change-Id: Ic8218078f4b1075b41f769e26e34adf9c9b113ac Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/broadcom/bcm5785/early_setup.c 1 file changed, 23 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/23577/2 -- To view, visit https://review.coreboot.org/23577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic8218078f4b1075b41f769e26e34adf9c9b113ac Gerrit-Change-Number: 23577 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/broadcom/bcm5785/early_setup.c: Fix coding style
by build bot (Jenkins) (Code Review) 03 Feb '18

03 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23577 ) Change subject: sb/broadcom/bcm5785/early_setup.c: Fix coding style ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66992/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21566/ : SUCCESS -- To view, visit https://review.coreboot.org/23577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic8218078f4b1075b41f769e26e34adf9c9b113ac Gerrit-Change-Number: 23577 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Feb 2018 23:09:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: sb/broadcom/bcm5785/early_setup.c: Fix coding style
by Elyes HAOUAS (Code Review) 03 Feb '18

03 Feb '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23577 Change subject: sb/broadcom/bcm5785/early_setup.c: Fix coding style ...................................................................... sb/broadcom/bcm5785/early_setup.c: Fix coding style Change-Id: Ic8218078f4b1075b41f769e26e34adf9c9b113ac Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/broadcom/bcm5785/early_setup.c 1 file changed, 22 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/23577/1 diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index 7235444..2c79239 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -27,13 +27,13 @@ /* LPC Control 0 */ byte = pci_read_config8(dev, 0x44); /* Serial 0 */ - byte |= (1<<6); + byte |= (1 << 6); pci_write_config8(dev, 0x44, byte); /* LPC Control 4 */ byte = pci_read_config8(dev, 0x48); /* superio port 0x2e/4e enable */ - byte |=(1<<1)|(1<<0); + byte |= (1 << 1)|(1 << 0); pci_write_config8(dev, 0x48, byte); } @@ -46,21 +46,19 @@ dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); dword_old = pci_read_config32(dev, 0x4c); - dword = dword_old | (1<<4); //enable Timer Func - if (dword != dword_old ) { + dword = dword_old | (1 << 4); //enable Timer Func + if (dword != dword_old) pci_write_config32(dev, 0x4c, dword); - } dword_old = pci_read_config32(dev, 0x6c); - dword = dword_old | (1<<9); //unhide Timer Func in pci space - if (dword != dword_old ) { + dword = dword_old | (1 << 9); //unhide Timer Func in pci space + if (dword != dword_old) pci_write_config32(dev, 0x6c, dword); - } dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0); /* enable cf9 */ - pci_write_config8(dev, 0x40, (1<<2)); + pci_write_config8(dev, 0x40, (1 << 2)); } unsigned get_sbdn(unsigned bus) @@ -74,7 +72,7 @@ PCI_ID(0x1166, 0x0036), bus); - return (dev>>15) & 0x1f; + return (dev >> 15) & 0x1f; } @@ -84,7 +82,7 @@ { //ACPI Decode Enable outb(0x0e, 0xcd6); - outb((1<<3), 0xcd7); + outb((1 << 3), 0xcd7); // set port to 0x2060 outb(0x67, 0xcd6); @@ -138,7 +136,7 @@ dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); byte = pci_read_config8(dev, 0x42); - byte = (1<<1); //enable a20 + byte = (1 << 1); //enable a20 pci_write_config8(dev, 0x42, byte); dword_old = pci_read_config32(dev, 0x6c); @@ -148,10 +146,12 @@ // bit 2: enable keyboard init message // bit 1: enable upsteam messages // bit 0: enable shutdowm message to init generation - dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor - if (dword != dword_old ) { + + /* bit 1 and bit 4 must be set, otherwise + * interrupt msg will not be delivered to the processor */ + dword = dword_old|(1 << 5)|(1 << 3)|(1 << 2)|(1 << 1)|(1 << 0); + if (dword != dword_old) pci_write_config32(dev, 0x6c, dword); - } } static void bcm5785_early_setup(void) @@ -164,13 +164,13 @@ // enable device on bcm5785 at first dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); dword = pci_read_config32(dev, 0x64); - dword |= (1<<15) | (1<<11) | (1<<3); // ioapci enable - dword |= (1<<8); // USB enable - dword |= /* (1<<27)|*/(1<<14); // IDE enable + dword |= (1 << 15) | (1 << 11) | (1 << 3); // ioapci enable + dword |= (1 << 8); // USB enable + dword |= /* (1 << 27)|*/(1 << 14); // IDE enable pci_write_config32(dev, 0x64, dword); byte = pci_read_config8(dev, 0x84); - byte |= (1<<0); // SATA enable + byte |= (1 << 0); // SATA enable pci_write_config8(dev, 0x84, byte); // WDT and cf9 for later in ramstage to call hard_reset @@ -182,7 +182,7 @@ // IDE related //F0 byte = pci_read_config8(dev, 0x4e); - byte |= (1<<4); //enable IDE ext regs + byte |= (1 << 4); //enable IDE ext regs pci_write_config8(dev, 0x4e, byte); //F1 @@ -193,7 +193,7 @@ pci_write_config8(dev, 0xb0, 0x01); pci_write_config8(dev, 0xb2, 0x02); byte = pci_read_config8(dev, 0x06); - byte |= (1<<4); // so b0, b2 can not be changed from now + byte |= (1 << 4); // so b0, b2 can not be changed from now pci_write_config8(dev, 0x06, byte); byte = pci_read_config8(dev, 0x49); byte |= 1; // enable second channel @@ -203,7 +203,7 @@ dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); byte = pci_read_config8(dev, 0x40); - byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable + byte |= (1 << 3)|(1 << 2); // LPC Retry, LPC to PCI DMA enable pci_write_config8(dev, 0x40, byte); pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end -- To view, visit https://review.coreboot.org/23577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic8218078f4b1075b41f769e26e34adf9c9b113ac Gerrit-Change-Number: 23577 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: soc/amd/stoneyridge/acpi/sleepstates.asl: Fix guarded code
by build bot (Jenkins) (Code Review) 02 Feb '18

02 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23575 ) Change subject: soc/amd/stoneyridge/acpi/sleepstates.asl: Fix guarded code ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66991/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21565/ : SUCCESS -- To view, visit https://review.coreboot.org/23575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I268b228706a625e1415c4f24e808261c279ba41e Gerrit-Change-Number: 23575 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Feb 2018 22:39:48 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/skylake: Set PsysPl3 and Pl4
by build bot (Jenkins) (Code Review) 02 Feb '18

02 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23527 ) Change subject: soc/intel/skylake: Set PsysPl3 and Pl4 ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66987/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21561/ : SUCCESS -- To view, visit https://review.coreboot.org/23527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idbe04f48079b4fa3302d21acd065f2e4c53dd1ed Gerrit-Change-Number: 23527 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Feb 2018 22:34:24 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: google/fizz: Set Pmax value based on SKU id
by build bot (Jenkins) (Code Review) 02 Feb '18

02 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23576 ) Change subject: google/fizz: Set Pmax value based on SKU id ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66990/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21564/ : SUCCESS -- To view, visit https://review.coreboot.org/23576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I47aa7f363781ae877e29bcebf9fae4d59b98027f Gerrit-Change-Number: 23576 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Feb 2018 22:33:54 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: google/fizz: Determine PsysPl3 and Pl4 values
by build bot (Jenkins) (Code Review) 02 Feb '18

02 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23528 ) Change subject: google/fizz: Determine PsysPl3 and Pl4 values ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66988/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21562/ : SUCCESS -- To view, visit https://review.coreboot.org/23528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I06a4c5bc25f6ec036b79f6941f80e26058d64930 Gerrit-Change-Number: 23528 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Feb 2018 22:33:48 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/skylake: Set PsysPmax value
by build bot (Jenkins) (Code Review) 02 Feb '18

02 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23268 ) Change subject: soc/intel/skylake: Set PsysPmax value ...................................................................... Patch Set 10: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66989/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21563/ : SUCCESS -- To view, visit https://review.coreboot.org/23268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I44f2e2917a8eb9ce3bb69d9c15899d4c7c5b2883 Gerrit-Change-Number: 23268 Gerrit-PatchSet: 10 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rajneesh Bhardwaj <rajneesh.bhardwaj(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Rushikesh S Kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Feb 2018 22:33:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: google/fizz: Set Pmax value based on SKU id
by build bot (Jenkins) (Code Review) 02 Feb '18

02 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23576 ) Change subject: google/fizz: Set Pmax value based on SKU id ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/66984/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/21558/ : SUCCESS -- To view, visit https://review.coreboot.org/23576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I47aa7f363781ae877e29bcebf9fae4d59b98027f Gerrit-Change-Number: 23576 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Feb 2018 22:25:27 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge/acpi/sb_pci0_fch.asl: Fix instability
by build bot (Jenkins) (Code Review) 02 Feb '18

02 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23573 ) Change subject: soc/amd/stoneyridge/acpi/sb_pci0_fch.asl: Fix instability ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66986/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21560/ : SUCCESS -- To view, visit https://review.coreboot.org/23573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If6c877df5a87df1b348de92868b91eed4a76de55 Gerrit-Change-Number: 23573 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Feb 2018 22:25:25 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit February 2018