coreboot-gerrit February 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mainboard/winent: Remove unnecessary braces {}
by build bot (Jenkins) (Code Review) 03 Feb '18

03 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23524 ) Change subject: mainboard/winent: Remove unnecessary braces {} ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67005/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21579/ : SUCCESS -- To view, visit https://review.coreboot.org/23524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I48a7bd4bd98d1a9d7b0ce4c12e09284fa4be6c7a Gerrit-Change-Number: 23524 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Feb 2018 09:08:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Add basic CPU PM entry of FSP
by Furquan Shaikh (Code Review) 03 Feb '18

03 Feb '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/23580 ) Change subject: soc/intel/cannonlake: Add basic CPU PM entry of FSP ...................................................................... Patch Set 3: (5 comments) https://review.coreboot.org/#/c/23580/3/src/soc/intel/cannonlake/chip.h File src/soc/intel/cannonlake/chip.h: https://review.coreboot.org/#/c/23580/3/src/soc/intel/cannonlake/chip.h@89 PS3, Line 89: power limit What is the unit? https://review.coreboot.org/#/c/23580/3/src/soc/intel/cannonlake/chip.h@89 PS3, Line 89: Package PL1 - Package long duration turbo mode power limit : * Package PL2 - Short Duration Turbo Mode : * Package PL1 - Package short duration turbo mode power limit */ These comments don't seem to match the fields below. https://review.coreboot.org/#/c/23580/3/src/soc/intel/cannonlake/chip.h@92 PS3, Line 92: uint32_t PPL1Power; : uint8_t PPL2_enable; : uint32_t PPL2Power; I know this file is not very consistent about the naming, but it would be better to use: uint32_t package_pl1; uint8_t package_pl2_enable; uint32_t package_pl2; Also, would it be safe to assume that package_pl2_enable should be set to 1 if package_pl2 is provided? i.e. do we need to accept a separate package_pl2_enable from mainboard? https://review.coreboot.org/#/c/23580/3/src/soc/intel/cannonlake/chip.c File src/soc/intel/cannonlake/chip.c: https://review.coreboot.org/#/c/23580/3/src/soc/intel/cannonlake/chip.c@183 PS3, Line 183: params_t Can we name this tparams or test_params? params_t looks like a typedef. https://review.coreboot.org/#/c/23580/3/src/soc/intel/cannonlake/chip.c@273 PS3, Line 273: Powermanagement space after power? -- To view, visit https://review.coreboot.org/23580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I81bd04f5de05543ad00ce2562839a51a5c0ae047 Gerrit-Change-Number: 23580 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Feb 2018 05:50:57 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/cannonlake: Add basic CPU PM entry of FSP
by build bot (Jenkins) (Code Review) 03 Feb '18

03 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23580 ) Change subject: soc/intel/cannonlake: Add basic CPU PM entry of FSP ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67003/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21577/ : SUCCESS -- To view, visit https://review.coreboot.org/23580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I81bd04f5de05543ad00ce2562839a51a5c0ae047 Gerrit-Change-Number: 23580 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Feb 2018 04:17:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/google/meowth: Limit Package PL2 to 11.625W
by build bot (Jenkins) (Code Review) 03 Feb '18

03 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23581 ) Change subject: mainboard/google/meowth: Limit Package PL2 to 11.625W ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67004/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21578/ : SUCCESS -- To view, visit https://review.coreboot.org/23581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3aa16ba17f38f71bc5cb2e4cc7a226931e1503b2 Gerrit-Change-Number: 23581 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Feb 2018 04:12:54 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/google/meowth: Limit Package PL2 to 11.625W
by build bot (Jenkins) (Code Review) 03 Feb '18

03 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23581 ) Change subject: mainboard/google/meowth: Limit Package PL2 to 11.625W ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67002/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/21576/ : SUCCESS -- To view, visit https://review.coreboot.org/23581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3aa16ba17f38f71bc5cb2e4cc7a226931e1503b2 Gerrit-Change-Number: 23581 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Feb 2018 04:06:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Add basic CPU PM entry of FSP
by build bot (Jenkins) (Code Review) 03 Feb '18

03 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23580 ) Change subject: soc/intel/cannonlake: Add basic CPU PM entry of FSP ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67001/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/21575/ : SUCCESS -- To view, visit https://review.coreboot.org/23580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I81bd04f5de05543ad00ce2562839a51a5c0ae047 Gerrit-Change-Number: 23580 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Feb 2018 04:05:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Add basic CPU PM entry of FSP
by Lijian Zhao (Code Review) 03 Feb '18

03 Feb '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/23580 to look at the new patch set (#3). Change subject: soc/intel/cannonlake: Add basic CPU PM entry of FSP ...................................................................... soc/intel/cannonlake: Add basic CPU PM entry of FSP Enable coreboot's ability of update basic CPU power management about package power limit 1 and package power limit 2. BUG=b.72574971 TEST=Build and flash to meowth platform, able to boot up fine into OS. Update PPL1 in coreboot, and combine with debug build FSP can see desired value got printed. Change-Id: I81bd04f5de05543ad00ce2562839a51a5c0ae047 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/chip.h 2 files changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/23580/3 -- To view, visit https://review.coreboot.org/23580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I81bd04f5de05543ad00ce2562839a51a5c0ae047 Gerrit-Change-Number: 23580 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mainboard/google/meowth: Limit Package PL2 to 11.625W
by build bot (Jenkins) (Code Review) 03 Feb '18

03 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23581 ) Change subject: mainboard/google/meowth: Limit Package PL2 to 11.625W ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67000/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/21574/ : ABORTED -- To view, visit https://review.coreboot.org/23581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3aa16ba17f38f71bc5cb2e4cc7a226931e1503b2 Gerrit-Change-Number: 23581 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Feb 2018 04:03:41 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Add basic CPU PM entry of FSP
by build bot (Jenkins) (Code Review) 03 Feb '18

03 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23580 ) Change subject: soc/intel/cannonlake: Add basic CPU PM entry of FSP ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/66999/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/21573/ : SUCCESS -- To view, visit https://review.coreboot.org/23580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I81bd04f5de05543ad00ce2562839a51a5c0ae047 Gerrit-Change-Number: 23580 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Feb 2018 04:03:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Add basic CPU PM entry of FSP
by Lijian Zhao (Code Review) 03 Feb '18

03 Feb '18

Lijian Zhao has uploaded a new patch set (#2). ( https://review.coreboot.org/23580 ) Change subject: soc/intel/cannonlake: Add basic CPU PM entry of FSP ...................................................................... soc/intel/cannonlake: Add basic CPU PM entry of FSP Enable coreboot's ability of update basic CPU power management about package power limit 1 and package power limit 2. BUG=b.72574971 TEST=Build and flash to meowth platform, able to boot up fine into OS. Update PPL1 in coreboot, and combine with debug build FSP can see desired value got printed. Change-Id: I81bd04f5de05543ad00ce2562839a51a5c0ae047 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/chip.h 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/23580/2 -- To view, visit https://review.coreboot.org/23580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I81bd04f5de05543ad00ce2562839a51a5c0ae047 Gerrit-Change-Number: 23580 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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coreboot-gerrit February 2018