coreboot-gerrit February 2018

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Change in coreboot[master]: mainboard/google/meowth: Limit Package PL2 to 11.625W
by Lijian Zhao (Code Review) 03 Feb '18

03 Feb '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/23581 Change subject: mainboard/google/meowth: Limit Package PL2 to 11.625W ...................................................................... mainboard/google/meowth: Limit Package PL2 to 11.625W Meowth system's CPU heat sink have a designed limitation of 11.7W, hence limit package PL2 (short turbo limit) to 11.625W( 93 * 125 MilliWatts). BUG=b.72574971 TEST=Flash and boot up with meowth platform, check value with debug build FSP. Change-Id: I3aa16ba17f38f71bc5cb2e4cc7a226931e1503b2 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/google/zoombini/variants/meowth/devicetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/23581/1 diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb index 88de878..ef434cb 100644 --- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb @@ -32,6 +32,11 @@ register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "1" + # CPU Basic Management # + register "PPL1Power" = "0x38" # 7W + register "PPL2_enable" = "1" # Package PL2 enabled + register "PPL2Power" = "0x5D" # 11.625W for Package PL2 + # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM # communication before memory is up. register "gspi[0]" = "{ -- To view, visit https://review.coreboot.org/23581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3aa16ba17f38f71bc5cb2e4cc7a226931e1503b2 Gerrit-Change-Number: 23581 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Add basic CPU PM entry of FSP
by Lijian Zhao (Code Review) 03 Feb '18

03 Feb '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/23580 Change subject: soc/intel/cannonlake: Add basic CPU PM entry of FSP ...................................................................... soc/intel/cannonlake: Add basic CPU PM entry of FSP Enable coreboot's ability of update basic CPU power management about package power limit 1 and package power limit 2. BUG=b.72574971 TEST=Build and flash to meowth platform, able to boot up fine into OS. Update PPL1 in coreboot, and combine with debug build FSP can see desired value got printed. Change-Id: I81bd04f5de05543ad00ce2562839a51a5c0ae047 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/chip.h 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/23580/1 diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index f05b55a..e2d4a82 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -180,6 +180,7 @@ { int i; FSP_S_CONFIG *params = &supd->FspsConfig; + FSP_S_TEST_CONFIG *params_t = &supd->FspsTestConfig; const struct device *dev = SA_DEV_ROOT; config_t *config = dev->chip_info; @@ -269,6 +270,11 @@ params->Device4Enable = config->Device4Enable; params->SkipMpInit = config->FspSkipMpInit; + /* Cpu Basic Powermanagement */ + params_t->PowerLimit1 = config->PPL1Power; + params_t->PowerLimit2 = config->PPL2_enable; + params_t->PowerLimit2Power = config->PPL2Power; + /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */ diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index a42494c..64de442 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -85,6 +85,14 @@ /* TCC activation offset */ uint32_t tcc_offset; + /* CPU Basic Power Management + * Package PL1 - Package long duration turbo mode power limit + * Package PL2 - Short Duration Turbo Mode + * Package PL1 - Package short duration turbo mode power limit */ + uint32_t PPL1Power; + uint32_t PPL2_enable; + uint32_t PPL2Power; + uint64_t PlatformMemorySize; uint8_t SmramMask; uint8_t MrcFastBoot; -- To view, visit https://review.coreboot.org/23580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I81bd04f5de05543ad00ce2562839a51a5c0ae047 Gerrit-Change-Number: 23580 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: southbridge/amd/cimx/sb900: Fix coding style
by build bot (Jenkins) (Code Review) 03 Feb '18

03 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23579 ) Change subject: southbridge/amd/cimx/sb900: Fix coding style ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66996/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21570/ : SUCCESS -- To view, visit https://review.coreboot.org/23579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5448004da37db02ba3ae5ac2677bfcf45b12418d Gerrit-Change-Number: 23579 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Feb 2018 00:30:32 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/apollolake: Clear RTC failure bit after reading it
by build bot (Jenkins) (Code Review) 03 Feb '18

03 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23578 ) Change subject: soc/intel/apollolake: Clear RTC failure bit after reading it ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66998/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21572/ : SUCCESS -- To view, visit https://review.coreboot.org/23578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib23b1fcd5c3624bad6ab83dce17a469b2f5b5ba8 Gerrit-Change-Number: 23578 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Feb 2018 00:25:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/apollolake: Clear RTC failure bit after reading it
by build bot (Jenkins) (Code Review) 03 Feb '18

03 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23578 ) Change subject: soc/intel/apollolake: Clear RTC failure bit after reading it ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/66994/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/21568/ : SUCCESS -- To view, visit https://review.coreboot.org/23578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib23b1fcd5c3624bad6ab83dce17a469b2f5b5ba8 Gerrit-Change-Number: 23578 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Feb 2018 00:11:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: southbridge/amd/cimx/sb900: Fix coding style
by build bot (Jenkins) (Code Review) 03 Feb '18

03 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23579 ) Change subject: southbridge/amd/cimx/sb900: Fix coding style ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/66995/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/21569/ : SUCCESS -- To view, visit https://review.coreboot.org/23579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5448004da37db02ba3ae5ac2677bfcf45b12418d Gerrit-Change-Number: 23579 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Feb 2018 00:10:24 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: southbridge/amd/cimx/sb900: Fix coding style
by Elyes HAOUAS (Code Review) 03 Feb '18

03 Feb '18

Elyes HAOUAS has uploaded a new patch set (#2). ( https://review.coreboot.org/23579 ) Change subject: southbridge/amd/cimx/sb900: Fix coding style ...................................................................... southbridge/amd/cimx/sb900: Fix coding style Change-Id: I5448004da37db02ba3ae5ac2677bfcf45b12418d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/cimx/sb900/smbus_spd.c 1 file changed, 73 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/23579/2 -- To view, visit https://review.coreboot.org/23579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I5448004da37db02ba3ae5ac2677bfcf45b12418d Gerrit-Change-Number: 23579 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: southbridge/amd/cimx/sb900: Fix coding style
by Elyes HAOUAS (Code Review) 03 Feb '18

03 Feb '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23579 Change subject: southbridge/amd/cimx/sb900: Fix coding style ...................................................................... southbridge/amd/cimx/sb900: Fix coding style Change-Id: I5448004da37db02ba3ae5ac2677bfcf45b12418d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/cimx/sb900/smbus_spd.c 1 file changed, 73 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/23579/1 diff --git a/src/southbridge/amd/cimx/sb900/smbus_spd.c b/src/southbridge/amd/cimx/sb900/smbus_spd.c index 3fd4439..2f766e3 100644 --- a/src/southbridge/amd/cimx/sb900/smbus_spd.c +++ b/src/southbridge/amd/cimx/sb900/smbus_spd.c @@ -35,29 +35,20 @@ #define SMBUS_BASE_ADDR 0xB00 -STATIC -VOID -WritePmReg ( - IN UINT8 Reg, - IN UINT8 Data - ) +static void WritePmReg(int Reg, int Data) { - __outbyte (0xCD6, Reg); - __outbyte (0xCD7, Data); + __outbyte(0xCD6, Reg); + __outbyte(0xCD7, Data); } -STATIC -VOID -SetupFch ( - IN UINT16 - IN IoBase - ) + +static void SetupFch(int IoBase) { - WritePmReg (0x2D, IoBase >> 8); - WritePmReg (0x2C, IoBase | 1); - WritePmReg (0x29, 0x80); - WritePmReg (0x28, 0x61); - /* set SMBus clock to 400 KHz */ - __outbyte (IoBase + 0x0E, 66000000 / 400000 / 4); + WritePmReg(0x2D, IoBase >> 8); + WritePmReg(0x2C, IoBase | 1); + WritePmReg(0x29, 0x80); + WritePmReg(0x28, 0x61); + /* set SMBus clock to 400 KHz */ + __outbyte(IoBase + 0x0E, 66000000 / 400000 / 4); } /* @@ -66,40 +57,37 @@ * */ -STATIC -AGESA_STATUS -ReadSmbusByteData ( - IN UINT16 Iobase, - IN UINT8 Address, - OUT UINT8 *Buffer, - IN UINTN Offset - ) +static int ReadSmbusByteData(int Iobase, int Address, char *Buffer, int Offset) { - UINTN Status; - UINT64 Limit; + unsigned int Status; + UINT64 Limit; - Address |= 1; // set read bit + Address |= 1; // set read bit - __outbyte (Iobase + 0, 0xFF); // clear error status - __outbyte (Iobase + 1, 0x1F); // clear error status - __outbyte (Iobase + 3, Offset); // offset in eeprom - __outbyte (Iobase + 4, Address); // slave address and read bit - __outbyte (Iobase + 2, 0x48); // read byte command + __outbyte(Iobase + 0, 0xFF); // clear error status + __outbyte(Iobase + 1, 0x1F); // clear error status + __outbyte(Iobase + 3, Offset); // offset in eeprom + __outbyte(Iobase + 4, Address); // slave address and read bit + __outbyte(Iobase + 2, 0x48); // read byte command - /* time limit to avoid hanging for unexpected error status (should never happen) */ - Limit = __rdtsc () + 2000000000 / 10; - for (;;) { - Status = __inbyte (Iobase); - if (__rdtsc () > Limit) break; - if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((Status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } + /* time limit to avoid hanging for unexpected error status (should never happen) */ + Limit = __rdtsc() + 2000000000 / 10; + for (;;) { + Status = __inbyte(Iobase); + if (__rdtsc() > Limit) + break; + if ((Status & 2) == 0) + continue; // SMBusInterrupt not set, keep waiting + if ((Status & 1) == 1) + continue; // HostBusy set, keep waiting + break; + } - Buffer [0] = __inbyte (Iobase + 5); - if (Status == 2) Status = 0; // check for done with no errors - return Status; - } + Buffer [0] = __inbyte(Iobase + 5); + if (Status == 2) + Status = 0; // check for done with no errors + return Status; +} /* * @@ -108,33 +96,31 @@ * */ -STATIC -AGESA_STATUS -ReadSmbusByte ( - IN UINT16 Iobase, - IN UINT8 Address, - OUT UINT8 *Buffer - ) +static int ReadSmbusByte(int Iobase, int Address, char *Buffer) { - UINTN Status; - UINT64 Limit; + unsigned int Status; + UINT64 Limit; - __outbyte (Iobase + 0, 0xFF); // clear error status - __outbyte (Iobase + 2, 0x44); // read command + __outbyte(Iobase + 0, 0xFF); // clear error status + __outbyte(Iobase + 2, 0x44); // read command - // time limit to avoid hanging for unexpected error status - Limit = __rdtsc () + 2000000000 / 10; - for (;;) { - Status = __inbyte (Iobase); - if (__rdtsc () > Limit) break; - if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((Status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } + // time limit to avoid hanging for unexpected error status + Limit = __rdtsc() + 2000000000 / 10; + for (;;) { + Status = __inbyte(Iobase); + if (__rdtsc() > Limit) + break; + if ((Status & 2) == 0) + continue; // SMBusInterrupt not set, keep waiting + if ((Status & 1) == 1) + continue; // HostBusy set, keep waiting + break; + } - Buffer [0] = __inbyte (Iobase + 5); - if (Status == 2) Status = 0; // check for done with no errors - return Status; + Buffer [0] = __inbyte(Iobase + 5); + if (Status == 2) + Status = 0; // check for done with no errors + return Status; } /* @@ -147,31 +133,26 @@ * */ -STATIC -AGESA_STATUS -ReadSpd ( - IN UINT16 IoBase, - IN UINT8 SmbusSlaveAddress, - OUT UINT8 *Buffer, - IN UINTN Count - ) +static int ReadSpd(int IoBase, int SmbusSlaveAddress, char *Buffer, int Count) { - UINTN Index, Status; + int Index, Status; - /* read the first byte using offset zero */ - Status = ReadSmbusByteData (IoBase, SmbusSlaveAddress, Buffer, 0); - if (Status) return Status; + /* read the first byte using offset zero */ + Status = ReadSmbusByteData(IoBase, SmbusSlaveAddress, Buffer, 0); + if (Status) + return Status; - /* read the remaining bytes using auto-increment for speed */ - for (Index = 1; Index < Count; Index++){ - Status = ReadSmbusByte (IoBase, SmbusSlaveAddress, &Buffer [Index]); - if (Status) return Status; - } - return 0; + /* read the remaining bytes using auto-increment for speed */ + for (Index = 1; Index < Count; Index++){ + Status = ReadSmbusByte(IoBase, SmbusSlaveAddress, &Buffer [Index]); + if (Status) + return Status; + } + return 0; } int smbus_readSpd(int spdAddress, char *buf, size_t len) { - SetupFch (SMBUS_BASE_ADDR); - return ReadSpd (SMBUS_BASE_ADDR, spdAddress, (UINT8 *) buf, len); + SetupFch(SMBUS_BASE_ADDR); + return ReadSpd(SMBUS_BASE_ADDR, spdAddress, buf, len); } -- To view, visit https://review.coreboot.org/23579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5448004da37db02ba3ae5ac2677bfcf45b12418d Gerrit-Change-Number: 23579 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: soc/intel/apollolake: Clear RTC failure bit after reading it
by Furquan Shaikh (Code Review) 03 Feb '18

03 Feb '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/23578 Change subject: soc/intel/apollolake: Clear RTC failure bit after reading it ...................................................................... soc/intel/apollolake: Clear RTC failure bit after reading it This change ensures that the RTC failure bit is cleared in PMCON1 after cmos_init checks for it. Before this change, RPS was cleared in dev init phase. If any reboot occurred before dev init stage (e.g. FSP reset) then RPS won't be cleared and cmos_init will re-initialize CMOS data. This resulted in any information like VBNV flags stored in CMOS after first cmos_init to be lost. BUG=b:72879807 BRANCH=coral TEST=Verified that recovery request is preserved when recovery is requested without battery on coral. Change-Id: Ib23b1fcd5c3624bad6ab83dce17a469b2f5b5ba8 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c 2 files changed, 21 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/23578/1 diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 34b9f96..0ab53af 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -173,8 +173,13 @@ #define COLD_BOOT_STS (1 << 27) #define COLD_RESET_STS (1 << 26) #define WARM_RESET_STS (1 << 25) +#define GLOBAL_RESET_STS (1 << 24) #define SRS (1 << 20) +#define MS4V (1 << 18) #define RPS (1 << 2) +#define GEN_PMCON1_CLR1_BITS (COLD_BOOT_STS | COLD_RESET_STS | \ + WARM_RESET_STS | GLOBAL_RESET_STS |\ + SRS | MS4V) #define GEN_PMCON2 0x1024 #define GEN_PMCON3 0x1028 # define SLP_S3_ASSERT_WIDTH_SHIFT 10 diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index dbaed70..2900e6d 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -232,5 +232,20 @@ int vbnv_cmos_failed(void) { - return rtc_failed(read32((void *)(read_pmc_mmio_bar() + GEN_PMCON1))); + uintptr_t pmc_bar = read_pmc_mmio_bar(); + uint32_t gen_pmcon1 = read32((void *)(pmc_bar + GEN_PMCON1)); + int rtc_failure = rtc_failed(gen_pmcon1); + + /* We do not want to write 1 to clear-1 bits. So set them to 0. */ + gen_pmcon &= ~GEN_PMCON1_CLR1_BITS; + + /* RPS is write 0 to clear. */ + gen_pmcon &= ~RPS; + + if (rtc_failure) { + printk(BIOS_INFO, "RTC failed!\n"); + write32((void *)(pmc_bar + GEN_PMCON1), gen_pmcon1); + } + + return rtc_failure; } -- To view, visit https://review.coreboot.org/23578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib23b1fcd5c3624bad6ab83dce17a469b2f5b5ba8 Gerrit-Change-Number: 23578 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: sb/broadcom/bcm5785/early_setup.c: Fix coding style
by build bot (Jenkins) (Code Review) 03 Feb '18

03 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23577 ) Change subject: sb/broadcom/bcm5785/early_setup.c: Fix coding style ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66993/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21567/ : SUCCESS -- To view, visit https://review.coreboot.org/23577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic8218078f4b1075b41f769e26e34adf9c9b113ac Gerrit-Change-Number: 23577 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Feb 2018 23:14:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit February 2018