coreboot-gerrit December 2018

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Change in ...coreboot[master]: sb/intel/lynxpoint/acpi/serialio.asl: [test] support FixedDMA
by HAOUAS Elyes (Code Review) 10 Dec '18

10 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30130 Change subject: sb/intel/lynxpoint/acpi/serialio.asl: [test] support FixedDMA ...................................................................... sb/intel/lynxpoint/acpi/serialio.asl: [test] support FixedDMA Change-Id: I90918c319088693e3cd970fbc69867ca7d34f17c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/lynxpoint/acpi/serialio.asl 1 file changed, 8 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/30130/1 diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 9323b91..b7b5de6 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -178,9 +178,8 @@ // DMA channels are only used if Serial IO DMA controller is enabled Name (DBUF, ResourceTemplate () { - // TODO: Need to update IASL to support FixedDMA - //FixedDMA (0x18, 4, Width32Bit, DMA1) // Tx - //FixedDMA (0x19, 5, Width32Bit, DMA2) // Rx + FixedDMA (0x18, 4, Width32Bit, DMA1) // Tx + FixedDMA (0x19, 5, Width32Bit, DMA2) // Rx }) Method (_CRS, 0, NotSerialized) @@ -260,9 +259,8 @@ // DMA channels are only used if Serial IO DMA controller is enabled Name (DBUF, ResourceTemplate () { - // TODO: Need to update IASL to support FixedDMA - //FixedDMA (0x1A, 6, Width32Bit, DMA1) // Tx - //FixedDMA (0x1B, 7, Width32Bit, DMA2) // Rx + FixedDMA (0x1A, 6, Width32Bit, DMA1) // Tx + FixedDMA (0x1B, 7, Width32Bit, DMA2) // Rx }) Method (_CRS, 0, NotSerialized) @@ -377,9 +375,8 @@ // DMA channels are only used if Serial IO DMA controller is enabled Name (DBUF, ResourceTemplate () { - // TODO: Need to update IASL to support FixedDMA - //FixedDMA (0x10, 0, Width32Bit, DMA1) // Tx - //FixedDMA (0x11, 1, Width32Bit, DMA2) // Rx + FixedDMA (0x10, 0, Width32Bit, DMA1) // Tx + FixedDMA (0x11, 1, Width32Bit, DMA2) // Rx }) Method (_CRS, 0, NotSerialized) @@ -428,9 +425,8 @@ // DMA channels are only used if Serial IO DMA controller is enabled Name (DBUF, ResourceTemplate () { - // TODO: Need to update IASL to support FixedDMA - //FixedDMA (0x16, 2, Width32Bit, DMA1) // Tx - //FixedDMA (0x17, 3, Width32Bit, DMA2) // Rx + FixedDMA (0x16, 2, Width32Bit, DMA1) // Tx + FixedDMA (0x17, 3, Width32Bit, DMA2) // Rx }) Method (_CRS, 0, NotSerialized) -- To view, visit https://review.coreboot.org/c/coreboot/+/30130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90918c319088693e3cd970fbc69867ca7d34f17c Gerrit-Change-Number: 30130 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/octopus/var/ampton: Tune I2C Audio
by Justin TerAvest (Code Review) 10 Dec '18

10 Dec '18

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30129 Change subject: mb/google/octopus/var/ampton: Tune I2C Audio ...................................................................... mb/google/octopus/var/ampton: Tune I2C Audio The previous settings caused the I2C frequency for the audio bus to be too high, at 417kHz. The settings in this commit correct the frequency to 396kHz. BUG=b:119423345 Change-Id: Ibed886e6e1b0df4df6b87f6291e515364b3bf718 Signed-off-by: Justin TerAvest <teravest(a)chromium.org> --- M src/mainboard/google/octopus/variants/ampton/overridetree.cb 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/30129/1 diff --git a/src/mainboard/google/octopus/variants/ampton/overridetree.cb b/src/mainboard/google/octopus/variants/ampton/overridetree.cb index 46d4dcd..b3f9416 100644 --- a/src/mainboard/google/octopus/variants/ampton/overridetree.cb +++ b/src/mainboard/google/octopus/variants/ampton/overridetree.cb @@ -12,8 +12,9 @@ }, .i2c[5] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 104, - .fall_time_ns = 52, + .rise_time_ns = 60, + .fall_time_ns = 20, + .data_hold_time_ns = 350, }, .i2c[6] = { .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/30129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibed886e6e1b0df4df6b87f6291e515364b3bf718 Gerrit-Change-Number: 30129 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: siemens/mc_apl4: Add GPIO configuration
by Mario Scheithauer (Code Review) 10 Dec '18

10 Dec '18

Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30128 ) Change subject: siemens/mc_apl4: Add GPIO configuration ...................................................................... Patch Set 2: (4 comments) https://review.coreboot.org/#/c/30128/2/src/mainboard/siemens/mc_apl1/varia… File src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c: https://review.coreboot.org/#/c/30128/2/src/mainboard/siemens/mc_apl1/varia… PS2, Line 28: */ one more - sorry, I overlooked it at first https://review.coreboot.org/#/c/30128/2/src/mainboard/siemens/mc_apl1/varia… PS2, Line 141: */ same https://review.coreboot.org/#/c/30128/2/src/mainboard/siemens/mc_apl1/varia… PS2, Line 232: */ same https://review.coreboot.org/#/c/30128/2/src/mainboard/siemens/mc_apl1/varia… PS2, Line 321: Wrong syntax for a comment -- To view, visit https://review.coreboot.org/c/coreboot/+/30128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia69603f42c57c1cc682550b8eeeab42fbac27563 Gerrit-Change-Number: 30128 Gerrit-PatchSet: 2 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 10 Dec 2018 14:25:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: siemens/mc_apl4: Add GPIO configuration
by uwe poeche (Code Review) 10 Dec '18

10 Dec '18

uwe poeche has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30128 ) Change subject: siemens/mc_apl4: Add GPIO configuration ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/30128/1/src/mainboard/siemens/mc_apl1/varia… File src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c: https://review.coreboot.org/#/c/30128/1/src/mainboard/siemens/mc_apl1/varia… PS1, Line 80: > One blank line is enough. Done https://review.coreboot.org/#/c/30128/1/src/mainboard/siemens/mc_apl1/varia… PS1, Line 358: TB > blank character Done -- To view, visit https://review.coreboot.org/c/coreboot/+/30128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia69603f42c57c1cc682550b8eeeab42fbac27563 Gerrit-Change-Number: 30128 Gerrit-PatchSet: 2 Gerrit-Owner: uwe poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: uwe poeche <uwe.poeche(a)siemens.com> Gerrit-Comment-Date: Mon, 10 Dec 2018 14:08:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: siemens/mc_apl4: Add GPIO configuration
by uwe poeche (Code Review) 10 Dec '18

10 Dec '18

Hello Werner Zeh, Mario Scheithauer, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30128 to look at the new patch set (#2). Change subject: siemens/mc_apl4: Add GPIO configuration ...................................................................... siemens/mc_apl4: Add GPIO configuration Add GPIO configuration to match the hardware of mc_apl4. Change-Id: Ia69603f42c57c1cc682550b8eeeab42fbac27563 Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc A src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c 2 files changed, 392 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/30128/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia69603f42c57c1cc682550b8eeeab42fbac27563 Gerrit-Change-Number: 30128 Gerrit-PatchSet: 2 Gerrit-Owner: uwe poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: uwe poeche <uwe.poeche(a)siemens.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: buildgcc: Update IASL to version 20181031
by HAOUAS Elyes (Code Review) 10 Dec '18

10 Dec '18

Hello build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30111 to look at the new patch set (#3). Change subject: buildgcc: Update IASL to version 20181031 ...................................................................... buildgcc: Update IASL to version 20181031 Update IASL from version 20180810 to 20181031 Change-Id: Ic83f4e220b7bcf0cfafa8dcb95f575b576e84996 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix2-20181031_iasl.patch D util/crossgcc/sum/acpica-unix2-20180810.tar.gz.cksum A util/crossgcc/sum/acpica-unix2-20181031.tar.gz.cksum 4 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/30111/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/30111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic83f4e220b7bcf0cfafa8dcb95f575b576e84996 Gerrit-Change-Number: 30111 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: siemens/mc_apl4: Add GPIO configuration
by Mario Scheithauer (Code Review) 10 Dec '18

10 Dec '18

Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30128 ) Change subject: siemens/mc_apl4: Add GPIO configuration ...................................................................... Patch Set 1: Code-Review+1 (2 comments) https://review.coreboot.org/#/c/30128/1/src/mainboard/siemens/mc_apl1/varia… File src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c: https://review.coreboot.org/#/c/30128/1/src/mainboard/siemens/mc_apl1/varia… PS1, Line 80: One blank line is enough. https://review.coreboot.org/#/c/30128/1/src/mainboard/siemens/mc_apl1/varia… PS1, Line 358: */ blank character -- To view, visit https://review.coreboot.org/c/coreboot/+/30128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia69603f42c57c1cc682550b8eeeab42fbac27563 Gerrit-Change-Number: 30128 Gerrit-PatchSet: 1 Gerrit-Owner: uwe poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: uwe poeche <uwe.poeche(a)siemens.com> Gerrit-Comment-Date: Mon, 10 Dec 2018 13:08:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: siemens/mc_apl4: Add GPIO configuration
by Uwe Pöche (Code Review) 10 Dec '18

10 Dec '18

Uwe Pöche has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30128 Change subject: siemens/mc_apl4: Add GPIO configuration ...................................................................... siemens/mc_apl4: Add GPIO configuration Add GPIO configuration to match the hardware of mc_apl4. Change-Id: Ia69603f42c57c1cc682550b8eeeab42fbac27563 Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc A src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c 2 files changed, 393 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/30128/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc index fd45b94..0a124ce 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc @@ -1 +1,4 @@ romstage-y += memory.c +romstage-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c new file mode 100644 index 0000000..edaa112 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c @@ -0,0 +1,390 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * Copyright (C) 2017-2018 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <commonlib/helpers.h> +#include <baseboard/variants.h> + +/* + * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' + * table found in EDS vol 1, but some pins aren't grouped functionally in + * the table so those were moved for more logical grouping. + */ +static const struct pad_config gpio_table[] = { + /* Southwest Community */ + + /* PCIE_WAKE[0:3]_N - unused*/ + PAD_CFG_GPI(GPIO_205, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_206, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_207, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_208, UP_20K, DEEP), + + /* EMMC interface. */ + PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC_CLK */ + PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC_D0 */ + PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1), /* EMMC_D1 */ + PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1), /* EMMC_D2 */ + PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1), /* EMMC_D3 */ + PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1), /* EMMC_D4 */ + PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1), /* EMMC_D5 */ + PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1), /* EMMC_D6 */ + PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1), /* EMMC_D7 */ + PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC_CMD */ + PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */ + + /* SDIO - unused */ + PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_167, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_168, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_169, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_170, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_171, DN_20K, DEEP), + + /* SDCARD */ + PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1), /* SDCARD_CLK */ + PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */ + PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */ + PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */ + PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */ + PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1), /* SDCARD_CD_N */ + PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */ + /* + * SDCARD_CLK_FB - APL EDS Vol1 remarks: + * This is not a physical GPIO that can be used. This Signal is not Ball + * out on the SoC, only the buffer exists. + */ + PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_186, UP_20K, DEEP, NF1), /* SDCARD_WP_1V8 */ + PAD_CFG_TERM_GPO(GPIO_183, 1, UP_20K, DEEP), /* SD_PWR_EN_1V8 */ + + /* West Community */ + + PAD_CFG_GPI(GPIO_124, DN_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_125, DN_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_126, DN_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_127, DN_20K, DEEP), /* unused */ + + + PAD_CFG_NF(GPIO_128, NONE, DEEP, NF1), /* provided LPSS_I2C2_SDA */ + PAD_CFG_NF(GPIO_129, NONE, DEEP, NF1), /* provided LPSS_I2C2_SCL */ + + PAD_CFG_GPI(GPIO_130, DN_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_131, DN_20K, DEEP), /* unused */ + + PAD_CFG_NF(GPIO_132, NONE, DEEP, NF1), /* provided LPSS_I2C4_SDA */ + PAD_CFG_NF(GPIO_133, NONE, DEEP, NF1), /* provided LPSS_I2C4_SCL */ + + /* + * Hint for USB enable power: some GPIOs are open drain outputs, + * to drive high -> Bit GPIO_TX_DIS has to be set in combination with PU + * PAD_CFG_GPO macro does not work. Refer to APL EDS Vol 4. + */ + PAD_CFG_GPI(GPIO_134, UP_20K, DEEP), /* enable USB0 power */ + PAD_CFG_GPI(GPIO_135, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_136, UP_20K, DEEP), /* enable USB7 power */ + PAD_CFG_GPI(GPIO_137, UP_20K, DEEP), /* enable USB6 power */ + PAD_CFG_GPI(GPIO_138, UP_20K, DEEP), /* enable USB2 power */ + PAD_CFG_GPI(GPIO_139, UP_20K, DEEP), /* enable USB1 power */ + + /* ISH_GPIO_[0:9] -- unused */ + PAD_CFG_GPI(GPIO_146, DN_20K, DEEP), /* ISH_GPIO_0 */ + PAD_CFG_GPI(GPIO_147, DN_20K, DEEP), /* ISH_GPIO_1 */ + PAD_CFG_GPI(GPIO_148, DN_20K, DEEP), /* ISH_GPIO_2 */ + PAD_CFG_GPI(GPIO_149, DN_20K, DEEP), /* ISH_GPIO_3 */ + PAD_CFG_GPI(GPIO_150, DN_20K, DEEP), /* ISH_GPIO_4 */ + PAD_CFG_GPI(GPIO_151, DN_20K, DEEP), /* ISH_GPIO_5 */ + PAD_CFG_GPI(GPIO_152, DN_20K, DEEP), /* ISH_GPIO_6 */ + PAD_CFG_GPI(GPIO_153, DN_20K, DEEP), /* ISH_GPIO_7 */ + PAD_CFG_GPI(GPIO_154, DN_20K, DEEP), /* ISH_GPIO_8 */ + PAD_CFG_GPI(GPIO_155, DN_20K, DEEP), /* ISH_GPIO_9 */ + + /* PCIE_CLKREQ[0:3]_N */ + PAD_CFG_NF(GPIO_209, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_210, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_211, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_212, DN_20K, DEEP, NF1), + + /* OSC_CLK_OUT_[0:4] - unused */ + PAD_CFG_GPI(OSC_CLK_OUT_0, DN_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_1, DN_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_2, DN_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_3, DN_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_4, DN_20K, DEEP), + + /* PMU Signals */ + PAD_CFG_NF(PMU_AC_PRESENT, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), + PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1), + PAD_CFG_GPI(PMU_SLP_S0_B, UP_20K, DEEP), + PAD_CFG_GPI(PMU_SLP_S3_B, UP_20K, DEEP), + PAD_CFG_GPI(PMU_SLP_S4_B, UP_20K, DEEP), + PAD_CFG_GPI(PMU_SUSCLK, DN_20K, DEEP), + PAD_CFG_GPI(PMU_WAKE_B, DN_20K, DEEP), + PAD_CFG_GPI(SUS_STAT_B, DN_20K, DEEP), + PAD_CFG_GPI(SUSPWRDNACK, DN_20K, DEEP), + + /* Northwest Community */ + + /* DDI0 SDA and SCL - Display-Port X24*/ + PAD_CFG_NF(GPIO_187, UP_20K, DEEP, NF1), /* HV_DDI0_DDC_SDA */ + PAD_CFG_NF(GPIO_188, UP_20K, DEEP, NF1), /* HV_DDI0_DDC_SCL */ + /* DDI1 SDA and SCL - unused */ + PAD_CFG_GPI(GPIO_189, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_190, DN_20K, DEEP), + /* MIPI I2C - unused */ + PAD_CFG_GPI(GPIO_191, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_192, DN_20K, DEEP), + + /* Panel 0 control - unused */ + PAD_CFG_GPI(GPIO_193, DN_20K, DEEP), /* PNL0_VDDEN */ + PAD_CFG_GPI(GPIO_194, DN_20K, DEEP), /* PNL0_BKLTEN */ + PAD_CFG_GPI(GPIO_195, DN_20K, DEEP), /* PNL0_BKLTCTL */ + + /* Panel 1 control - unused */ + PAD_CFG_GPI(GPIO_196, DN_20K, DEEP), /* PNL1_VDDEN */ + PAD_CFG_GPI(GPIO_197, DN_20K, DEEP), /* PNL1_BKLTEN */ + PAD_CFG_GPI(GPIO_198, DN_20K, DEEP), /* PNL1_BKLTCTL */ + + /* DDI[0:1]_HPD */ + PAD_CFG_GPI(GPIO_199, UP_20K, DEEP), /* DDI1_HPD unused */ + PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* DDI0_HDP X24 */ + + /* MDSI signals - unused */ + PAD_CFG_GPI(GPIO_201, DN_20K, DEEP), /* MDSI_A_TE */ + PAD_CFG_GPI(GPIO_202, DN_20K, DEEP), /* MDSI_C_TE */ + + /* USB overcurrent pins. */ + PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1), /* USB_OC0_N */ + PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1), /* USB_OC1_N */ + + /* PMC SPI */ + PAD_CFG_GPI(PMC_SPI_FS0, DN_20K, DEEP), /* unused */ + PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2), /* XHPD_EDP_APL */ + PAD_CFG_GPI(PMC_SPI_FS2, DN_20K, DEEP), /* unused */ + PAD_CFG_GPI(PMC_SPI_RXD, DN_20K, DEEP), /* unused */ + PAD_CFG_GPI(PMC_SPI_TXD, DN_20K, DEEP), /* unused */ + PAD_CFG_GPI(PMC_SPI_CLK, DN_20K, DEEP), /* unused */ + + /* PMIC Signals unused signals related to an old PMIC interface. */ + PAD_CFG_GPI(PMIC_PWRGOOD, DN_20K, DEEP), /* PMIC_PWRGOOD */ + PAD_CFG_GPI(PMIC_RESET_B, DN_20K, DEEP), /* PMIC_RESET_B */ + PAD_CFG_GPI(GPIO_213, UP_20K, DEEP), /* PMIC_SDWN_B */ + PAD_CFG_GPI(GPIO_214, DN_20K, DEEP), /* PMIC_BCUDISW2 */ + PAD_CFG_GPI(GPIO_215, DN_20K, DEEP), /* PMIC_BCUDISCRIT */ + PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1),/* THERMTRIP_N */ + PAD_CFG_GPI(PMIC_STDBY, DN_20K, DEEP), /* PMIC_STDBY */ + PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1), /* PROCHOT_N */ + PAD_CFG_GPI(PMIC_I2C_SCL, DN_20K, DEEP), /* unused */ + PAD_CFG_GPI(PMIC_I2C_SDA, DN_20K, DEEP), /* unused */ + + /* I2S1 - unused */ + PAD_CFG_GPI(GPIO_74, DN_20K, DEEP), /* I2S1_MCLK */ + PAD_CFG_GPI(GPIO_75, DN_20K, DEEP), /* I2S1_BCLK */ + PAD_CFG_GPI(GPIO_76, DN_20K, DEEP), /* I2S1_WS_SYNC */ + PAD_CFG_GPI(GPIO_77, DN_20K, DEEP), /* I2S1_SDI */ + PAD_CFG_GPI(GPIO_78, DN_20K, DEEP), /* I2S1_SDO */ + + /* DMIC or I2S4 - unused */ + PAD_CFG_GPI(GPIO_79, DN_20K, DEEP), /* AVS_M_CLK_A1 */ + PAD_CFG_GPI(GPIO_80, DN_20K, DEEP), /* AVS_M_CLK_B1 */ + PAD_CFG_GPI(GPIO_81, DN_20K, DEEP), /* AVS_M_DATA_1 */ + PAD_CFG_GPI(GPIO_82, DN_20K, DEEP), /* AVS_M_CLK_AB2 */ + PAD_CFG_GPI(GPIO_83, DN_20K, DEEP), /* AVS_M_DATA_2 */ + + /* I2S2 - unused */ + PAD_CFG_GPO(GPIO_84, 0, DEEP), /* AVS_I2S2_MCLK */ + PAD_CFG_GPI(GPIO_85, DN_20K, DEEP), /* AVS_I2S2_BCLK */ + PAD_CFG_GPI(GPIO_86, DN_20K, DEEP), /* AVS_I2S2_WS_SYNC */ + PAD_CFG_GPI(GPIO_87, DN_20K, DEEP), /* AVS_I2S2_SDI */ + PAD_CFG_GPI(GPIO_88, DN_20K, DEEP), /* AVS_I2S2_SDO */ + + /* I2S3 - unused */ + PAD_CFG_GPI(GPIO_89, DN_20K, DEEP), /* AVS_I2S3_BCLK */ + PAD_CFG_GPI(GPIO_90, DN_20K, DEEP), /* AVS_I2S3_WS_SYNC */ + PAD_CFG_GPI(GPIO_91, DN_20K, DEEP), /* AVS_I2S3_SDI */ + PAD_CFG_GPI(GPIO_92, DN_20K, DEEP), /* AVS_I2S3_SDO */ + + /* Fast SPI for mainboard Flash and TPM on mainboard. */ + PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1), /* FST_SPI_CS0_B */ + PAD_CFG_GPI(GPIO_98, DN_20K, DEEP), /* FST_SPI_CS1_B - unused */ + PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), /* FST_SPI_MOSI_IO0 */ + PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1),/* FST_SPI_MISO_IO1 */ + PAD_CFG_NF(GPIO_101, NATIVE, DEEP, NF1),/* FST_IO2 - MEM_CONFIG0 */ + PAD_CFG_NF(GPIO_102, NATIVE, DEEP, NF1),/* FST_IO3 - MEM_CONFIG1 */ + PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1),/* FST_SPI_CLK */ + /* FST_SPI_CLK_FB - Pad not bonded, default register value is the same + * as here. Refer to Intel Doc APL EDS Vol 1 */ + PAD_CFG_NF(FST_SPI_CLK_FB, NONE, DEEP, NF1), + + /* SIO_SPI_0 for F-module on mainboard*/ + PAD_CFG_NF(GPIO_104, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_105, UP_20K, DEEP, NF1), + /* GPIO_106 configured as XCS for TPM */ + PAD_CFG_NF(GPIO_106, UP_20K, DEEP, NF3), + PAD_CFG_NF(GPIO_109, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_110, UP_20K, DEEP, NF1), + + /* SIO_SPI_1 -- unused */ + PAD_CFG_GPI(GPIO_111, DN_20K, DEEP), /* GP_SSP_1_CLK */ + PAD_CFG_GPI(GPIO_112, DN_20K, DEEP), /* GP_SSP_1_FS0 */ + PAD_CFG_GPI(GPIO_113, DN_20K, DEEP), /* GP_SSP_1_FS1 */ + PAD_CFG_GPI(GPIO_116, DN_20K, DEEP), /* GP_SSP_1_RXD */ + PAD_CFG_GPI(GPIO_117, DN_20K, DEEP), /* GP_SSP_1_TXD */ + + /* SIO_SPI_2 -- unused */ + PAD_CFG_GPI(GPIO_118, UP_20K, DEEP), /* GP_SSP_2_CLK */ + PAD_CFG_GPI(GPIO_119, DN_20K, DEEP), /* GP_SSP_2_FS0 */ + PAD_CFG_GPI(GPIO_120, DN_20K, DEEP), /* GP_SSP_2_FS1 */ + PAD_CFG_GPI(GPIO_121, DN_20K, DEEP), /* GP_SSP_2_FS2 */ + PAD_CFG_GPI(GPIO_122, DN_20K, DEEP), /* GP_SSP_2_RXD */ + PAD_CFG_GPI(GPIO_123, DN_20K, DEEP), /* GP_SSP_2_TXD */ + + /* North Community */ + + PAD_CFG_GPI(GPIO_0, DN_20K, DEEP), + /* GPIO_1 in early_gpio_table */ + PAD_CFG_GPI(GPIO_2, DN_20K, DEEP), + /* GPIO_3,4 in early_gpio_table */ + PAD_CFG_GPI(GPIO_5, DN_20K, DEEP), /* TRACE_0_DATA4_VNN */ + PAD_CFG_GPI(GPIO_6, DN_20K, DEEP), /* TRACE_0_DATA5_VNN */ + PAD_CFG_GPO(GPIO_7, 0, DEEP), + PAD_CFG_GPI(GPIO_8, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_9, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_10, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_11, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_12, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_13, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_14, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_15, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_16, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_17, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_18, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_19, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_20, DN_20K, DEEP), + PAD_CFG_GPO(GPIO_21, 0, DEEP), /* activate SMARC Ethernetmac 2 */ + PAD_CFG_GPO(GPIO_22, 0, DEEP), /* activate SMARC Ethernetmac 1 */ + PAD_CFG_GPI(GPIO_23, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_24, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_25, DN_20K, DEEP), /* pin open */ + PAD_CFG_NF(GPIO_26, UP_20K, DEEP, NF5), /* SATA_LEDN */ + PAD_CFG_GPI(GPIO_27, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPO(GPIO_28, 1, DEEP), /* disable SMARC HDMI */ + PAD_CFG_GPO(GPIO_29, 0, DEEP), + PAD_CFG_GPI(GPIO_30, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_31, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_32, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_33, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_34, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_35, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_36, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_37, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_38, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* pin open */ + + /* LPSS_UART[0:2] */ + PAD_CFG_GPI(GPIO_41, DN_20K, DEEP), /* pin open */ + /* GPIO_42/43 are in early_gpio_table */ + PAD_CFG_GPI(GPIO_44, DN_20K, DEEP), /* LPSS_UART1_RTS - unused */ + PAD_CFG_GPI(GPIO_45, DN_20K, DEEP), /* LPSS_UART1_CTS - unused */ + /* GPIO_46/47 are in early_gpio_table */ + PAD_CFG_GPI(GPIO_48, DN_20K, DEEP), /* LPSS_UART2_RTS - unused */ + PAD_CFG_GPI(GPIO_49, DN_20K, DEEP), /* LPSS_UART2_CTS - unused */ + + /* Camera interface -- completely unused. */ + PAD_CFG_GPI(GPIO_62, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_63, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_64, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_65, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_66, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_67, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPO(GPIO_68, 0, DEEP), /* APL4 Testpoint P403 */ + PAD_CFG_GPO(GPIO_69, 0, DEEP), /* APL4 Testpoint P404 */ + PAD_CFG_GPI(GPIO_70, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPO(GPIO_71, 1, DEEP), /* XCHC_UPD_REQ */ + PAD_CFG_GPO(GPIO_72, 0, DEEP), /* APL4 Testpoint P402 */ + PAD_CFG_GPI(GPIO_73, DN_20K, DEEP), /* pin open */ + + //no TAP controller pins available on SMARC of APL4 + PAD_CFG_GPI(TCK, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(TRST_B, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(TMS, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(TDI, DN_20K, DEEP), /* pin open */ + + PAD_CFG_GPI(CX_PMODE, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(CX_PREQ_B, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(JTAGX, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(CX_PRDY_B, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(TDO, DN_20K, DEEP), /* pin open */ + + /* GPIO_[216:219] described into EDS Vol1. */ + PAD_CFG_GPO(CNV_BRI_DT, 0, DEEP), /* Disable eDP to LVDS bridge */ + PAD_CFG_GPI(CNV_BRI_RSP, UP_20K, DEEP), + PAD_CFG_GPI(CNV_RGI_DT, DN_20K, DEEP), /* pin open */ + + /* Writing to following GPIO registers leads to 0xFFFF FFFF in CFG0/1 */ + PAD_CFG_GPI(CNV_RGI_RSP, DN_20K, DEEP), /* pin open */ + + /* Serial Voltage Identification */ + PAD_CFG_NF(SVID0_ALERT_B, NONE, DEEP, NF1), /* SVID0_ALERT_B */ + PAD_CFG_NF(SVID0_DATA, UP_20K, DEEP, NF1), /* SVID0_DATA */ + PAD_CFG_NF(SVID0_CLK, UP_20K, DEEP, NF1), /* SVID0_CLK */ +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* GPIOs needed prior to ramstage. */ +static const struct pad_config early_gpio_table[] = { + /* Southwest Community */ + + /* Multiplexed I2C7*/ + PAD_CFG_NF(SMB_ALERTB, UP_20K, DEEP, NF2), + PAD_CFG_NF(SMB_CLK, UP_20K, DEEP, NF2), + PAD_CFG_NF(SMB_DATA, UP_20K, DEEP, NF2), + + /* get LPC Bus early working */ + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT1, NONE, DEEP, NF1), + PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1), + + /* North Community */ + PAD_CFG_GPO(GPIO_1, 1, DEEP), /* XPCIE_A_RST */ + PAD_CFG_GPO(GPIO_3, 1, DEEP), /* XPCIE_B_RST */ + PAD_CFG_GPO(GPIO_4, 1, DEEP), /* XPCIE_C_RST */ + + /* UARTs for early coreboot output */ + PAD_CFG_NF(GPIO_42, UP_20K, DEEP, NF1), /* LPSS_UART1_RXD */ + PAD_CFG_NF(GPIO_43, UP_20K, DEEP, NF1), /* LPSS_UART1_TXD */ + PAD_CFG_NF(GPIO_46, UP_20K, DEEP, NF1), /* LPSS_UART2_RXD */ + PAD_CFG_NF(GPIO_47, UP_20K, DEEP, NF1), /* LPSS_UART2_TXD */ +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia69603f42c57c1cc682550b8eeeab42fbac27563 Gerrit-Change-Number: 30128 Gerrit-PatchSet: 1 Gerrit-Owner: Uwe Pöche <uwe.poeche(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mediatek/mt8183: Deselect BOOTBLOCK_CONSOLE
by You-Cheng Syu (Code Review) 10 Dec '18

10 Dec '18

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30127 Change subject: mediatek/mt8183: Deselect BOOTBLOCK_CONSOLE ...................................................................... mediatek/mt8183: Deselect BOOTBLOCK_CONSOLE MT8183 only allows booting from eMMC, so we have to do eMMC emulation from an external source, for example EC, which makes the size of bootblock very important. Currently a fully functional bootblock is about 26000 bytes. If we deselect BOOTBLOCK_CONSOLE, it can be reduced to about 19500 bytes (75%). Since we don't have much logic in mt8183 bootblock, it should be fine to disable console in bootblock. BUG=b:120588396 TEST=manually flashed into kukui and boots into kernel Change-Id: I84909fc8dbba972c8293070fcf71391cd9ae0151 --- M src/soc/mediatek/mt8183/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/30127/1 diff --git a/src/soc/mediatek/mt8183/Kconfig b/src/soc/mediatek/mt8183/Kconfig index b58be7f..fdc22a2 100644 --- a/src/soc/mediatek/mt8183/Kconfig +++ b/src/soc/mediatek/mt8183/Kconfig @@ -6,7 +6,6 @@ select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 select ARM64_USE_ARM_TRUSTED_FIRMWARE - select BOOTBLOCK_CONSOLE select GENERIC_UDELAY select HAVE_UART_SPECIAL select HAVE_MONOTONIC_TIMER -- To view, visit https://review.coreboot.org/c/coreboot/+/30127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84909fc8dbba972c8293070fcf71391cd9ae0151 Gerrit-Change-Number: 30127 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/intel/icelake_rvp: Fill Icelake U and Y RVP devicetree parameters
by Subrata Banik (Code Review) 10 Dec '18

10 Dec '18

Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30015 ) Change subject: mb/intel/icelake_rvp: Fill Icelake U and Y RVP devicetree parameters ...................................................................... mb/intel/icelake_rvp: Fill Icelake U and Y RVP devicetree parameters This implementation configures below parameters: 1. Enable SaGv, isclk. 2. Set Pcie rootport enable, Clock source usage and clkreq. 3. Configure SATA and LPSS controllers parameters. 4. Enable CNVI controller, configure Wifi end device under PCIE RP1. 5. Add TPM device support under GSPI1. Change-Id: I585e82799eea0bad19ad2c94d6b4b3024f930ed4 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> Reviewed-on: https://review.coreboot.org/c/30015 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb M src/soc/intel/icelake/chip.h 3 files changed, 279 insertions(+), 64 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb index a971332..0d2ea76 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb @@ -4,28 +4,40 @@ device lapic 0 on end end + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + # FSP configuration - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1" + register "SdCardPowerEnableActiveHigh" = "1" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB3/2 Type A port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # USB2 WWAN - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # USB2 Bluetooth + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2 WWAN + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Bluetooth register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # Type-C Port1 register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 - register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-C Port3 - register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Type-C Port4 + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 + register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-C Port4 register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 - register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" # USB2 Type A port2 - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" # USB2 Type A port2 + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB2 Type A port1 + register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # USB2 Type A port2 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3 WLAN - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WLAN + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + + # Enable Pch iSCLK + register "pch_isclk" = "1" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" @@ -36,6 +48,8 @@ register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" + register "PrmrrSize" = "0x10000000" + register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" register "PcieRpEnable[2]" = "1" @@ -53,12 +67,22 @@ register "PcieRpEnable[14]" = "1" register "PcieRpEnable[15]" = "1" - register "PcieClkSrcUsage[0]" = "1" + register "PcieClkSrcUsage[0]" = "2" register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" - register "PcieClkSrcUsage[3]" = "13" + register "PcieClkSrcUsage[2]" = "0xC" + register "PcieClkSrcUsage[3]" = "0x70" register "PcieClkSrcUsage[4]" = "4" - register "PcieClkSrcUsage[5]" = "14" + register "PcieClkSrcUsage[5]" = "0xE" + register "PcieClkSrcUsage[6]" = "0x80" + register "PcieClkSrcUsage[7]" = "0x80" + register "PcieClkSrcUsage[8]" = "0x80" + register "PcieClkSrcUsage[9]" = "0x80" + register "PcieClkSrcUsage[10]" = "0x80" + register "PcieClkSrcUsage[11]" = "0x80" + register "PcieClkSrcUsage[12]" = "0x80" + register "PcieClkSrcUsage[13]" = "0x80" + register "PcieClkSrcUsage[14]" = "0x80" + register "PcieClkSrcUsage[15]" = "0x80" register "PcieClkSrcClkReq[0]" = "0" register "PcieClkSrcClkReq[1]" = "1" @@ -66,6 +90,69 @@ register "PcieClkSrcClkReq[3]" = "3" register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcClkReq[6]" = "6" + register "PcieClkSrcClkReq[7]" = "7" + register "PcieClkSrcClkReq[8]" = "8" + register "PcieClkSrcClkReq[9]" = "9" + register "PcieClkSrcClkReq[10]" = "10" + register "PcieClkSrcClkReq[11]" = "11" + register "PcieClkSrcClkReq[12]" = "12" + register "PcieClkSrcClkReq[13]" = "13" + register "PcieClkSrcClkReq[14]" = "14" + register "PcieClkSrcClkReq[15]" = "15" + + register "SataEnable" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "SataPortsDevSlp[0]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "SataPortsDevSlp[2]" = "1" + register "SataPortsDevSlp[3]" = "1" + register "SataPortsDevSlp[4]" = "1" + register "SataPortsDevSlp[5]" = "1" + register "SataPortsDevSlp[6]" = "1" + register "SataPortsDevSlp[7]" = "1" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 1, + [PchSerialIoIndexGSPI1] = 1, + [PchSerialIoIndexGSPI2] = 1, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" @@ -74,29 +161,32 @@ register "sdcard_cd_gpio" = "GPP_G5" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| I2C3 | Audio | + #| GSPI1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | #+-------------------+---------------------------+ + register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .i2c[3] = { - .speed = I2C_SPEED_STANDARD, - .rise_time_ns = 104, - .fall_time_ns = 52, + .gspi[1] = { + .speed_mhz = 1, + .early_init = 1, }, }" device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem + device pci 04.0 off end # SA Thermal device + device pci 12.0 off end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 device pci 14.0 on @@ -188,6 +278,7 @@ end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 off end # PMC SRAM chip drivers/intel/wifi register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi wifi @@ -203,7 +294,7 @@ end end # I2C 0 device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 + device pci 15.2 on end # I2C #2 device pci 15.3 on end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 @@ -211,12 +302,17 @@ device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA + device pci 17.0 on end # SATA device pci 19.0 on end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 + device pci 1c.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_PCI_EXP" + device pci 00.0 on end + end + end # PCI Express Port 1 x4 SLOT1 device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 @@ -232,12 +328,15 @@ device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end + device pci 1e.3 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + device spi 0 on end end - end # LPC Interface + end # GSPI #1 + device pci 1f.0 on end # eSPI Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel HDA diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index 787097e..62c7a82 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -4,28 +4,40 @@ device lapic 0 on end end + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + # FSP configuration - register "SaGv" = "3" + register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1" + register "SdCardPowerEnableActiveHigh" = "1" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB3/2 Type A port1 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB3/2 Type A port2 - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # Bluetooth + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB3/2 Type A port2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # Type-C Port1 register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 - register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-C Port3 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" # UNUSED - register "usb2_ports[7]" = "USB2_PORT_EMPTY" # UNUSED - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # USB2 Type A port1 - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" # USB2 Type A port2 + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # UNUSED + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # UNUSED + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port1 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port2 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3 WLAN - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WLAN + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + + # Enable Pch iSCLK + register "pch_isclk" = "1" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" @@ -35,8 +47,8 @@ register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" - register "PchHdaAudioLinkSsp0" = "1" - register "PchHdaAudioLinkSsp1" = "1" + + register "PrmrrSize" = "0x10000000" register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" @@ -52,13 +64,25 @@ register "PcieRpEnable[11]" = "1" register "PcieRpEnable[12]" = "1" register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[15]" = "1" - register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[0]" = "0x80" register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" - register "PcieClkSrcUsage[3]" = "14" - register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcUsage[5]" = "1" + register "PcieClkSrcUsage[2]" = "0xC" + register "PcieClkSrcUsage[3]" = "0x70" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcUsage[5]" = "2" + register "PcieClkSrcUsage[6]" = "0x80" + register "PcieClkSrcUsage[7]" = "0x80" + register "PcieClkSrcUsage[8]" = "0x80" + register "PcieClkSrcUsage[9]" = "0x80" + register "PcieClkSrcUsage[10]" = "0x80" + register "PcieClkSrcUsage[11]" = "0x80" + register "PcieClkSrcUsage[12]" = "0x80" + register "PcieClkSrcUsage[13]" = "0x80" + register "PcieClkSrcUsage[14]" = "0x80" + register "PcieClkSrcUsage[15]" = "0x80" register "PcieClkSrcClkReq[0]" = "0" register "PcieClkSrcClkReq[1]" = "1" @@ -66,6 +90,69 @@ register "PcieClkSrcClkReq[3]" = "3" register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcClkReq[6]" = "6" + register "PcieClkSrcClkReq[7]" = "7" + register "PcieClkSrcClkReq[8]" = "8" + register "PcieClkSrcClkReq[9]" = "9" + register "PcieClkSrcClkReq[10]" = "10" + register "PcieClkSrcClkReq[11]" = "11" + register "PcieClkSrcClkReq[12]" = "12" + register "PcieClkSrcClkReq[13]" = "13" + register "PcieClkSrcClkReq[14]" = "14" + register "PcieClkSrcClkReq[15]" = "15" + + register "SataEnable" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "SataPortsDevSlp[0]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "SataPortsDevSlp[2]" = "1" + register "SataPortsDevSlp[3]" = "1" + register "SataPortsDevSlp[4]" = "1" + register "SataPortsDevSlp[5]" = "1" + register "SataPortsDevSlp[6]" = "1" + register "SataPortsDevSlp[7]" = "1" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 1, + [PchSerialIoIndexGSPI1] = 1, + [PchSerialIoIndexGSPI2] = 1, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" @@ -74,13 +161,32 @@ register "sdcard_cd_gpio" = "GPP_G5" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #+-------------------+---------------------------+ + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[1] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem + device pci 04.0 off end # SA Thermal device + device pci 12.0 off end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 device pci 14.0 on @@ -172,6 +278,7 @@ end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 off end # PMC SRAM chip drivers/intel/wifi register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi wifi @@ -187,20 +294,25 @@ end end # I2C 0 device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 on end # I2C #3 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA + device pci 17.0 on end # SATA device pci 19.0 on end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 + device pci 1c.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_PCI_EXP" + device pci 00.0 on end + end + end # PCI Express Port 1 x4 SLOT1 device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 @@ -216,12 +328,15 @@ device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end + device pci 1e.3 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + device spi 0 on end end - end # LPC Interface + end # GSPI #1 + device pci 1f.0 on end # eSPI Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel HDA diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index c8653b2..3e2b78a 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -115,6 +115,7 @@ uint16_t usb3_wake_enable_bitmap; /* SATA related */ + uint8_t SataEnable; uint8_t SataMode; uint8_t SataSalpSupport; uint8_t SataPortsEnable[8]; -- To view, visit https://review.coreboot.org/c/coreboot/+/30015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I585e82799eea0bad19ad2c94d6b4b3024f930ed4 Gerrit-Change-Number: 30015 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit December 2018