coreboot-gerrit December 2018

coreboot-gerrit@coreboot.org

1 participants
1832 discussions

Change in ...coreboot[master]: soc/intel/braswell/northcluster.c: Fix typo
by Frans Hendriks (Code Review) 10 Dec '18

10 Dec '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30125 Change subject: soc/intel/braswell/northcluster.c: Fix typo ...................................................................... soc/intel/braswell/northcluster.c: Fix typo Correct typo of 'resource' BUG=N/A TEST=N/A Change-Id: I79dde87007759b7cab92061df37fd3a19d5e3d1f Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/northcluster.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/30125/1 diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index dcd98b5..1e5204e 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -53,7 +53,7 @@ * +--------------------------+ 0 * * Note that there are really only a few regions that need to enumerated w.r.t. - * coreboot's resrouce model: + * coreboot's resource model: * * +--------------------------+ BMBOUND_HI * | Cacheable/Usable | -- To view, visit https://review.coreboot.org/c/coreboot/+/30125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79dde87007759b7cab92061df37fd3a19d5e3d1f Gerrit-Change-Number: 30125 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mb/google/sarien: Update GPIOs for next build
by Patrick Georgi (Code Review) 10 Dec '18

10 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30062 ) Change subject: mb/google/sarien: Update GPIOs for next build ...................................................................... mb/google/sarien: Update GPIOs for next build Update the GPIOs for the next board build. Mostly minor changes but the polarity change on GPP_E8/RECOVERY on sarien will result in it booting to recovery every time unless using new hardware. For this reason the recovery mode GPIO that is passed to vboot is commented out for sarien. It is only used for testing and currently it is useful to have an image that works on both board versions. Change-Id: I32d84f3010cb4d3968370a03f7e191b1710a50e8 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/c/30062 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/sarien/gpio.c 2 files changed, 40 insertions(+), 27 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index 0ffd029..a29fd06 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -30,18 +30,23 @@ /* ESPI_CLK */ /* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* PME# */ PAD_NC(GPP_A11, NONE), -/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), + /* ISH_LID_CL#_TAB */ +/* BM_BUSY# */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* SUSWARN# */ PAD_NC(GPP_A13, NONE), /* ESPI_RESET# */ /* SUSACK# */ PAD_NC(GPP_A15, NONE), /* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), /* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), -/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), -/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), + /* ISH_ACC1_INT# */ +/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* ISH_ACC2_INT# */ +/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* ISH_GP2 */ PAD_NC(GPP_A20, NONE), /* ISH_GP3 */ PAD_NC(GPP_A21, NONE), -/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), -/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), + /* ISH_NB_MODE */ +/* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), + /* ISH_LID_CL#_NB */ +/* ISH_GP5 */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* CORE_VID0 */ /* CORE_VID1 */ @@ -49,12 +54,17 @@ /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ + /* LAN_CLKREQ_CPU_N */ /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* CARD_CLKREQ_CPU_N */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* WLAN_CLKREQ_CPU_N */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* WWAN_CLKREQ_CPU_N */ /* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* SSD_CKLREQ_CPU_N */ /* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* TBT_CLKREQ_CPU_N (nostuff) */ /* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */ /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), @@ -63,7 +73,7 @@ /* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */ /* GSPI0_MISO */ PAD_CFG_GPI(GPP_B17, NONE, DEEP), /* RTC_DET# */ /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), -/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ /* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ /* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), @@ -112,8 +122,10 @@ /* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE), /* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */ /* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE), -/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), -/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), + /* ISH_CPU_UART0_RX */ +/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* ISH_CPU_UART0_TX */ +/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */ /* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), /* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */ @@ -144,10 +156,10 @@ /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ -/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_SCL_CPU */ +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_SDA_CPU */ /* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), /* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), /* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), @@ -179,9 +191,9 @@ /* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE), /* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */ -/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */ /* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* TBT_CIO_PLUG_EVT# (nostuff) */ -/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), /* T383 */ +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), /* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */ /* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */ /* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */ diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index a41d940..38d21c8 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -49,11 +49,11 @@ /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ -/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), -/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), -/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), -/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), -/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLKREQ_PCIE#0 */ +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* CLKREQ_PCIE#1 */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* CLKREQ_PCIE#2 */ +/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* CLKREQ_PCIE#3 */ +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* CLKREQ_PCIE#4 */ /* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */ /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), @@ -63,8 +63,7 @@ /* GSPI0_CLK */ PAD_NC(GPP_B16, NONE), /* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), -/* GSPI1_CS# */ PAD_CFG_GPI_APIC(GPP_B19, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* HDD_FALL_INT */ +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ /* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ /* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), @@ -101,7 +100,7 @@ EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ /* SPI1_CLK */ PAD_NC(GPP_D1, NONE), /* SPI1_MISO */ PAD_NC(GPP_D2, NONE), -/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), +/* SPI1_MOSI */ PAD_CFG_GPI(GPP_D3, NONE, DEEP), /* RTC_DET# */ /* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), /* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), @@ -135,7 +134,7 @@ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */ /* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */ /* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */ -/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */ +/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */ /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */ /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB_OC2# */ @@ -143,8 +142,7 @@ /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* HDMI_DP1_HPD */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* CPU_DP2_HPD */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ -/* DDPE_HPD3 */ PAD_CFG_GPI_APIC(GPP_E16, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* FFS_INT2 */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), @@ -237,7 +235,7 @@ /* RESET# need to stay low before FULL_CARD_POWER_OFF assert */ /* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */ /* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ -/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */ +/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ }; @@ -254,7 +252,10 @@ } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AH(GPP_E8, CROS_GPIO_DEVICE_NAME), + /* + * TODO: re-enable recovery mode when boards are updated: + * CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), + */ CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/30062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32d84f3010cb4d3968370a03f7e191b1710a50e8 Gerrit-Change-Number: 30062 Gerrit-PatchSet: 5 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: mb/google/sarien: Setup GPIOs again after FSP-S
by Patrick Georgi (Code Review) 10 Dec '18

10 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30113 ) Change subject: mb/google/sarien: Setup GPIOs again after FSP-S ...................................................................... mb/google/sarien: Setup GPIOs again after FSP-S Currently CoffeeLake FSP is incorrectly modifying GPIO pad configuration if specific UPD variables are not set as it expects. This affects the display-related SOC pads with the following UPD variables: UINT8 DdiPortBHpd; // GPP_E13 UINT8 DdiPortCHpd; // GPP_E14 UINT8 DdiPortDHpd; // GPP_E15 UINT8 DdiPortFHpd; // GPP_E16 UINT8 DdiPortBDdc; // GPP_E18/GPP_E19 UINT8 DdiPortCDdc; // GPP_E20/GPP_E21 UINT8 DdiPortDDdc; // GPP_E22/GPP_E23 UINT8 DdiPortFDdc; // GPP_H16/GPP_H17 Until FSP is fixed to not touch the pad configuration this workaround will reprogram the GPIO settings after FSP-S step so they are correct when the OS attempts to use them. This was found in CoffeLake FSP Gold release: https://github.com/IntelFsp/FSP/tree/master/CoffeeLakeFspBinPkg As well as the current top-of-tree for the FSP sources. BUG=b:120686247,chromium:913216 TEST=verify correct GPIO configuration for GPP_E group in the kernel Change-Id: I19550c4347cf65d409de6a8638619270372c4d0a Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/c/30113 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao(a)intel.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/sarien/ramstage.c 1 file changed, 11 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Lijian Zhao: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index c65104b..c2dc27d 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -27,8 +27,19 @@ gpio_configure_pads(gpio_table, num_gpios); } +/* Workaround FSP issue by reprogramming GPIOs after FSP-S */ +static void mainboard_init(struct device *dev) +{ + const struct pad_config *gpio_table; + size_t num_gpios; + + gpio_table = variant_gpio_table(&num_gpios); + gpio_configure_pads(gpio_table, num_gpios); +} + static void mainboard_enable(struct device *dev) { + dev->ops->init = mainboard_init; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } -- To view, visit https://review.coreboot.org/c/coreboot/+/30113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19550c4347cf65d409de6a8638619270372c4d0a Gerrit-Change-Number: 30113 Gerrit-PatchSet: 3 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: mb/{intel, google}/{icelake_rvp, dragonegg}: Move cpuid(1) function int...
by Subrata Banik (Code Review) 10 Dec '18

10 Dec '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30124 Change subject: mb/{intel,google}/{icelake_rvp,dragonegg}: Move cpuid(1) function into cpu common code ...................................................................... mb/{intel,google}/{icelake_rvp,dragonegg}: Move cpuid(1) function into cpu common code This patch replaces all cpuid(1) references from icelake mainboard with intel cpu common code library functions. - cpu_get_cpuid() -> to get processor id (from cpuid.eax) Change-Id: Ia12d95d911dd6ee60a3a35937264fef668ad9e35 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/google/dragonegg/variants/baseboard/memory.c M src/mainboard/intel/icelake_rvp/spd/spd_util.c 2 files changed, 4 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/30124/1 diff --git a/src/mainboard/google/dragonegg/variants/baseboard/memory.c b/src/mainboard/google/dragonegg/variants/baseboard/memory.c index c7d579b..dac8e2d 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/memory.c +++ b/src/mainboard/google/dragonegg/variants/baseboard/memory.c @@ -16,6 +16,7 @@ #include <arch/cpu.h> #include <baseboard/variants.h> #include <gpio.h> +#include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> #include <variant/gpio.h> @@ -36,19 +37,6 @@ /* Rcomp resistor */ static const u16 rcomp_resistor[] = { 100, 100, 100 }; -/* - * get processor id using cpuid eax=1 - * return value will be in EAX register - */ -static uint32_t get_cpuid(void) -{ - struct cpuid_result cpuidr; - - cpuidr = cpuid(1); - - return cpuidr.eax; -} - void __weak variant_memory_params(struct lpddr4_config *mem_config) { /* Rcomp target */ @@ -61,7 +49,7 @@ mem_config->dqs_map_size = sizeof(dqs_map); mem_config->rcomp_resistor = rcomp_resistor; mem_config->rcomp_resistor_size = sizeof(rcomp_resistor); - if (get_cpuid() == CPUID_ICELAKE_A0) { + if (cpu_get_cpuid() == CPUID_ICELAKE_A0) { mem_config->rcomp_target = rcomp_target_es0; mem_config->rcomp_target_size = sizeof(rcomp_target_es0); } else { diff --git a/src/mainboard/intel/icelake_rvp/spd/spd_util.c b/src/mainboard/intel/icelake_rvp/spd/spd_util.c index 63b39fd..0a0dffe 100644 --- a/src/mainboard/intel/icelake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/icelake_rvp/spd/spd_util.c @@ -15,6 +15,7 @@ #include <arch/byteorder.h> #include <arch/cpu.h> #include <console/console.h> +#include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> #include <stdint.h> #include <string.h> @@ -111,19 +112,6 @@ memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); } -/* - * get processor id using cpuid eax=1 - * return value will be in EAX register - */ -static uint32_t get_cpuid(void) -{ - struct cpuid_result cpuidr; - - cpuidr = cpuid(1); - - return cpuidr.eax; -} - void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) { /* Rcomp target */ @@ -142,7 +130,7 @@ case icl_y_lpddr4: case icl_u_lpddr4: case icl_u_lpddr4_type_3: - if (get_cpuid() == CPUID_ICELAKE_A0) + if (cpu_get_cpuid() == CPUID_ICELAKE_A0) memcpy(rcomp_strength_ptr, RcompTarget_LPDDR4_Ax, sizeof(RcompTarget_LPDDR4_Ax)); else -- To view, visit https://review.coreboot.org/c/coreboot/+/30124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia12d95d911dd6ee60a3a35937264fef668ad9e35 Gerrit-Change-Number: 30124 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: soc/intel/{skl, cnl, icl}: Move cpuid(1) function into soc/intel/common...
by Subrata Banik (Code Review) 10 Dec '18

10 Dec '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30123 Change subject: soc/intel/{skl,cnl,icl}: Move cpuid(1) function into soc/intel/common/ code ...................................................................... soc/intel/{skl,cnl,icl}: Move cpuid(1) function into soc/intel/common/ code This patch replaces all cpuid(1) references from soc/intel/{skl,cnl,icl} with intel cpu common code library functions. 1. cpu_get_cpuid() -> to get processor id (from cpuid.eax) 2. cpu_get_feature_flag -> to get processor feature flag (from cpuid.ecx) Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/common/block/vmx/vmx.c M src/soc/intel/icelake/bootblock/report_platform.c M src/soc/intel/icelake/cpu.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/cpu.c 9 files changed, 77 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/30123/1 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 17bcce9..54de85d 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -20,6 +20,7 @@ #include <cpu/x86/msr.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> #include <soc/bootblock.h> #include <soc/pch.h> @@ -96,7 +97,7 @@ static void report_cpu_info(void) { struct cpuid_result cpuidr; - u32 i, index; + u32 i, index, cpu_id, cpu_feature_flag; char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ int vt, txt, aes; msr_t microcode_ver; @@ -128,12 +129,12 @@ microcode_ver.lo = 0; microcode_ver.hi = 0; wrmsr(BIOS_SIGN_ID, microcode_ver); - cpuidr = cpuid(1); + cpu_id = cpu_get_cpuid(); microcode_ver = rdmsr(BIOS_SIGN_ID); /* Look for string to match the name */ for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { - if (cpu_table[i].cpuid == cpuidr.eax) { + if (cpu_table[i].cpuid == cpu_id) { cpu_type = cpu_table[i].name; break; } @@ -141,11 +142,12 @@ printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", - cpuidr.eax, cpu_type, microcode_ver.hi); + cpu_id, cpu_type, microcode_ver.hi); - aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; - txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; - vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; + cpu_feature_flag = cpu_get_feature_flag(); + aes = (cpu_feature_flag & (1 << 25)) ? 1 : 0; + txt = (cpu_feature_flag & (1 << 6)) ? 1 : 0; + vt = (cpu_feature_flag & (1 << 5)) ? 1 : 0; printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", mode[aes], mode[txt], mode[vt]); diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index ccd1dea..d651985 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -104,12 +104,12 @@ static void configure_dca_cap(void) { - struct cpuid_result cpuid_regs; + uint32_t feature_flag; msr_t msr; /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - cpuid_regs = cpuid(1); - if (cpuid_regs.ecx & (1 << 18)) { + feature_flag = cpu_get_feature_flag(); + if (feature_flag & (1 << 18)) { msr = rdmsr(IA32_PLATFORM_DCA_CAP); msr.lo |= 1; wrmsr(IA32_PLATFORM_DCA_CAP, msr); diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index d18b50c..af7e7aa 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -335,3 +335,29 @@ (msr_t) {.lo = 0xffffffff, .hi = 0xffffffff}); } } + +/* + * Get processor id using cpuid eax=1 + * return value will be in EAX register + */ +uint32_t cpu_get_cpuid(void) +{ + struct cpuid_result cpuidr; + + cpuidr = cpuid(1); + + return cpuidr.eax; +} + +/* + * Get processor feature flag using cpuid eax=1 + * return value will be in ECX register + */ +uint32_t cpu_get_feature_flag(void) +{ + struct cpuid_result cpuidr; + + cpuidr = cpuid(1); + + return cpuidr.ecx; +} diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 5cea96e..51d499e 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -167,4 +167,16 @@ /* Configure Machine Check Architecture support */ void mca_configure(void *unused); +/* + * Get processor id using cpuid eax=1 + * return value will be in EAX register + */ +uint32_t cpu_get_cpuid(void); + +/* + * Get processor feature flag using cpuid eax=1 + * return value will be in ECX register + */ +uint32_t cpu_get_feature_flag(void); + #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ diff --git a/src/soc/intel/common/block/vmx/vmx.c b/src/soc/intel/common/block/vmx/vmx.c index 2cffdab..4ef9359 100644 --- a/src/soc/intel/common/block/vmx/vmx.c +++ b/src/soc/intel/common/block/vmx/vmx.c @@ -13,6 +13,7 @@ #include <console/console.h> #include <cpu/x86/msr.h> +#include <intelblocks/cpulib.h> #include <intelblocks/msr.h> #include <intelblocks/vmx.h> #include <soc/cpu.h> @@ -46,11 +47,11 @@ void vmx_configure(void *unused) { msr_t msr; - struct cpuid_result regs; + uint32_t feature_flag; - regs = cpuid(1); + feature_flag = cpu_get_feature_flag(); - if (!soc_vmx_enabled() || !(regs.ecx & CPUID_VMX)) { + if (!soc_vmx_enabled() || !(feature_flag & CPUID_VMX)) { printk(BIOS_ERR, "VMX: pre-conditions not met\n"); return; } diff --git a/src/soc/intel/icelake/bootblock/report_platform.c b/src/soc/intel/icelake/bootblock/report_platform.c index a5dcd77..07a45c1 100644 --- a/src/soc/intel/icelake/bootblock/report_platform.c +++ b/src/soc/intel/icelake/bootblock/report_platform.c @@ -19,6 +19,7 @@ #include <cpu/x86/msr.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> #include <soc/bootblock.h> #include <soc/pch.h> @@ -92,7 +93,7 @@ static void report_cpu_info(void) { struct cpuid_result cpuidr; - u32 i, index; + u32 i, index, cpu_id, cpu_feature_flag; char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ int vt, txt, aes; msr_t microcode_ver; @@ -124,12 +125,12 @@ microcode_ver.lo = 0; microcode_ver.hi = 0; wrmsr(BIOS_SIGN_ID, microcode_ver); - cpuidr = cpuid(1); + cpu_id = cpu_get_cpuid(); microcode_ver = rdmsr(BIOS_SIGN_ID); /* Look for string to match the name */ for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { - if (cpu_table[i].cpuid == cpuidr.eax) { + if (cpu_table[i].cpuid == cpu_id) { cpu_type = cpu_table[i].name; break; } @@ -137,11 +138,12 @@ printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", - cpuidr.eax, cpu_type, microcode_ver.hi); + cpu_id, cpu_type, microcode_ver.hi); - aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; - txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; - vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; + cpu_feature_flag = cpu_get_feature_flag(); + aes = (cpu_feature_flag & (1 << 25)) ? 1 : 0; + txt = (cpu_feature_flag & (1 << 6)) ? 1 : 0; + vt = (cpu_feature_flag & (1 << 5)) ? 1 : 0; printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", mode[aes], mode[txt], mode[vt]); diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index bfe9f7be..26b5414 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -105,12 +105,12 @@ static void configure_dca_cap(void) { - struct cpuid_result cpuid_regs; + uint32_t feature_flag; msr_t msr; /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - cpuid_regs = cpuid(1); - if (cpuid_regs.ecx & (1 << 18)) { + feature_flag = cpu_get_feature_flag(); + if (feature_flag & (1 << 18)) { msr = rdmsr(IA32_PLATFORM_DCA_CAP); msr.lo |= 1; wrmsr(IA32_PLATFORM_DCA_CAP, msr); diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 7dbd371..5b34a16 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -20,6 +20,7 @@ #include <cpu/x86/msr.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> #include <soc/bootblock.h> #include <soc/cpu.h> @@ -121,7 +122,7 @@ static void report_cpu_info(void) { struct cpuid_result cpuidr; - u32 i, index; + u32 i, index, cpu_id, cpu_feature_flag; char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ int vt, txt, aes; msr_t microcode_ver; @@ -149,12 +150,12 @@ microcode_ver.lo = 0; microcode_ver.hi = 0; wrmsr(IA32_BIOS_SIGN_ID, microcode_ver); - cpuidr = cpuid(1); + cpu_id = cpu_get_cpuid(); microcode_ver = rdmsr(IA32_BIOS_SIGN_ID); /* Look for string to match the name */ for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { - if (cpu_table[i].cpuid == cpuidr.eax) { + if (cpu_table[i].cpuid == cpu_id) { cpu_type = cpu_table[i].name; break; } @@ -164,9 +165,10 @@ printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", cpuidr.eax, cpu_type, microcode_ver.hi); - aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; - txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; - vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; + cpu_feature_flag = cpu_get_feature_flag(); + aes = (cpu_feature_flag & (1 << 25)) ? 1 : 0; + txt = (cpu_feature_flag & (1 << 6)) ? 1 : 0; + vt = (cpu_feature_flag & (1 << 5)) ? 1 : 0; printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", mode[aes], mode[txt], mode[vt]); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 9e4bbe8..2a9a446 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -333,12 +333,12 @@ static void configure_dca_cap(void) { - struct cpuid_result cpuid_regs; + uint32_t feature_flag; msr_t msr; /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - cpuid_regs = cpuid(1); - if (cpuid_regs.ecx & (1 << 18)) { + feature_flag = cpu_get_feature_flag(); + if (feature_flag & (1 << 18)) { msr = rdmsr(IA32_PLATFORM_DCA_CAP); msr.lo |= 1; wrmsr(IA32_PLATFORM_DCA_CAP, msr); -- To view, visit https://review.coreboot.org/c/coreboot/+/30123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50 Gerrit-Change-Number: 30123 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mb/google/poppy/variants/nami: Modify SPD for hynix memory part
by Ren Kuo (Code Review) 10 Dec '18

10 Dec '18

Ren Kuo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30076 ) Change subject: mb/google/poppy/variants/nami: Modify SPD for hynix memory part ...................................................................... Patch Set 1: > Patch Set 1: > > > Patch Set 1: > > > > (1 comment) > > the previous part with"A" was submit by me. > now i correct the P/N to"4". > but I not sure it will be use by other projects shelley, We're going to run the EVT build. Could you confirm the memory part can be replaced? -- To view, visit https://review.coreboot.org/c/coreboot/+/30076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c33343eb1269919fba324333897805da1d1ff9b Gerrit-Change-Number: 30076 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Vincent Wang <vwang(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 10 Dec 2018 02:01:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mb/google/sarien: Update GPIOs for next build
by Furquan Shaikh (Code Review) 09 Dec '18

09 Dec '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30062 ) Change subject: mb/google/sarien: Update GPIOs for next build ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32d84f3010cb4d3968370a03f7e191b1710a50e8 Gerrit-Change-Number: 30062 Gerrit-PatchSet: 4 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 09 Dec 2018 22:28:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mb/google/sarien: Setup GPIOs again after FSP-S
by Furquan Shaikh (Code Review) 09 Dec '18

09 Dec '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30113 ) Change subject: mb/google/sarien: Setup GPIOs again after FSP-S ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19550c4347cf65d409de6a8638619270372c4d0a Gerrit-Change-Number: 30113 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 09 Dec 2018 22:26:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: util/board_status/board_status.sh: use sudo for local dmesg too
by Michael Bacarella (Code Review) 09 Dec '18

09 Dec '18

Michael Bacarella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30121 Change subject: util/board_status/board_status.sh: use sudo for local dmesg too ...................................................................... util/board_status/board_status.sh: use sudo for local dmesg too Some systems have started locking down unprivileged user access to dmesg. Signed-off-by: Michael Bacarella <michael.bacarella(a)gmail.com> Change-Id: I60061832e88fc6c549f6d5d7de276da650c4ca60 --- M util/board_status/board_status.sh 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/30121/1 diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index bba3d1f..8af3dd8 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -403,7 +403,7 @@ cmd_nonfatal $LOCAL "$cbmem_cmd -t" "${tmpdir}/${results}/coreboot_timestamps.txt" echo "Getting local dmesg" - cmd $LOCAL dmesg "${tmpdir}/${results}/kernel_log.txt" + cmd $LOCAL sudo dmesg "${tmpdir}/${results}/kernel_log.txt" fi # -- To view, visit https://review.coreboot.org/c/coreboot/+/30121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60061832e88fc6c549f6d5d7de276da650c4ca60 Gerrit-Change-Number: 30121 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Bacarella <michael.bacarella(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: src: Remove useless include <device/pci_ids.h>
by HAOUAS Elyes (Code Review) 09 Dec '18

09 Dec '18

Hello Patrick Rudolph, Piotr Król, build bot (Jenkins), Alexander Couzens, Werner Zeh, Vanessa Eusebio, Huang Jin, York Yang, Philipp Deppenwiese, Damien Zammit, David Guckian, Michał Żygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30120 to look at the new patch set (#2). Change subject: src: Remove useless include <device/pci_ids.h> ...................................................................... src: Remove useless include <device/pci_ids.h> Change-Id: Ia640131479d4221ccd84613033f28de3932b8bff Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/family_10h-family_15h/monotonic_timer.c M src/cpu/amd/family_10h-family_15h/powernow_acpi.c M src/device/azalia_device.c M src/device/oprom/realmode/x86_interrupts.c M src/device/pci_ops.c M src/device/pci_ops_mmconf.c M src/device/pcix_device.c M src/drivers/aspeed/common/aspeed_coreboot.h M src/drivers/sil/3114/sil_sata.c M src/drivers/xgi/common/xgi_coreboot.h M src/mainboard/adi/rcc-dff/acpi_tables.c M src/mainboard/advansus/a785e-i/acpi_tables.c M src/mainboard/advansus/a785e-i/get_bus_conf.c M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/bettong/acpi_tables.c M src/mainboard/amd/bimini_fam10/acpi_tables.c M src/mainboard/amd/bimini_fam10/get_bus_conf.c M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/amd/db-ft3b-lc/acpi_tables.c M src/mainboard/amd/db-ft3b-lc/romstage.c M src/mainboard/amd/inagua/acpi_tables.c M src/mainboard/amd/lamar/acpi_tables.c M src/mainboard/amd/lamar/romstage.c M src/mainboard/amd/mahogany_fam10/acpi_tables.c M src/mainboard/amd/mahogany_fam10/get_bus_conf.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/olivehill/acpi_tables.c M src/mainboard/amd/olivehill/romstage.c M src/mainboard/amd/olivehillplus/acpi_tables.c M src/mainboard/amd/olivehillplus/romstage.c M src/mainboard/amd/parmer/acpi_tables.c M src/mainboard/amd/persimmon/acpi_tables.c M src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c M src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c M src/mainboard/amd/south_station/acpi_tables.c M src/mainboard/amd/thatcher/acpi_tables.c M src/mainboard/amd/thatcher/romstage.c M src/mainboard/amd/tilapia_fam10/acpi_tables.c M src/mainboard/amd/tilapia_fam10/get_bus_conf.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/amd/torpedo/acpi_tables.c M src/mainboard/amd/union_station/acpi_tables.c M src/mainboard/aopen/dxplplusu/acpi_tables.c M src/mainboard/apple/macbook21/mainboard.c M src/mainboard/asrock/e350m1/acpi_tables.c M src/mainboard/asrock/imb-a180/acpi_tables.c M src/mainboard/asrock/imb-a180/romstage.c M src/mainboard/asus/am1i-a/acpi_tables.c M src/mainboard/asus/f2a85-m/acpi_tables.c M src/mainboard/asus/kcma-d8/acpi_tables.c M src/mainboard/asus/kcma-d8/get_bus_conf.c M src/mainboard/asus/kcma-d8/romstage.c M src/mainboard/asus/kfsn4-dre/acpi_tables.c M src/mainboard/asus/kfsn4-dre/get_bus_conf.c M src/mainboard/asus/kgpe-d16/acpi_tables.c M src/mainboard/asus/kgpe-d16/get_bus_conf.c M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/asus/m4a78-em/acpi_tables.c M src/mainboard/asus/m4a78-em/get_bus_conf.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/acpi_tables.c M src/mainboard/asus/m4a785-m/get_bus_conf.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/acpi_tables.c M src/mainboard/asus/m5a88-v/get_bus_conf.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/avalue/eax-785e/acpi_tables.c M src/mainboard/avalue/eax-785e/get_bus_conf.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/bap/ode_e20XX/acpi_tables.c M src/mainboard/bap/ode_e21XX/acpi_tables.c M src/mainboard/bap/ode_e21XX/romstage.c M src/mainboard/biostar/a68n_5200/acpi_tables.c M src/mainboard/biostar/a68n_5200/romstage.c M src/mainboard/biostar/am1ml/acpi_tables.c M src/mainboard/elmex/pcm205400/acpi_tables.c M src/mainboard/emulation/qemu-q35/acpi_tables.c M src/mainboard/emulation/qemu-q35/mainboard.c M src/mainboard/esd/atom15/acpi_tables.c M src/mainboard/getac/p470/acpi_tables.c M src/mainboard/gigabyte/ma785gm/acpi_tables.c M src/mainboard/gigabyte/ma785gm/get_bus_conf.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/acpi_tables.c M src/mainboard/gigabyte/ma785gmt/get_bus_conf.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/acpi_tables.c M src/mainboard/gigabyte/ma78gm/get_bus_conf.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/gizmosphere/gizmo/acpi_tables.c M src/mainboard/gizmosphere/gizmo2/acpi_tables.c M src/mainboard/google/beltino/acpi_tables.c M src/mainboard/google/jecht/acpi_tables.c M src/mainboard/google/parrot/acpi_tables.c M src/mainboard/google/rambi/acpi_tables.c M src/mainboard/google/slippy/acpi_tables.c M src/mainboard/google/stout/acpi_tables.c M src/mainboard/hp/abm/acpi_tables.c M src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c M src/mainboard/iei/kino-780am2-fam10/acpi_tables.c M src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/intel/baskingridge/acpi_tables.c M src/mainboard/intel/bayleybay_fsp/acpi_tables.c M src/mainboard/intel/emeraldlake2/acpi_tables.c M src/mainboard/intel/harcuvar/acpi_tables.c M src/mainboard/intel/littleplains/acpi_tables.c M src/mainboard/intel/minnowmax/acpi_tables.c M src/mainboard/intel/mohonpeak/acpi_tables.c M src/mainboard/intel/strago/acpi_tables.c M src/mainboard/intel/wtm2/acpi_tables.c M src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c M src/mainboard/jetway/pa78vm5/acpi_tables.c M src/mainboard/jetway/pa78vm5/get_bus_conf.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/lenovo/g505s/acpi_tables.c M src/mainboard/lenovo/t400/acpi_tables.c M src/mainboard/lenovo/x200/acpi_tables.c M src/mainboard/lippert/frontrunner-af/acpi_tables.c M src/mainboard/lippert/toucan-af/acpi_tables.c M src/mainboard/msi/ms7721/acpi_tables.c M src/mainboard/msi/ms9652_fam10/acpi_tables.c M src/mainboard/msi/ms9652_fam10/get_bus_conf.c M src/mainboard/packardbell/ms2290/mainboard.c M src/mainboard/pcengines/apu1/acpi_tables.c M src/mainboard/pcengines/apu2/acpi_tables.c M src/mainboard/pcengines/apu2/romstage.c M src/mainboard/roda/rk9/acpi_tables.c M src/mainboard/samsung/lumpy/acpi_tables.c M src/mainboard/samsung/stumpy/acpi_tables.c M src/mainboard/scaleway/tagada/acpi_tables.c M src/mainboard/siemens/mc_tcu3/acpi_tables.c M src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c M src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c M src/mainboard/supermicro/h8scm_fam10/acpi_tables.c M src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/tyan/s2912_fam10/get_bus_conf.c M src/mainboard/via/epia-m850/romstage.c M src/northbridge/amd/amdfam10/get_pci1234.c M src/northbridge/amd/amdht/comlib.c M src/northbridge/amd/amdht/h3finit.c M src/northbridge/amd/amdht/h3ncmn.c M src/northbridge/amd/lx/northbridgeinit.c M src/northbridge/intel/gm45/acpi.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/i945/acpi.c M src/northbridge/intel/nehalem/acpi.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/acpi.c M src/northbridge/intel/sandybridge/common.c M src/northbridge/intel/x4x/acpi.c M src/northbridge/intel/x4x/northbridge.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/intel/apollolake/lpc.c M src/soc/intel/baytrail/scc.c M src/soc/intel/baytrail/spi.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/scc.c M src/soc/intel/braswell/spi.c M src/soc/intel/broadwell/me_status.c M src/soc/intel/broadwell/romstage/smbus.c M src/soc/intel/broadwell/romstage/spi.c M src/soc/intel/broadwell/smbus_common.c M src/soc/intel/broadwell/spi.c M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/include/soc/i2c.h M src/soc/intel/fsp_baytrail/spi.c M src/soc/intel/fsp_broadwell_de/smbus_common.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/lpc.c M src/soc/intel/quark/i2c.c M src/soc/intel/quark/romstage/pcie.c M src/soc/intel/skylake/lpc.c M src/soc/intel/skylake/me.c M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/agesa/hudson/hudson.h M src/southbridge/amd/amd8111/early_ctrl.c M src/southbridge/amd/pi/hudson/hudson.h M src/southbridge/amd/rs780/cmn.c M src/southbridge/amd/rs780/pcie.c M src/southbridge/amd/rs780/rs780.c M src/southbridge/amd/rs780/rs780.h M src/southbridge/amd/sb700/bootblock.c M src/southbridge/amd/sb700/sb700.h M src/southbridge/amd/sb800/bootblock.c M src/southbridge/amd/sb800/sb800.h M src/southbridge/amd/sr5650/pcie.c M src/southbridge/amd/sr5650/sr5650.h M src/southbridge/intel/bd82x6x/early_me.c M src/southbridge/intel/bd82x6x/early_me_mrc.c M src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/bd82x6x/early_spi.c M src/southbridge/intel/bd82x6x/early_usb.c M src/southbridge/intel/bd82x6x/early_usb_mrc.c M src/southbridge/intel/common/spi.c M src/southbridge/intel/fsp_rangeley/early_smbus.c M src/southbridge/intel/fsp_rangeley/early_spi.c M src/southbridge/intel/fsp_rangeley/early_usb.c M src/southbridge/intel/i82371eb/acpi_tables.c M src/southbridge/intel/i82801dx/i82801dx.c M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/ibexpeak/madt.c M src/southbridge/intel/lynxpoint/early_me.c M src/southbridge/intel/lynxpoint/early_smbus.c M src/southbridge/intel/lynxpoint/early_spi.c M src/southbridge/intel/lynxpoint/early_usb.c M src/southbridge/ti/pci7420/cardbus.c M src/southbridge/ti/pci7420/firewire.c M src/southbridge/ti/pcixx12/pcixx12.c 219 files changed, 2 insertions(+), 219 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/30120/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia640131479d4221ccd84613033f28de3932b8bff Gerrit-Change-Number: 30120 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2018