coreboot-gerrit December 2018

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: libpayload: Don't try to use invalid row count
by Patrick Georgi (Code Review) 09 Dec '18

09 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30092 ) Change subject: libpayload: Don't try to use invalid row count ...................................................................... libpayload: Don't try to use invalid row count console->scroll_up() was hanging when console->rows is 0. This was happening on delan if no screen was attached. If there are no rows, just return. BUG=b:119234919 TEST=Boot delan with no flat panel. System boots to OS Change-Id: Ib022d3c6fc0c9cf360809dca28761a50c787304a Signed-off-by: Martin Roth <martinroth(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/30092 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M payloads/libpayload/drivers/video/video.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/payloads/libpayload/drivers/video/video.c b/payloads/libpayload/drivers/video/video.c index 71140f0..b932a63 100644 --- a/payloads/libpayload/drivers/video/video.c +++ b/payloads/libpayload/drivers/video/video.c @@ -87,6 +87,9 @@ cursory++; } + if (console->rows <= 0) + return; + while(cursory >= console->rows) { console->scroll_up(); cursory--; -- To view, visit https://review.coreboot.org/c/coreboot/+/30092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib022d3c6fc0c9cf360809dca28761a50c787304a Gerrit-Change-Number: 30092 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/sarien: Enable LAN clock source usage
by Patrick Georgi (Code Review) 09 Dec '18

09 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30100 ) Change subject: mb/google/sarien: Enable LAN clock source usage ...................................................................... mb/google/sarien: Enable LAN clock source usage FSP defined a special clock source usage 0x70 for PCH LAN device, update that to google sarien platform. BUG=b:120003760 TEST=Boot up into OS, ethernet able to be listed in ifconfig. Change-Id: I9f945be4f0ce15470ab53f44e60143f3fd0fddf8 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Reviewed-on: https://review.coreboot.org/c/30100 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Subrata Banik: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 93e0af9..fccec9f 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -80,7 +80,7 @@ # PCIe port 9 for LAN register "PcieRpEnable[8]" = "1" - register "PcieClkSrcUsage[0]" = "8" + register "PcieClkSrcUsage[0]" = "PCIE_CLK_LAN" register "PcieClkSrcClkReq[0]" = "0" # PCIe port 10 for M.2 2230 WLAN diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index d25e725..49200ad 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -85,7 +85,7 @@ # PCIe port 9 for LAN register "PcieRpEnable[8]" = "1" - register "PcieClkSrcUsage[3]" = "8" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN" register "PcieClkSrcClkReq[3]" = "3" # PCIe port 10 for M.2 2230 WLAN -- To view, visit https://review.coreboot.org/c/coreboot/+/30100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f945be4f0ce15470ab53f44e60143f3fd0fddf8 Gerrit-Change-Number: 30100 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: Documentation/CoC: make clearer it's also for real world events
by Angel Pons (Code Review) 09 Dec '18

09 Dec '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30104 ) Change subject: Documentation/CoC: make clearer it's also for real world events ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/30104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23883cfd8200496f4281d73b6e75fac0d3448a3c Gerrit-Change-Number: 30104 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 09 Dec 2018 09:01:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/lynxpoint: Handle H81 only having 6 PCIe root ports
by Tristan Corrick (Code Review) 09 Dec '18

09 Dec '18

Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30077 ) Change subject: sb/intel/lynxpoint: Handle H81 only having 6 PCIe root ports ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/30077/1/src/southbridge/intel/lynxpoint/pci… File src/southbridge/intel/lynxpoint/pcie.c: https://review.coreboot.org/#/c/30077/1/src/southbridge/intel/lynxpoint/pci… PS1, Line 209: !rpc.ports[6]->enabl > align with opening ( Done -- To view, visit https://review.coreboot.org/c/coreboot/+/30077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3ce217e8a4f4ea4e111e4525b03dbbfc63f92b0 Gerrit-Change-Number: 30077 Gerrit-PatchSet: 2 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 09 Dec 2018 01:16:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/lynxpoint: Handle H81 only having 6 PCIe root ports
by Tristan Corrick (Code Review) 09 Dec '18

09 Dec '18

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30077 to look at the new patch set (#2). Change subject: sb/intel/lynxpoint: Handle H81 only having 6 PCIe root ports ...................................................................... sb/intel/lynxpoint: Handle H81 only having 6 PCIe root ports The H81 chipset is the only non-LP Lynx Point chipset with 6 PCIe root ports, all others have 8 [1]. The existing PCIe code assumed that all non-LP chipsets had 8 root ports, which meant that port 6 would not be considered the last root port on H81, so `root_port_commit_config()` would not run. Ultimately, while PCIe still worked on H81, all the root ports would remain enabled, even if disabled in the devicetree. Also, remove `PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_{MIN,MAX}`, as they are unused, and the MAX constant is incorrect. Interestingly, this fixes an issue where GRUB is unable to halt the system. Tested on an ASRock H81M-HDS. The root ports disabled in the devicetree do indeed end up disabled. [1] Intel® 8 Series/C220 Series Chipset Family Platform Controller Hub (PCH) Datasheet, revision 003, document number 328904. Change-Id: If3ce217e8a4f4ea4e111e4525b03dbbfc63f92b0 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/include/device/pci_ids.h M src/mainboard/asrock/h81m-hds/devicetree.cb M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/pcie.c 5 files changed, 38 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/30077/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3ce217e8a4f4ea4e111e4525b03dbbfc63f92b0 Gerrit-Change-Number: 30077 Gerrit-PatchSet: 2 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: sb/intel/lynxpoint/pcie.c: Add more checks for NULL pointers
by Tristan Corrick (Code Review) 09 Dec '18

09 Dec '18

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30079 to look at the new patch set (#2). Change subject: sb/intel/lynxpoint/pcie.c: Add more checks for NULL pointers ...................................................................... sb/intel/lynxpoint/pcie.c: Add more checks for NULL pointers If PCIe root port `n` is disabled, then `rpc.ports[n - 1]` remains NULL. The existing Lynx Point systems probably don't end up dereferencing NULL pointers this way. However, it might occur on a system using Flexible I/O to remap PCIe root ports to other functions. Tested on an ASRock H81M-HDS and an Acer C720 (Google Peppy). No issues presented themselves. Change-Id: I2c22fa36217766c2c4d6e8046f99989063066b16 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/southbridge/intel/lynxpoint/pcie.c 1 file changed, 29 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/30079/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c22fa36217766c2c4d6e8046f99989063066b16 Gerrit-Change-Number: 30079 Gerrit-PatchSet: 2 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/sarien: Setup GPIOs again after FSP-S
by Lijian Zhao (Code Review) 09 Dec '18

09 Dec '18

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30113 ) Change subject: mb/google/sarien: Setup GPIOs again after FSP-S ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/30113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19550c4347cf65d409de6a8638619270372c4d0a Gerrit-Change-Number: 30113 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 09 Dec 2018 00:59:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Setup GPIOs again after FSP-S
by Lijian Zhao (Code Review) 09 Dec '18

09 Dec '18

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30113 ) Change subject: mb/google/sarien: Setup GPIOs again after FSP-S ...................................................................... Patch Set 2: > Patch Set 2: > > FWIW I am not sure what version "gold" is, it does not seem to map to an actual number. https://github.com/IntelFsp/FSP/blob/master/CoffeeLakeFspBinPkg/Docs/Coffee… Release notes still call it Gold release. -- To view, visit https://review.coreboot.org/c/coreboot/+/30113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19550c4347cf65d409de6a8638619270372c4d0a Gerrit-Change-Number: 30113 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 09 Dec 2018 00:59:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Setup GPIOs again after FSP-S
by Duncan Laurie (Code Review) 08 Dec '18

08 Dec '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30113 ) Change subject: mb/google/sarien: Setup GPIOs again after FSP-S ...................................................................... Patch Set 2: FWIW I am not sure what version "gold" is, it does not seem to map to an actual number. -- To view, visit https://review.coreboot.org/c/coreboot/+/30113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19550c4347cf65d409de6a8638619270372c4d0a Gerrit-Change-Number: 30113 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 08 Dec 2018 21:26:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Setup GPIOs again after FSP-S
by Duncan Laurie (Code Review) 08 Dec '18

08 Dec '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30113 ) Change subject: mb/google/sarien: Setup GPIOs again after FSP-S ...................................................................... Patch Set 2: > Patch Set 1: > > Please also mention the FSP version that is broken. > It would also be nice to have it in the SOC specific documentation until fixed. > Do you have a link to a public issue tracker ? I filed a public bug at crbug.com/913216 and added details to the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/30113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19550c4347cf65d409de6a8638619270372c4d0a Gerrit-Change-Number: 30113 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 08 Dec 2018 21:25:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2018