coreboot-gerrit December 2018

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Change in ...coreboot[master]: Work in progress: Early eMMC phase 1
by Richard Spiegel (Code Review) 07 Dec '18

07 Dec '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30109 Change subject: Work in progress: Early eMMC phase 1 ...................................................................... Work in progress: Early eMMC phase 1 Global objective: Early ready of eMMC by sending CMD0 and CMD1. This phase objective: Create bh720 driver to be used by phase 2. BUG=b:118680303 TEST= Change-Id: Ifd2a307ead37c62abca811654873c43c02ac2a4a Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- A src/drivers/emmc/README A src/drivers/emmc/bh7720/Kconfig A src/drivers/emmc/bh7720/Makefile.inc A src/drivers/emmc/bh7720/bh720.c A src/include/device/emmc/bh720.h A src/include/device/emmc/emmc.h 6 files changed, 281 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/30109/1 diff --git a/src/drivers/emmc/README b/src/drivers/emmc/README new file mode 100644 index 0000000..b95b477 --- /dev/null +++ b/src/drivers/emmc/README @@ -0,0 +1,51 @@ +/* + * Documentation for eMMC host drivers + * + * This file is part of the coreboot project. + * + * Copyright 2018 Silverback Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +This folder has drivers for several eMMC hosts. There's a minimum set of +commands these drivers must implement, though it can implement more: +emmc_driver_init -> initializes all required registers of a particular host, + so that commands can be send. +emmc_send_command -> the host sends a command to the eMMC card, status is + returned. +emmc_get_ocr -> The OCR value is read. + +Commands description: +int emmc_driver_init(void *params); +Some parameters are always the same, so they don't need to be send for code +execution. Only parameters that are board dependent plus the base address +should be send. +The input is a void pointer to parameters, which is internally converted to +a pointer to structure, defined in the chip specific header file. Inside +this structure, the first 2 elements are common: (uint8_t) total and +(uint16_t/uint32_t) base_address. The remaining are chip specific,. +The return can be 0 if success, or a negative number if there's a problem. + +uint32_t emmc_send_command(uint8_t command, uint32_t argument); +Using the base address from emmc_driver_init, it sends commands to the eMMC +and return the host status at the moment the command was issued. This is only +for 48-bits commands (start, stop, direction,CRC77, command and argument). + +uint32_t emmc_get_ocr(uint32_t base_address); +This function can be called before or after PCI enumeration, as it receives +the base address to use. If the base address is IO, the upper word should +be 0. It assumes that CMD1 was already issued, and returns the OCR received +from the eMMC. + +Generally speaking, emmc_driver_init must be used at romstage, while the +other 2 can be romstage or ramstage, though if PCI access is needed by the +particular chip to execute them, then they must be either romstage or have +a device declared to be used in ramstage. diff --git a/src/drivers/emmc/bh7720/Kconfig b/src/drivers/emmc/bh7720/Kconfig new file mode 100644 index 0000000..27b5c80 --- /dev/null +++ b/src/drivers/emmc/bh7720/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_EMMC_BH720 + bool diff --git a/src/drivers/emmc/bh7720/Makefile.inc b/src/drivers/emmc/bh7720/Makefile.inc new file mode 100644 index 0000000..e282a67 --- /dev/null +++ b/src/drivers/emmc/bh7720/Makefile.inc @@ -0,0 +1,2 @@ +romstage-$(CONFIG_DRIVERS_EMMC_BH720) += bh720.c +ramstage-$(CONFIG_DRIVERS_EMMC_BH720) += bh720.c diff --git a/src/drivers/emmc/bh7720/bh720.c b/src/drivers/emmc/bh7720/bh720.c new file mode 100644 index 0000000..ebd48d8 --- /dev/null +++ b/src/drivers/emmc/bh7720/bh720.c @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Silverback Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <rules.h> +#include <device/pci_def.h> +#include <device/emmc/emmc.h> +#include <device/emmc/bh720.h> + +static uint8_t *base_ptr; +static boolean flag = false; + +static void pci_set8(uint32_t dev, uint8_t reg, uint8_t bits) +{ + uint8_t value; + value = pci_read_config8(dev, reg); + value |= bits; + pci_write_config8(dev, reg, value); +} + +static void pci_clear8(uint32_t dev, uint8_t reg, uint8_t bits) +{ + uint8_t value, mask; + mask = ~bits; + value = pci_read_config8(dev, reg); + value &= mask; + pci_write_config8(dev, reg, value); +} + +static void pci_set32(uint32_t dev, uint8_t reg, uint32_t bits) +{ + uint32_t value; + value = pci_read_config32(dev, reg); + value |= bits; + pci_write_config32(dev, reg, value); +} + +static void pci_clear32(uint32_t dev, uint8_t reg, uint32_t bits) +{ + uint32_t value, mask; + mask = ~bits; + value = pci_read_config32(dev, reg); + value &= mask; + pci_write_config32(dev, reg, value); +} + +static void program_base(uint32_t dev, uint32_t base) +{ +} + +static void program_id(uint32_t dev, uint32_t id) +{ +} + +static uint32_t read_base(uint32_t dev, uint32_t id) +{ + uint32_t bridge_dev; + /* + * Read bridge, check if programmed. If programmed, generate + * bridge_dev and read/return base address. + */ + + /* + * Program bridge and base address. If (id) program_id. + * Set flag to indicate need of desprogramming bridge and BAR0. + */ +} + +int emmc_driver_init(void *params) +{ + bh720_params *param = (bh720_params *)params; + uint32_t temp; + uint32_t device = param->pci_dev; + uint32_t subsys_id = param->subsys_vend_dev_id; + uint8_t total = param->total + uint8_t mode = DEFAUT_MODE; + + base_ptr = (uint8_t *)param->base_address; + if (total > 4) + mode = param->mode; + if ((total == 0) || (total == 2)) + return EMMC_STATUS_INVALID_PARAM; + if (total == 1) { + temp = read_base(device, subsys_id); + param = (bh720_params *)temp; + if(flag) { + } + return EMMC_STATUS_SUCCESS; + } + if ((total > 3) { + if (subsys_id && (mode & MODE_VEND_DEV)) + program_id(device, subsys_id); +#if defined(__SIMPLE_DEVICE__) + if (mode > MODE_VEND_DEV) + return EMMC_STATUS_INVALID_STAGE; +#endif + if (mode & MODE_DIS_SD) { + } + if (mode & MODE_VCCQ_18) { + } + if (mode & MODE_POWER_SAVE) { + } + if (mode & MODE_L1_TIMER) { + } + if (mode & MODE_IDDQ) { + } + if (mode & MODE_TUNNING) { + } + if (mode & MODE_DLL_CLK_PHASE) { + } + return EMMC_STATUS_SUCCESS; +} + +uint32_t emmc_send_command(uint8_t command, uint32_t argument) +{ +} + +uint32_t emmc_get_ocr(uint32_t base_address) +{ +} + diff --git a/src/include/device/emmc/bh720.h b/src/include/device/emmc/bh720.h new file mode 100644 index 0000000..ca8faf5 --- /dev/null +++ b/src/include/device/emmc/bh720.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Silverback Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BH720_H__ +#define __BH720_H__ + +#include <types.h> + +struct bh720_params { + uint8_t total; /* Note 1 */ + uintptr_t base_address; /* memory address */ + uint32_t pci_dev; /* PCI_DEV(bus, slot, func) */ + uint32_t subsys_vend_dev_id; /* if 0 or total = 3, do not set */ + uint8_t mode; /* optional, note 2 */ +}; /* total 5 parameters, so if all parameters, total = 5 */ + +#define MODE_VEND_DEV BIT(0) +#define MODE_DIS_SD BIT(1) +#define MODE_VCCQ_18 BIT(2) +#define MODE_POWER_SAVE BIT(3) +#define MODE_L1_TIMER BIT(4) +#define MODE_IDDQ BIT(5) +#define MODE_TUNNING BIT(6) +#define MODE_DLL_CLK_PHASE BIT(7) + +/* + * Note 1: The value of total shold be between 3 and 5, so value of 1 meaning + * is: + * A) pci_dev is relative to the bridge the host resides. + * B) If the bridge has not been programmed, then program the BAR with base + * adress. + * C) If bridge is programmed, then read BAR0 into base_address. + * D) If subsys_vend_dev_id is provided and (B) than program subsystem vendor + * and device IDs. + * + * Note 2: MODE_DIS_SD, MODE_VCCQ_18, MODE_POWER_SAVE, MODE_IDDQ, MODE_TUNNING, + * MODE_DLL_CLK_PHASE can only be set in ramstage, with a BH720 device defined, + * because they access PCI config space above 0xff. + */ +#define DEFAUT_MODE MODE_VEND_DEV + +#endif diff --git a/src/include/device/emmc/emmc.h b/src/include/device/emmc/emmc.h new file mode 100644 index 0000000..a2305f6 --- /dev/null +++ b/src/include/device/emmc/emmc.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Silverback Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __EMMC_H__ +#define __EMMC_H__ + +#define EMMC_PARAM_BYTE 1 +#define EMMC_PARAM_WORD 2 +#define EMMC_PARAM_DWORD 3 +#define EMMC_PARAM_QWORD 4 +#define EMMC_PARAM_PCI_DEV 5 + +#define EMMC_STATUS_SUCCESS 0 +#define EMMC_STATUS_INVALID_PARAM -1 +#define EMMC_STATUS_NO_BASE_ADDRESS -2 /* drive not initialized */ +#define EMMC_STATUS_INVALID_BASE_ADDR -3 /* invalid base size */ +#define EMMC_STATUS_HOST_BUSY -4 /* bit 31 of OCR 0b */ +#define EMMC_STATUS_INVALID_STAGE -5 /* PCI reg > 0xff in romstage */ + +int emmc_driver_init(void *params); +uint32_t emmc_send_command(uint8_t command, uint32_t argument); +uint32_t emmc_get_ocr(uint32_t base_address); + +int emmc_go_idle(void); +int emmc_go_ready(uint32_t argument); /* CMD1 argument depends on board/host */ +int emmc_check_ready{uint32_t *ocr, uint32_t base_address); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/30109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd2a307ead37c62abca811654873c43c02ac2a4a Gerrit-Change-Number: 30109 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Disable PCH Gigabit LAN
by Lijian Zhao (Code Review) 07 Dec '18

07 Dec '18

Hello Pratikkumar V Prajapati, Subrata Banik, Roy Mingi Park, Bora Guvendik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30096 to look at the new patch set (#4). Change subject: mb/google/sarien: Disable PCH Gigabit LAN ...................................................................... mb/google/sarien: Disable PCH Gigabit LAN There's no LAN connection on Arcada board, so disable PCH GBE. BUG=N/A Change-Id: I07c66df50dbe9fefd95a67b5af9e3f61ce6a18aa Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 1 insertion(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/30096/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/30096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c66df50dbe9fefd95a67b5af9e3f61ce6a18aa Gerrit-Change-Number: 30096 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: google/grunt: Update micron-MT40A1G16KNR-075-E.spd.hex SPD file Modul...
by Martin Roth (Code Review) 07 Dec '18

07 Dec '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30049 ) Change subject: google/grunt: Update micron-MT40A1G16KNR-075-E.spd.hex SPD file Module Part Number ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/30049/2/src/mainboard/google/kahlee/variant… File src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A1G16KNR-075-E.spd.hex: https://review.coreboot.org/#/c/30049/2/src/mainboard/google/kahlee/variant… PS2, Line 23: 00 00 It looks like according to the spec these should both be 20. There's no null terminator in some of the other SPDs, so I think that should be fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/30049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d582b3753de9a48865eb6eca7e4fbdb31b799ff Gerrit-Change-Number: 30049 Gerrit-PatchSet: 2 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Dec 2018 20:46:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: google/grunt: Update hynix-H5AN8G6NAFR-UH.spd.hex SPD file Module Par...
by Martin Roth (Code Review) 07 Dec '18

07 Dec '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30048 ) Change subject: google/grunt: Update hynix-H5AN8G6NAFR-UH.spd.hex SPD file Module Part Number ...................................................................... google/grunt: Update hynix-H5AN8G6NAFR-UH.spd.hex SPD file Module Part Number Correct Ram_ID=0b0000 SPD Module Part Number to "H5AN8G6NAFR-UH" from "HMA851S6AFR6N-UH". BUG=b:120000816 BRANCH=master TEST=mosys memory spd print all Change-Id: I1f6e885638589a35334a9a8f905af4877c5d1f91 Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30048 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NAFR-UH.spd.hex 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NAFR-UH.spd.hex b/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NAFR-UH.spd.hex index fd5fe6f..2a8c293 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NAFR-UH.spd.hex +++ b/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NAFR-UH.spd.hex @@ -19,8 +19,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 AD 01 00 00 00 00 00 00 48 4D 41 38 35 31 53 -36 41 46 52 36 4E 2D 55 48 20 20 20 20 00 80 AD +80 AD 01 00 00 00 00 00 00 48 35 41 4E 38 47 36 +4E 41 46 52 2D 55 48 20 20 20 20 20 20 00 80 AD FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/30048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f6e885638589a35334a9a8f905af4877c5d1f91 Gerrit-Change-Number: 30048 Gerrit-PatchSet: 4 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: google/grunt: Update hynix-H5AN8G6NAFR-UH.spd.hex SPD file Module Par...
by Martin Roth (Code Review) 07 Dec '18

07 Dec '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30048 ) Change subject: google/grunt: Update hynix-H5AN8G6NAFR-UH.spd.hex SPD file Module Part Number ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f6e885638589a35334a9a8f905af4877c5d1f91 Gerrit-Change-Number: 30048 Gerrit-PatchSet: 3 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Dec 2018 19:27:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: google/grunt: Update micron-MT40A512M16JY-083E-B.spd.hex SPD file Mod...
by Martin Roth (Code Review) 07 Dec '18

07 Dec '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30050 ) Change subject: google/grunt: Update micron-MT40A512M16JY-083E-B.spd.hex SPD file Module Part Number ...................................................................... google/grunt: Update micron-MT40A512M16JY-083E-B.spd.hex SPD file Module Part Number Correct Ram_ID=0b0010 SPD Module Part Number to "MT40A512M16JY-083E:B" from "4ATF51264HZ-2G3B2". BUG=b:120000816 BRANCH=master TEST=mosys memory spd print all Change-Id: I6847a55968260cdbc1588ddeb8d23c515ad87920 Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30050 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16JY-083E-B.spd.hex 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16JY-083E-B.spd.hex b/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16JY-083E-B.spd.hex index 6f90d9b..ee6a4a6 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16JY-083E-B.spd.hex +++ b/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16JY-083E-B.spd.hex @@ -19,8 +19,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 2C 00 00 00 00 00 00 00 34 41 54 46 35 31 32 -36 34 48 5a 2d 32 47 33 42 32 20 20 00 32 80 2C +80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 35 31 +32 4D 31 36 4A 59 2D 30 38 33 45 3A 42 32 80 2C 42 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/30050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6847a55968260cdbc1588ddeb8d23c515ad87920 Gerrit-Change-Number: 30050 Gerrit-PatchSet: 3 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: google/grunt: Update micron-MT40A512M16JY-083E-B.spd.hex SPD file Mod...
by Martin Roth (Code Review) 07 Dec '18

07 Dec '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30050 ) Change subject: google/grunt: Update micron-MT40A512M16JY-083E-B.spd.hex SPD file Module Part Number ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6847a55968260cdbc1588ddeb8d23c515ad87920 Gerrit-Change-Number: 30050 Gerrit-PatchSet: 2 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Dec 2018 19:26:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: Documentation/CoC: make clearer it's also for real world events
by Martin Roth (Code Review) 07 Dec '18

07 Dec '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30104 ) Change subject: Documentation/CoC: make clearer it's also for real world events ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23883cfd8200496f4281d73b6e75fac0d3448a3c Gerrit-Change-Number: 30104 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Dec 2018 19:19:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/octopus/phaser: Fix trackpad GPE wake configuration
by Karthik Ramasubramanian (Code Review) 07 Dec '18

07 Dec '18

Hello Karthikeyan Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30105 to review the following change. Change subject: mb/google/octopus/phaser: Fix trackpad GPE wake configuration ...................................................................... mb/google/octopus/phaser: Fix trackpad GPE wake configuration Synaptics Trackpad wake event is incorrectly routed to GPE0_DW2_02. The concerned GPIO is not connected and hence wont trigger a wakeup. Fix the GPE wake configuration for synaptics trackpad. BUG=b:120666158 BRANCH=octopus TEST=Ensure that the wake on trackpad works with Synaptics touch pad. Ensure that the system can enter S0ix successfully(run suspend_stress_test -c 25). Change-Id: I87b8c266266280f61700839d428e6f8938b0f72f Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/octopus/variants/phaser/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/30105/1 diff --git a/src/mainboard/google/octopus/variants/phaser/overridetree.cb b/src/mainboard/google/octopus/variants/phaser/overridetree.cb index f996d8b..d42fe81 100644 --- a/src/mainboard/google/octopus/variants/phaser/overridetree.cb +++ b/src/mainboard/google/octopus/variants/phaser/overridetree.cb @@ -84,8 +84,8 @@ chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_135_IRQ)" - register "generic.wake" = "GPE0_DW2_02" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.wake" = "GPE0_DW3_27" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 0x2c on end -- To view, visit https://review.coreboot.org/c/coreboot/+/30105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87b8c266266280f61700839d428e6f8938b0f72f Gerrit-Change-Number: 30105 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: libpayload: Don't try to use invalid row count
by Martin Roth (Code Review) 07 Dec '18

07 Dec '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30092 ) Change subject: libpayload: Don't try to use invalid row count ...................................................................... Patch Set 1: > Patch Set 1: > > (1 comment) > > > Are you sure this is the right fix? I'd argue that a console with 0 rows is an illegal console anyway, so ... > > Same sentiment here. I'm curious where it began to leave the rails. I'm certainly not going to disagree that there's something wrong somewhere earlier in the chain, but I'd argue that an invalid console isn't a reason to hang the system. I'm going to keep working on this issue, but I think think this is a good first step. -- To view, visit https://review.coreboot.org/c/coreboot/+/30092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib022d3c6fc0c9cf360809dca28761a50c787304a Gerrit-Change-Number: 30092 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Fri, 07 Dec 2018 18:52:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2018