coreboot-gerrit December 2018

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Change in ...coreboot[master]: Documentation/CoC: make clearer it's also for real world events
by Patrick Georgi (Code Review) 07 Dec '18

07 Dec '18

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30104 Change subject: Documentation/CoC: make clearer it's also for real world events ...................................................................... Documentation/CoC: make clearer it's also for real world events It's not just for the mailing lists, tools and IRC channel. Change-Id: I23883cfd8200496f4281d73b6e75fac0d3448a3c Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/code_of_conduct.md 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/30104/1 diff --git a/Documentation/code_of_conduct.md b/Documentation/code_of_conduct.md index b262a3b..c40393f 100644 --- a/Documentation/code_of_conduct.md +++ b/Documentation/code_of_conduct.md @@ -3,11 +3,11 @@ This code of conduct outlines our rules and expectations for everybody participating in the coreboot community. -## Mailing list and chat etiquette +## coreboot community etiquette We have a friendly and productive atmosphere on our mailing lists, -development / code review tools and IRC chat rooms. Our principles evolve -around the following: +development / code review tools, IRC chat rooms and when we meet in +person. Our principles evolve around the following: * It's not the user's fault if something goes wrong. * Attempt collaboration before conflict. -- To view, visit https://review.coreboot.org/c/coreboot/+/30104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23883cfd8200496f4281d73b6e75fac0d3448a3c Gerrit-Change-Number: 30104 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: qclib: Add qclib support
by Patrick Georgi (Code Review) 07 Dec '18

07 Dec '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29967 ) Change subject: qclib: Add qclib support ...................................................................... Patch Set 2: (1 comment) lots of parts are commented out. please sort that out before the next iteration. Also, we indent code by tabs (as the build bot helpfully pointed out), so please account for that. https://review.coreboot.org/#/c/29967/2/src/mainboard/google/mistral/mainbo… File src/mainboard/google/mistral/mainboard.c: https://review.coreboot.org/#/c/29967/2/src/mainboard/google/mistral/mainbo… PS2, Line 21: #if 0 what's this for? if it's not needed, kick it out entirely. -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 2 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Fri, 07 Dec 2018 18:16:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Enable ISH on arcada, disable on sarien
by Patrick Georgi (Code Review) 07 Dec '18

07 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30070 ) Change subject: mb/google/sarien: Enable ISH on arcada, disable on sarien ...................................................................... mb/google/sarien: Enable ISH on arcada, disable on sarien The Intel Sensor Hub was enabled on the wrong variant so this change moves the enable from sarien to arcada. Change-Id: If933623f7dbb45c4805fb61430465236eca19ee8 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/c/30070 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Li1 Feng <li1.feng(a)intel.com> Reviewed-by: Jett Rink <jettrink(a)chromium.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Jett Rink: Looks good to me, but someone else must approve Li1 Feng: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 54308e1..93e0af9 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -113,6 +113,7 @@ device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 + device pci 13.0 on end # Integrated Sensor Hub device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 6afc13c..d25e725 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -113,7 +113,7 @@ device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 - device pci 13.0 on end # Integrated Sensor Hub + device pci 13.0 off end # Integrated Sensor Hub device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" -- To view, visit https://review.coreboot.org/c/coreboot/+/30070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If933623f7dbb45c4805fb61430465236eca19ee8 Gerrit-Change-Number: 30070 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Jett Rink <jettrink(a)chromium.org> Gerrit-Reviewer: Jett Rink <jettrink(a)google.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/sarien: Enable ISH on arcada, disable on sarien
by Patrick Georgi (Code Review) 07 Dec '18

07 Dec '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30070 ) Change subject: mb/google/sarien: Enable ISH on arcada, disable on sarien ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If933623f7dbb45c4805fb61430465236eca19ee8 Gerrit-Change-Number: 30070 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Jett Rink <jettrink(a)chromium.org> Gerrit-Reviewer: Jett Rink <jettrink(a)google.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Dec 2018 18:02:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Enable LAN clock source usage
by Duncan Laurie (Code Review) 07 Dec '18

07 Dec '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30100 ) Change subject: mb/google/sarien: Enable LAN clock source usage ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f945be4f0ce15470ab53f44e60143f3fd0fddf8 Gerrit-Change-Number: 30100 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Dec 2018 17:52:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Enable LAN clock source usage
by Lijian Zhao (Code Review) 07 Dec '18

07 Dec '18

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30100 ) Change subject: mb/google/sarien: Enable LAN clock source usage ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/30100/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/30100/1//COMMIT_MSG@7 PS1, Line 7: sarien > {arcada, sarien} But the directory is sarien, I thought that's enough? -- To view, visit https://review.coreboot.org/c/coreboot/+/30100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f945be4f0ce15470ab53f44e60143f3fd0fddf8 Gerrit-Change-Number: 30100 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Dec 2018 17:41:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: Documentation: Add documentation about the release process
by Martin Roth (Code Review) 07 Dec '18

07 Dec '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30082 ) Change subject: Documentation: Add documentation about the release process ...................................................................... Patch Set 1: Code-Review+1 Thanks for your updates. Everything looks good to me. -- To view, visit https://review.coreboot.org/c/coreboot/+/30082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14938d678e4620abec7ed5f0d35dddaf00edda6d Gerrit-Change-Number: 30082 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Dec 2018 17:29:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: libpayload: Add Timer for qcs405
by Patrick Georgi (Code Review) 07 Dec '18

07 Dec '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29953 ) Change subject: libpayload: Add Timer for qcs405 ...................................................................... Patch Set 2: the commit message doesn't match what the commit does, as it only adds a config file -- To view, visit https://review.coreboot.org/c/coreboot/+/29953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15273fdacab0a23e05e821c433cf939be35fab97 Gerrit-Change-Number: 29953 Gerrit-PatchSet: 2 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Fri, 07 Dec 2018 14:56:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/cpu/intel: Set get_ia32_fsb function common
by HAOUAS Elyes (Code Review) 07 Dec '18

07 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30103 Change subject: src/cpu/intel: Set get_ia32_fsb function common ...................................................................... src/cpu/intel: Set get_ia32_fsb function common get_ia32_fsb will return FSB values of intel's CPUs. Change-Id: I232bf88de7ebba6ac5865db046ce79e9b2f3ed28 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/common/Makefile.inc A src/cpu/intel/common/fsb.c A src/include/cpu/intel/fsb.h 3 files changed, 88 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/30103/1 diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc index 1e94ec9..2fc6da9 100644 --- a/src/cpu/intel/common/Makefile.inc +++ b/src/cpu/intel/common/Makefile.inc @@ -1 +1,5 @@ ramstage-y += common_init.c +romstage-$(CONFIG_UDELAY_LAPIC) += fsb.c +ramstage-$(CONFIG_UDELAY_LAPIC) += fsb.c +postcar-$(CONFIG_UDELAY_LAPIC) += fsb.c +smm-y += fsb.c diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c new file mode 100644 index 0000000..9195ee6 --- /dev/null +++ b/src/cpu/intel/common/fsb.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <cpu/intel/speedstep.h> +#include <cpu/intel/fsb.h> +#include <console/console.h> + +int get_ia32_fsb(void) +{ + struct cpuinfo_x86 c; + int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 }; + int core2_fsb[8] = { 266, 133, 200, 166, 333, 100, 400, -1 }; + int f2x_fsb[8] = { 100, 133, 200, 166, -1, -1, -1, -1 }; + msr_t msr; + + get_fms(&c, cpuid_eax(1)); + switch (c.x86) { + case 0x6: + switch (c.x86_model) { + case 0xe: /* Core Solo/Duo */ + case 0x1c: /* Atom */ + return core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; + case 0xf: /* Core 2 or Xeon */ + case 0x17: /* Enhanced Core */ + return core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; + case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ + case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/ + case 0x3c: /* Haswell BCLK fixed at 100MHz */ + case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ + return 100; + default: + printk(BIOS_WARNING, + "Warning: No supported FSB frequency. Assuming 200MHz\n"); + return 200; + } + case 0xf: /* Netburst */ + msr = rdmsr(MSR_EBC_FREQUENCY_ID); + switch (c.x86_model) { + case 0x2: + return f2x_fsb[(msr.lo >> 16) & 7]; + case 0x3: + case 0x4: + case 0x6: + return core2_fsb[(msr.lo >> 16) & 7]; + default: + printk(BIOS_WARNING, + "Warning: No supported FSB frequency. Assuming 200MHz\n"); + return 200; + } /* default: fallthrough */ + default: + return -1; + } +} diff --git a/src/include/cpu/intel/fsb.h b/src/include/cpu/intel/fsb.h new file mode 100644 index 0000000..8064111 --- /dev/null +++ b/src/include/cpu/intel/fsb.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef CPU_INTEL_FSB_H +#define CPU_INTEL_FSB_H + +int get_ia32_fsb(void); + +#endif /* CPU_INTEL_FSB_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232bf88de7ebba6ac5865db046ce79e9b2f3ed28 Gerrit-Change-Number: 30103 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/soc/intel/braswell: Use DEVICE_NOOP
by HAOUAS Elyes (Code Review) 07 Dec '18

07 Dec '18

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29857 to look at the new patch set (#3). Change subject: src/soc/intel/braswell: Use DEVICE_NOOP ...................................................................... src/soc/intel/braswell: Use DEVICE_NOOP Use already defined DEVICE_NOOP instead. Change-Id: Ie6182f273cba3073c84a502c34a002dee6122c2f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/braswell/chip.c 1 file changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/29857/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/29857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6182f273cba3073c84a502c34a002dee6122c2f Gerrit-Change-Number: 29857 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2018