coreboot-gerrit December 2018

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Change in ...coreboot[master]: sb/amd/pi/hudson: Fix UART address math
by Patrick Georgi (Code Review) 07 Dec '18

07 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30072 ) Change subject: sb/amd/pi/hudson: Fix UART address math ...................................................................... sb/amd/pi/hudson: Fix UART address math Correct a build error that occurs when HUDSON_UART is selected. Replace sizeof() of a nonexistent variable with the intended type. This was introduced in bd48b23 "southbridge//hudson: Get rid of void pointer math". BUG=b:118484178 TEST=Build Bettong with Chipset/"UART controller for Kern" Change-Id: Icc0ff9d80c3f5cab9ab837cf1cd0cd8eb0753284 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/30072 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/southbridge/amd/pi/hudson/early_setup.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 07c4519..3b91f9b 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -36,10 +36,10 @@ u8 byte; byte = read8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + - CONFIG_UART_FOR_CONSOLE * sizeof(word))); + CONFIG_UART_FOR_CONSOLE * sizeof(u16))); byte |= 1 << 3; write8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + - CONFIG_UART_FOR_CONSOLE * sizeof(word)), byte); + CONFIG_UART_FOR_CONSOLE * sizeof(u16)), byte); byte = read8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62)); byte |= 1 << 3; write8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62), byte); -- To view, visit https://review.coreboot.org/c/coreboot/+/30072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc0ff9d80c3f5cab9ab837cf1cd0cd8eb0753284 Gerrit-Change-Number: 30072 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: sb/intel/lynxpoint/pcie.c: Fix a mistake in a comment
by Patrick Georgi (Code Review) 07 Dec '18

07 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30078 ) Change subject: sb/intel/lynxpoint/pcie.c: Fix a mistake in a comment ...................................................................... sb/intel/lynxpoint/pcie.c: Fix a mistake in a comment The code annotated by the comment is dealing with root port 7, so update the comment to reflect that. It looks like the comment was copied from the root port 3 case, but not updated. Change-Id: I0e27e4453f4c3b2b1b9dffb0c89b71373c6b303e Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30078 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/pcie.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index a7966f1..70bfe18 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -395,7 +395,7 @@ case 7: if (is_lp) break; - /* Root Port 3 is disabled in config 11b (1x4 links). */ + /* Root Port 7 is disabled in config 11b (1x4 links). */ if (((rpc.strpfusecfg2 >> 14) & 0x3) == 0x3) { root_port_mark_disable(dev); return; -- To view, visit https://review.coreboot.org/c/coreboot/+/30078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e27e4453f4c3b2b1b9dffb0c89b71373c6b303e Gerrit-Change-Number: 30078 Gerrit-PatchSet: 2 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: sb/intel/lynxpoint: Handle H81 only having 6 PCIe root ports
by Patrick Georgi (Code Review) 07 Dec '18

07 Dec '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30077 ) Change subject: sb/intel/lynxpoint: Handle H81 only having 6 PCIe root ports ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/30077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3ce217e8a4f4ea4e111e4525b03dbbfc63f92b0 Gerrit-Change-Number: 30077 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Dec 2018 11:32:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/braswell: Use DEVICE_NOOP
by HAOUAS Elyes (Code Review) 07 Dec '18

07 Dec '18

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29857 to look at the new patch set (#2). Change subject: src/soc/intel/braswell: Use DEVICE_NOOP ...................................................................... src/soc/intel/braswell: Use DEVICE_NOOP Use already defined DEVICE_NOOP instead. Change-Id: Ie6182f273cba3073c84a502c34a002dee6122c2f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/braswell/chip.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/29857/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6182f273cba3073c84a502c34a002dee6122c2f Gerrit-Change-Number: 29857 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: src/southbridge: Get rid of device_t
by Patrick Georgi (Code Review) 07 Dec '18

07 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30045 ) Change subject: src/southbridge: Get rid of device_t ...................................................................... src/southbridge: Get rid of device_t Use of device_t is deprecated. Change-Id: Ib4db9c263ff156966926f9576eed7e3cfb02e78a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/30045 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/amd/sr5650/cmn.h M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/usb_xhci.c 4 files changed, 137 insertions(+), 39 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h index 859e15d..126b786 100644 --- a/src/southbridge/amd/sr5650/cmn.h +++ b/src/southbridge/amd/sr5650/cmn.h @@ -34,30 +34,54 @@ #define AB_INDX 0xCD8 #define AB_DATA (AB_INDX+4) -static inline u32 nb_read_index(device_t dev, u32 index_reg, u32 index) +#ifdef __SIMPLE_DEVICE__ +static inline u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index) +#else +static inline u32 nb_read_index(struct device *dev, u32 index_reg, u32 index) +#endif { pci_write_config32(dev, index_reg, index); return pci_read_config32(dev, index_reg + 0x4); } -static inline void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data) +#ifdef __SIMPLE_DEVICE__ +static inline void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index, + u32 data) +#else +static inline void nb_write_index(struct device *dev, u32 index_reg, u32 index, + u32 data) +#endif { pci_write_config32(dev, index_reg, index); pci_write_config32(dev, index_reg + 0x4, data); } -static inline u32 nbmisc_read_index(device_t nb_dev, u32 index) +#ifdef __SIMPLE_DEVICE__ +static inline u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index) +#else +static inline u32 nbmisc_read_index(struct device *nb_dev, u32 index) +#endif { return nb_read_index((nb_dev), NBMISC_INDEX, (index)); } -static inline void nbmisc_write_index(device_t nb_dev, u32 index, u32 data) +#ifdef __SIMPLE_DEVICE__ +static inline void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) +#else +static inline void nbmisc_write_index(struct device *nb_dev, u32 index, + u32 data) +#endif { nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data)); } -static inline void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, - u32 val) +#ifdef __SIMPLE_DEVICE__ +static inline void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, + u32 mask, u32 val) +#else +static inline void set_nbmisc_enable_bits(struct device *nb_dev, u32 reg_pos, + u32 mask, u32 val) +#endif { u32 reg_old, reg; reg = reg_old = nbmisc_read_index(nb_dev, reg_pos); @@ -68,28 +92,49 @@ } } -static inline u32 htiu_read_index(device_t nb_dev, u32 index) +#ifdef __SIMPLE_DEVICE__ +static inline u32 htiu_read_index(pci_devfn_t nb_dev, u32 index) +#else +static inline u32 htiu_read_index(struct device *nb_dev, u32 index) +#endif { return nb_read_index((nb_dev), NBHTIU_INDEX, (index)); } -static inline void htiu_write_index(device_t nb_dev, u32 index, u32 data) +#ifdef __SIMPLE_DEVICE__ +static inline void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data) +#else +static inline void htiu_write_index(struct device *nb_dev, u32 index, u32 data) +#endif { nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data)); } -static inline u32 nbmc_read_index(device_t nb_dev, u32 index) +#ifdef __SIMPLE_DEVICE__ +static inline u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index) +#else +static inline u32 nbmc_read_index(struct device *nb_dev, u32 index) +#endif { return nb_read_index((nb_dev), NBMC_INDEX, (index)); } -static inline void nbmc_write_index(device_t nb_dev, u32 index, u32 data) +#ifdef __SIMPLE_DEVICE__ +static inline void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) +#else +static inline void nbmc_write_index(struct device *nb_dev, u32 index, u32 data) +#endif { nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data)); } -static inline void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, - u32 val) +#ifdef __SIMPLE_DEVICE__ +static inline void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, + u32 mask, u32 val) +#else +static inline void set_htiu_enable_bits(struct device *nb_dev, u32 reg_pos, + u32 mask, u32 val) +#endif { u32 reg_old, reg; reg = reg_old = htiu_read_index(nb_dev, reg_pos); @@ -100,8 +145,13 @@ } } -static inline void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, - u32 val) +#ifdef __SIMPLE_DEVICE__ +static inline void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, + u32 mask, u32 val) +#else +static inline void set_nbcfg_enable_bits(struct device *nb_dev, u32 reg_pos, + u32 mask, u32 val) +#endif { u32 reg_old, reg; reg = reg_old = pci_read_config32(nb_dev, reg_pos); @@ -112,8 +162,13 @@ } } -static inline void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, - u8 val) +#ifdef __SIMPLE_DEVICE__ +static inline void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, + u8 mask, u8 val) +#else +static inline void set_nbcfg_enable_bits_8(struct device *nb_dev, u32 reg_pos, + u8 mask, u8 val) +#endif { u8 reg_old, reg; reg = reg_old = pci_read_config8(nb_dev, reg_pos); @@ -124,8 +179,13 @@ } } -static inline void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, - u32 val) +#ifdef __SIMPLE_DEVICE__ +static inline void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, + u32 mask, u32 val) +#else +static inline void set_nbmc_enable_bits(struct device *nb_dev, u32 reg_pos, + u32 mask, u32 val) +#endif { u32 reg_old, reg; reg = reg_old = nbmc_read_index(nb_dev, reg_pos); @@ -136,7 +196,13 @@ } } -static inline void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val) +#ifdef __SIMPLE_DEVICE__ +static inline void set_pcie_enable_bits(pci_devfn_t dev, u32 reg_pos, u32 mask, + u32 val) +#else +static inline void set_pcie_enable_bits(struct device *dev, u32 reg_pos, + u32 mask, u32 val) +#endif { u32 reg_old, reg; reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos); diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 574a830..1a0a68c 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -52,12 +52,16 @@ [ME_DISABLE_BIOS_PATH] = "Disable", [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev); +static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev); #endif /* MMIO base address for MEI interface */ static u32 *mei_base_address; -void intel_me_mbp_clear(device_t dev); +#ifdef __SIMPLE_DEVICE__ +void intel_me_mbp_clear(pci_devfn_t dev); +#else +void intel_me_mbp_clear(struct device *dev); +#endif #if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) @@ -112,7 +116,11 @@ mei_dump(ptr, dword, offset, "WRITE"); } -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +#ifdef __SIMPLE_DEVICE__ +static inline void pci_read_dword_ptr(pci_devfn_t dev, void *ptr, int offset) +#else +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) +#endif { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -413,7 +421,11 @@ * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read * state machine on the BIOS end doesn't match the ME's state machine. */ -static void intel_me_mbp_give_up(device_t dev) +#ifdef __SIMPLE_DEVICE__ +static void intel_me_mbp_give_up(pci_devfn_t dev) +#else +static void intel_me_mbp_give_up(struct device *dev) +#endif { struct mei_csr csr; @@ -429,7 +441,11 @@ * mbp clear routine. This will wait for the ME to indicate that * the MBP has been read and cleared. */ -void intel_me_mbp_clear(device_t dev) +#ifdef __SIMPLE_DEVICE__ +void intel_me_mbp_clear(pci_devfn_t dev) +#else +void intel_me_mbp_clear(struct device *dev) +#endif { int count; struct me_hfs2 hfs2; @@ -657,7 +673,7 @@ } /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -727,7 +743,7 @@ } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -757,7 +773,7 @@ } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -804,7 +820,7 @@ } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { struct southbridge_intel_lynxpoint_config *config = dev->chip_info; me_bios_path path = intel_me_path(dev); @@ -857,7 +873,8 @@ */ } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -872,7 +889,7 @@ .set_subsystem = set_subsystem, }; -static void intel_me_enable(device_t dev) +static void intel_me_enable(struct device *dev) { /* Avoid talking to the device in S3 path */ if (acpi_is_wakeup_s3()) { @@ -939,7 +956,7 @@ * mbp seems to be following its own flow, let's retrieve it in a dedicated * function. */ -static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) +static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) { mbp_header mbp_hdr; u32 me2host_pending; diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index cb01de7..6596aa2 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -23,14 +23,17 @@ #include <device/pci_def.h> #include "pch.h" -static device_t pch_get_lpc_device(void) +#ifdef __SIMPLE_DEVICE__ +static pci_devfn_t pch_get_lpc_device(void) { -#ifdef __SMM__ return PCI_DEV(0, 0x1f, 0); -#else - return dev_find_slot(0, PCI_DEVFN(0x1f, 0)); -#endif } +#else +static struct device *pch_get_lpc_device(void) +{ + return dev_find_slot(0, PCI_DEVFN(0x1f, 0)); +} +#endif int pch_silicon_revision(void) { diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 186e3f9..03341da 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -23,7 +23,11 @@ typedef struct southbridge_intel_lynxpoint_config config_t; -static u8 *usb_xhci_mem_base(device_t dev) +#ifdef __SIMPLE_DEVICE__ +static u8 *usb_xhci_mem_base(pci_devfn_t dev) +#else +static u8 *usb_xhci_mem_base(struct device *dev) +#endif { u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -34,7 +38,11 @@ return (u8 *)(mem_base & ~0xf); } -static int usb_xhci_port_count_usb3(device_t dev) +#ifdef __SIMPLE_DEVICE__ +static int usb_xhci_port_count_usb3(pci_devfn_t dev) +#else +static int usb_xhci_port_count_usb3(struct device *dev) +#endif { if (pch_is_lp()) { /* LynxPoint-LP has 4 SS ports */ @@ -81,7 +89,11 @@ * b) Poll for warm reset complete * c) Write 1 to port change status bits */ -static void usb_xhci_reset_usb3(device_t dev, int all) +#ifdef __SIMPLE_DEVICE__ +static void usb_xhci_reset_usb3(pci_devfn_t dev, int all) +#else +static void usb_xhci_reset_usb3(struct device *dev, int all) +#endif { u32 status, port_disabled; int timeout, port; -- To view, visit https://review.coreboot.org/c/coreboot/+/30045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4db9c263ff156966926f9576eed7e3cfb02e78a Gerrit-Change-Number: 30045 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/sarien: Enable LAN clock source usage
by Subrata Banik (Code Review) 07 Dec '18

07 Dec '18

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30100 ) Change subject: mb/google/sarien: Enable LAN clock source usage ...................................................................... Patch Set 1: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/30100/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/30100/1//COMMIT_MSG@7 PS1, Line 7: sarien {arcada, sarien} -- To view, visit https://review.coreboot.org/c/coreboot/+/30100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f945be4f0ce15470ab53f44e60143f3fd0fddf8 Gerrit-Change-Number: 30100 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Dec 2018 08:39:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/asrock/h81m-hds: Allow "keep state" for power_on_after_fail
by Tristan Corrick (Code Review) 07 Dec '18

07 Dec '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30102 Change subject: mb/asrock/h81m-hds: Allow "keep state" for power_on_after_fail ...................................................................... mb/asrock/h81m-hds: Allow "keep state" for power_on_after_fail When I added the cmos.layout file, I did not realise that the southbridge code cleverly emulated the "keep state" option. Tested on an ASRock H81M-HDS. The `Keep` option works as it should. Change-Id: I908e59d1e1eedefa6610e7f980afc3c04390a519 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/mainboard/asrock/h81m-hds/cmos.layout 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/30102/1 diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout index c7947f7..4926a45 100644 --- a/src/mainboard/asrock/h81m-hds/cmos.layout +++ b/src/mainboard/asrock/h81m-hds/cmos.layout @@ -55,7 +55,7 @@ # coreboot config options: southbridge 408 1 e 1 nmi -409 2 e 1 power_on_after_fail +409 2 e 5 power_on_after_fail # coreboot config options: check sums 984 16 h 0 check_sum @@ -84,6 +84,10 @@ 4 7 Debug 4 8 Spew +5 0 Disable +5 1 Enable +5 2 Keep + # ----------------------------------------------------------------- checksums -- To view, visit https://review.coreboot.org/c/coreboot/+/30102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I908e59d1e1eedefa6610e7f980afc3c04390a519 Gerrit-Change-Number: 30102 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/lynxpoint: Don't force state keep after power fail
by Tristan Corrick (Code Review) 07 Dec '18

07 Dec '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30101 Change subject: sb/intel/lynxpoint: Don't force state keep after power fail ...................................................................... sb/intel/lynxpoint: Don't force state keep after power fail The deleted line crept in with commit 562db3bb3fa1 ("libpayload: find source of input characters"). Tested on an ASRock H81M-HDS with `power_on_after_fail` set to `Disable` via CMOS. After this patch, the system no longer powers on as soon as power is restored after a power failure. Change-Id: Ie9d9dab9885b285db1c5094c2c8d62aae551f1e7 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/30101/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index d914636..f0fc22d 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -199,7 +199,6 @@ * If the option is not existent (Laptops), use Kconfig setting. */ get_option(&pwr_on, "power_on_after_fail"); - pwr_on = MAINBOARD_POWER_KEEP; reg16 = pci_read_config16(dev, GEN_PMCON_3); reg16 &= 0xfffe; -- To view, visit https://review.coreboot.org/c/coreboot/+/30101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9d9dab9885b285db1c5094c2c8d62aae551f1e7 Gerrit-Change-Number: 30101 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/grunt: Update micron-MT40A512M16JY-083E-B.spd.hex SPD file Mod...
by Lucas Chen (Code Review) 07 Dec '18

07 Dec '18

Hello Tim Chen, build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30050 to look at the new patch set (#2). Change subject: google/grunt: Update micron-MT40A512M16JY-083E-B.spd.hex SPD file Module Part Number ...................................................................... google/grunt: Update micron-MT40A512M16JY-083E-B.spd.hex SPD file Module Part Number Correct Ram_ID=0b0010 SPD Module Part Number to "MT40A512M16JY-083E:B" from "4ATF51264HZ-2G3B2". BUG=b:120000816 BRANCH=master TEST=mosys memory spd print all Change-Id: I6847a55968260cdbc1588ddeb8d23c515ad87920 Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16JY-083E-B.spd.hex 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/30050/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6847a55968260cdbc1588ddeb8d23c515ad87920 Gerrit-Change-Number: 30050 Gerrit-PatchSet: 2 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: google/grunt: Update micron-MT40A512M16JY-083E-B.spd.hex SPD file Mod...
by Lucas Chen (Code Review) 07 Dec '18

07 Dec '18

Lucas Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30050 ) Change subject: google/grunt: Update micron-MT40A512M16JY-083E-B.spd.hex SPD file Module Part Number ...................................................................... Patch Set 1: > Patch Set 1: > > (1 comment) Sorry , Correct these bytes without change. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/30050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6847a55968260cdbc1588ddeb8d23c515ad87920 Gerrit-Change-Number: 30050 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Dec 2018 07:22:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2018