coreboot-gerrit December 2018

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Change in ...coreboot[master]: Fix potential NULL pointer dereferences and memory leak.
by Francois Toguo Fotso (Code Review) 07 Dec '18

07 Dec '18

Francois Toguo Fotso has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30098 Change subject: Fix potential NULL pointer dereferences and memory leak. ...................................................................... Fix potential NULL pointer dereferences and memory leak. Found-by: Klockwork BUG=None TEST=Boot to OS Change-Id: I38a8910e68b7a8ce0e97ca4cdb9ef7f595c0e319 Signed-off-by: Francois Toguo <francois.toguo.fotso(a)intel.com> --- M src/arch/x86/acpi_device.c M src/arch/x86/acpigen.c M src/include/nhlt.h M src/lib/nhlt.c M src/soc/intel/common/nhlt.c 5 files changed, 17 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/30098/1 diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index 48b7fee..12bd1ad 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -635,8 +635,10 @@ char *dp_count, *prop_count; int child_count = 0; - if (!table || table->type != ACPI_DP_TYPE_TABLE) + if (!table || table->type != ACPI_DP_TYPE_TABLE) { + acpi_dp_free(table); return; + } /* Name (name) */ acpigen_write_name(table->name); diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 290893d..00aec60 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -286,6 +286,13 @@ int dotcount = 0, i; int dotpos = 0; + /* If we have a null pointer. Then we need to put a null + name (0x00). */ + if (!namepath) { + acpigen_emit_byte(ZERO_OP); + return; + } + /* We can start with a '\'. */ if (namepath[0] == '\\') { acpigen_emit_byte('\\'); @@ -369,23 +376,6 @@ acpigen_pop_len(); } -/* Method to notify all CPU cores */ -void acpigen_write_processor_cnot(const unsigned int number_of_cores) -{ - int core_id; - - acpigen_write_method("\\_PR.CNOT", 1); - for (core_id = 0; core_id < number_of_cores; core_id++) { - char buffer[DEVICE_PATH_MAX]; - snprintf(buffer, sizeof(buffer), CONFIG_ACPI_CPU_STRING, - core_id); - acpigen_emit_byte(NOTIFY_OP); - acpigen_emit_namestring(buffer); - acpigen_emit_byte(ARG0_OP); - } - acpigen_pop_len(); -} - /* * Generate ACPI AML code for OperationRegion * Arg0: Pointer to struct opregion opreg = OPREGION(rname, space, offset, len) diff --git a/src/include/nhlt.h b/src/include/nhlt.h index a361ed8..5fdb191 100644 --- a/src/include/nhlt.h +++ b/src/include/nhlt.h @@ -57,6 +57,9 @@ /* Return the size of the NHLT table including APCI header. */ size_t nhlt_current_size(struct nhlt *nhlt); +/* Frees the allocated resources/memory for NHLT table */ +void nhlt_free_resources(struct nhlt *nhlt); + /* * Helper functions for adding NHLT devices utilizing an nhlt_endp_descriptor * to drive the logic. diff --git a/src/lib/nhlt.c b/src/lib/nhlt.c index 5001c38..0db5f7d 100644 --- a/src/lib/nhlt.c +++ b/src/lib/nhlt.c @@ -279,7 +279,7 @@ return calc_size(nhlt) + sizeof(acpi_header_t); } -static void nhlt_free_resources(struct nhlt *nhlt) +void nhlt_free_resources(struct nhlt *nhlt) { int i; int j; diff --git a/src/soc/intel/common/nhlt.c b/src/soc/intel/common/nhlt.c index a268ea6..5ecb641 100644 --- a/src/soc/intel/common/nhlt.c +++ b/src/soc/intel/common/nhlt.c @@ -30,8 +30,10 @@ gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs == NULL) + if (gnvs == NULL) { + nhlt_free_resources(nhlt); return acpi_addr; + } /* Update NHLT GNVS Data */ gnvs->nhla = (uintptr_t)acpi_addr; -- To view, visit https://review.coreboot.org/c/coreboot/+/30098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38a8910e68b7a8ce0e97ca4cdb9ef7f595c0e319 Gerrit-Change-Number: 30098 Gerrit-PatchSet: 1 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/poppy/variants/nami: Modify SPD for hynix memory part
by Ren Kuo (Code Review) 07 Dec '18

07 Dec '18

Ren Kuo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30076 ) Change subject: mb/google/poppy/variants/nami: Modify SPD for hynix memory part ...................................................................... Patch Set 1: > Patch Set 1: > > (1 comment) the previous part with"A" was submit by me. now i correct the P/N to"4". but I not sure it will be use by other projects -- To view, visit https://review.coreboot.org/c/coreboot/+/30076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c33343eb1269919fba324333897805da1d1ff9b Gerrit-Change-Number: 30076 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Vincent Wang <vwang(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Dec 2018 03:19:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: libpayload: Don't try to use invalid row count
by Marshall Dawson (Code Review) 07 Dec '18

07 Dec '18

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30092 ) Change subject: libpayload: Don't try to use invalid row count ...................................................................... Patch Set 1: (1 comment) > Are you sure this is the right fix? I'd argue that a console with 0 rows is an illegal console anyway, so ... Same sentiment here. I'm curious where it began to leave the rails. https://review.coreboot.org/#/c/30092/1/payloads/libpayload/drivers/video/v… File payloads/libpayload/drivers/video/video.c: https://review.coreboot.org/#/c/30092/1/payloads/libpayload/drivers/video/v… PS1, Line 90: console->rows <= 0 Just to be complete, maybe (console->rows <= 0 || console->columns <= 0)? Granted, it's a solution in search of a problem... -- To view, visit https://review.coreboot.org/c/coreboot/+/30092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib022d3c6fc0c9cf360809dca28761a50c787304a Gerrit-Change-Number: 30092 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Fri, 07 Dec 2018 02:28:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/poppy/variants/nami: Modify SPD for hynix memory part
by Furquan Shaikh (Code Review) 07 Dec '18

07 Dec '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30076 ) Change subject: mb/google/poppy/variants/nami: Modify SPD for hynix memory part ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/30076/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nami/Makefile.inc: https://review.coreboot.org/#/c/30076/1/src/mainboard/google/poppy/variants… PS1, Line 14: So this part was never used on any of the nami variants? Shelley, can you please verify? -- To view, visit https://review.coreboot.org/c/coreboot/+/30076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c33343eb1269919fba324333897805da1d1ff9b Gerrit-Change-Number: 30076 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Vincent Wang <vwang(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Dec 2018 02:03:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Auto turn on HDA controller
by Lijian Zhao (Code Review) 07 Dec '18

07 Dec '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30097 Change subject: soc/intel/cannonlake: Auto turn on HDA controller ...................................................................... soc/intel/cannonlake: Auto turn on HDA controller Update HDAenable bit in Fsp memory init UPD data base on devicetree settings. BUG=N/A TEST=N/A Change-Id: I5159c00a855a2a9516714ccee8ee9933465c5063 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/romstage/fsp_params.c 2 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/30097/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 9eb91bd..f148c37 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -130,7 +130,6 @@ uint8_t SataPortsDevSlp[8]; /* Audio related */ - uint8_t PchHdaEnable; uint8_t PchHdaDspEnable; /* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */ diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 8f6fa2f..d188a96 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -61,6 +61,14 @@ m_cfg->PchIshEnable = 0; else m_cfg->PchIshEnable = dev->enabled; + + /* If HDA is enabled, enable HDA elements */ + dev = dev_find_slot(0, PCH_DEVFN_HDA); + if (!dev) + m_cfg->PchHdaEnable = 0; + else + m_cfg->PchHdaEnable = dev->enabled; + } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/30097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5159c00a855a2a9516714ccee8ee9933465c5063 Gerrit-Change-Number: 30097 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Disable PCH Gigabit LAN
by Roy Mingi Park (Code Review) 07 Dec '18

07 Dec '18

Roy Mingi Park has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30096 ) Change subject: mb/google/sarien: Disable PCH Gigabit LAN ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/30096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c66df50dbe9fefd95a67b5af9e3f61ce6a18aa Gerrit-Change-Number: 30096 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Dec 2018 01:30:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Disable PCH Gigabit LAN
by Roy Mingi Park (Code Review) 07 Dec '18

07 Dec '18

Roy Mingi Park has uploaded a new patch set (#2) to the change originally created by Lijian Zhao. ( https://review.coreboot.org/c/coreboot/+/30096 ) Change subject: mb/google/sarien: Disable PCH Gigabit LAN ...................................................................... mb/google/sarien: Disable PCH Gigabit LAN There's no LAN connection on Arcada board, so disable PCH GBE. BUG=N/A Change-Id: I07c66df50dbe9fefd95a67b5af9e3f61ce6a18aa Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/30096/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c66df50dbe9fefd95a67b5af9e3f61ce6a18aa Gerrit-Change-Number: 30096 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/sarien: Disable PCH Gigabit LAN
by Lijian Zhao (Code Review) 07 Dec '18

07 Dec '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30096 Change subject: mb/google/sarien: Disable PCH Gigabit LAN ...................................................................... mb/google/sarien: Disable PCH Gigabit LAN There's no LOM connection on Arcada board, so disable PCH GBE. BUG=N/A Change-Id: I07c66df50dbe9fefd95a67b5af9e3f61ce6a18aa Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/30096/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index f487979..a935c27 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -245,6 +245,6 @@ device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI - device pci 1f.6 on end # GbE + device pci 1f.6 off end # GbE end end -- To view, visit https://review.coreboot.org/c/coreboot/+/30096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c66df50dbe9fefd95a67b5af9e3f61ce6a18aa Gerrit-Change-Number: 30096 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Use meaningful Satamode
by Lijian Zhao (Code Review) 07 Dec '18

07 Dec '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30095 Change subject: mb/google/sarien: Use meaningful Satamode ...................................................................... mb/google/sarien: Use meaningful Satamode Define Satamode to AHCI mode instead of 0, make devicetree more readable. BUG=N/A Change-Id: I903545d9487c1409f9008407fe5bee6aa4959b98 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/30095/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index f487979..26d2153 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -17,7 +17,7 @@ register "SaGv" = "3" register "HeciEnabled" = "1" register "SataSalpSupport" = "1" - register "SataMode" = "0" + register "SataMode" = "Sata_AHCI" register "SataPortsEnable[0]" = "0" register "SataPortsEnable[1]" = "1" register "SataPortsEnable[2]" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 5004abf..c5733fb 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -17,7 +17,7 @@ register "SaGv" = "3" register "HeciEnabled" = "1" register "SataSalpSupport" = "1" - register "SataMode" = "0" + register "SataMode" = "Sata_AHCI" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsEnable[2]" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/30095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I903545d9487c1409f9008407fe5bee6aa4959b98 Gerrit-Change-Number: 30095 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Declare SATA Mode clear
by Lijian Zhao (Code Review) 07 Dec '18

07 Dec '18

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30093 to look at the new patch set (#3). Change subject: soc/intel/cannonlake: Declare SATA Mode clear ...................................................................... soc/intel/cannonlake: Declare SATA Mode clear FSP support two SATA modes as AHCI mode (0) and RAID mode (1), make it more clear in header file. Change-Id: I1edcadc0048df839da145260b60f9f7720d981fe Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/chip.h 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/30093/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/30093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1edcadc0048df839da145260b60f9f7720d981fe Gerrit-Change-Number: 30093 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2018