coreboot-gerrit December 2018

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Change in ...coreboot[master]: arch/x86/smbios: Add SMBIOS type for QCA6174A
by Amanda Hwang (Code Review) 11 Dec '18

11 Dec '18

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30150 Change subject: arch/x86/smbios: Add SMBIOS type for QCA6174A ...................................................................... arch/x86/smbios: Add SMBIOS type for QCA6174A BUG=b:118656705 TEST=dmidecode -t 0xf8 and make sure that the correct SMBIOS type information gets returned. Change-Id: I0d1f84898bb4130b55508cc29fa2412ec8bad658 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M src/arch/x86/smbios.c M src/include/smbios.h M src/mainboard/google/kahlee/variants/baseboard/mainboard.c 3 files changed, 75 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/30150/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index c0545ce..5e7e696 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -450,6 +450,21 @@ return ""; } +const char *__weak smbios_bdf_extension(void) +{ + return ""; +} + +u8 __weak smbios_country_flag(void) +{ + return 0; +} + +u16 __weak smbios_country_value(void) +{ + return 0; +} + #ifdef CONFIG_MAINBOARD_FAMILY const char *smbios_mainboard_family(void) { @@ -457,6 +472,28 @@ } #endif /* CONFIG_MAINBOARD_FAMILY */ +static int smbios_write_typef8(unsigned long *current, int handle) +{ + struct smbios_typef8 *t = (struct smbios_typef8 *)*current; + int len = sizeof(struct smbios_typef8); + + printk(BIOS_INFO, "Create SMBIOS type 0xf8\n"); + + memset(t, 0, sizeof(struct smbios_typef8)); + t->type = SMBIOS_QCT_WLAN_CONFIGURATION; + t->handle = handle; + t->length = len - 2; + t->disable_11ac = 0; + t->country_code_flag = smbios_country_flag(); + t->country_code_value = smbios_country_value(); + t->board_file_extension = smbios_add_string(t->eos, smbios_bdf_extension()); + + len = t->length + smbios_string_table_len(t->eos); + *current += len; + return len; +} + + static int smbios_write_type1(unsigned long *current, int handle) { struct smbios_type1 *t = (struct smbios_type1 *)*current; @@ -736,6 +773,9 @@ current = ALIGN(current, 16); tables = current; + update_max(len, max_struct_size, smbios_write_typef8(&current, + handle++)); + update_max(len, max_struct_size, smbios_write_type0(&current, handle++)); update_max(len, max_struct_size, smbios_write_type1(&current, diff --git a/src/include/smbios.h b/src/include/smbios.h index 14badbc..4614897 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -52,6 +52,10 @@ const char *smbios_mainboard_family(void); #endif +const char *smbios_bdf_extension(void); +u8 smbios_country_flag(void); +u16 smbios_country_value(void); + #define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) #define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) #define BIOS_CHARACTERISTICS_PNP (1 << 9) @@ -199,7 +203,8 @@ SMBIOS_SYSTEM_BOOT_INFORMATION = 32, SMBIOS_IPMI_DEVICE_INFORMATION = 38, SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION = 41, - SMBIOS_END_OF_TABLE = 127, + SMBIOS_QCT_WLAN_CONFIGURATION = 0xf8, + SMBIOS_END_OF_TABLE = 127, } smbios_struct_type_t; struct smbios_entry { @@ -521,6 +526,17 @@ u8 eos[2]; } __packed; +struct smbios_typef8 { + u8 type; + u8 length; + u16 handle; + u8 disable_11ac; + u8 country_code_flag; + u16 country_code_value; + u8 board_file_extension; + u8 eos[2]; +} __packed; + void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, struct smbios_type17 *t); diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c index d1a3492..7f2ff54 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c +++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c @@ -97,3 +97,21 @@ return manuf; } + +const char *smbios_bdf_extension(void) +{ + return "BDF_GO_LIARA"; +} + +u8 smbios_country_flag(void) +{ + return 0x00; +} + +u16 smbios_country_value(void) +{ + return 0x00; +} + + + -- To view, visit https://review.coreboot.org/c/coreboot/+/30150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d1f84898bb4130b55508cc29fa2412ec8bad658 Gerrit-Change-Number: 30150 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: siemens/mc_apl4: Add GPIO configuration
by uwe poeche (Code Review) 11 Dec '18

11 Dec '18

Hello Werner Zeh, Mario Scheithauer, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30128 to look at the new patch set (#3). Change subject: siemens/mc_apl4: Add GPIO configuration ...................................................................... siemens/mc_apl4: Add GPIO configuration Add GPIO configuration to match the hardware of mc_apl4. Change-Id: Ia69603f42c57c1cc682550b8eeeab42fbac27563 Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc A src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c 2 files changed, 392 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/30128/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/30128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia69603f42c57c1cc682550b8eeeab42fbac27563 Gerrit-Change-Number: 30128 Gerrit-PatchSet: 3 Gerrit-Owner: uwe poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: uwe poeche <uwe.poeche(a)siemens.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/sarien: Disable unused SATA ports
by Patrick Georgi (Code Review) 11 Dec '18

11 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30091 ) Change subject: mb/google/sarien: Disable unused SATA ports ...................................................................... mb/google/sarien: Disable unused SATA ports Disable SATA port 0 and port 1 as that's not used as SATA on platform. BUG=N/A TEST=Build and boot up fine on google arcada board. Change-Id: I1b8801f7a0f9b7847b85d7c315fa0a2093b32f70 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Reviewed-on: https://review.coreboot.org/c/30091 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Roy Mingi Park <roy.mingi.park(a)intel.com> Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Bora Guvendik: Looks good to me, approved Roy Mingi Park: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 924f51d..ed2c34c 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -18,11 +18,7 @@ register "HeciEnabled" = "1" register "SataSalpSupport" = "1" register "SataMode" = "0" - register "SataPortsEnable[0]" = "0" - register "SataPortsEnable[1]" = "1" register "SataPortsEnable[2]" = "1" - register "SataPortsDevSlp[0]" = "0" - register "SataPortsDevSlp[1]" = "1" register "SataPortsDevSlp[2]" = "1" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/30091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b8801f7a0f9b7847b85d7c315fa0a2093b32f70 Gerrit-Change-Number: 30091 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/sarien: Disable PCH Gigabit LAN
by Patrick Georgi (Code Review) 11 Dec '18

11 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30096 ) Change subject: mb/google/sarien: Disable PCH Gigabit LAN ...................................................................... mb/google/sarien: Disable PCH Gigabit LAN There's no LAN connection on Arcada board, so disable PCH GBE. BUG=N/A Change-Id: I07c66df50dbe9fefd95a67b5af9e3f61ce6a18aa Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Reviewed-on: https://review.coreboot.org/c/30096 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 1 insertion(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Bora Guvendik: Looks good to me, approved diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index fccec9f..924f51d 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -78,11 +78,6 @@ }, }" - # PCIe port 9 for LAN - register "PcieRpEnable[8]" = "1" - register "PcieClkSrcUsage[0]" = "PCIE_CLK_LAN" - register "PcieClkSrcClkReq[0]" = "0" - # PCIe port 10 for M.2 2230 WLAN register "PcieRpEnable[9]" = "1" register "PcieClkSrcUsage[2]" = "9" @@ -250,6 +245,6 @@ device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI - device pci 1f.6 on end # GbE + device pci 1f.6 off end # GbE end end -- To view, visit https://review.coreboot.org/c/coreboot/+/30096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c66df50dbe9fefd95a67b5af9e3f61ce6a18aa Gerrit-Change-Number: 30096 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/intel/braswell/northcluster.c: Fix typo
by Patrick Georgi (Code Review) 11 Dec '18

11 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30125 ) Change subject: soc/intel/braswell/northcluster.c: Fix typo ...................................................................... soc/intel/braswell/northcluster.c: Fix typo Correct typo of 'resource' BUG=N/A TEST=N/A Change-Id: I79dde87007759b7cab92061df37fd3a19d5e3d1f Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/30125 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/soc/intel/braswell/northcluster.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tristan Corrick: Looks good to me, approved diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index dcd98b5..1e5204e 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -53,7 +53,7 @@ * +--------------------------+ 0 * * Note that there are really only a few regions that need to enumerated w.r.t. - * coreboot's resrouce model: + * coreboot's resource model: * * +--------------------------+ BMBOUND_HI * | Cacheable/Usable | -- To view, visit https://review.coreboot.org/c/coreboot/+/30125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79dde87007759b7cab92061df37fd3a19d5e3d1f Gerrit-Change-Number: 30125 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: sb/intel/lynxpoint: Remove incomplete SATA ACPI code
by Tristan Corrick (Code Review) 11 Dec '18

11 Dec '18

Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30149 ) Change subject: sb/intel/lynxpoint: Remove incomplete SATA ACPI code ...................................................................... Patch Set 2: > Patch Set 1: Code-Review+1 > > Please add an inline comment that legacy mode isn't supported yet. Done. -- To view, visit https://review.coreboot.org/c/coreboot/+/30149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I808a9dff7b9ba34239ffd95fa4cb9b39b10c4b62 Gerrit-Change-Number: 30149 Gerrit-PatchSet: 2 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Dec 2018 07:45:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/lynxpoint: Remove incomplete SATA ACPI code
by Tristan Corrick (Code Review) 11 Dec '18

11 Dec '18

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30149 to look at the new patch set (#2). Change subject: sb/intel/lynxpoint: Remove incomplete SATA ACPI code ...................................................................... sb/intel/lynxpoint: Remove incomplete SATA ACPI code The existing SATA ACPI code for Lynx Point implements some methods and devices, but not completely. These methods are optional and only used in IDE mode. The code was likely copied from bd82x6x, where it has since been removed. As a result, many remarks produced by iasl about unreferenced objects are eliminated. Tested on an ASRock H81M-HDS and an Acer C720. No issues with SATA were observed. Change-Id: I808a9dff7b9ba34239ffd95fa4cb9b39b10c4b62 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/southbridge/intel/lynxpoint/acpi/sata.asl 1 file changed, 2 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/30149/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I808a9dff7b9ba34239ffd95fa4cb9b39b10c4b62 Gerrit-Change-Number: 30149 Gerrit-PatchSet: 2 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/braswell: Configure IO APIC
by Frans Hendriks (Code Review) 11 Dec '18

11 Dec '18

Hello build bot (Jenkins), Hannah Williams, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29423 to look at the new patch set (#6). Change subject: soc/intel/braswell: Configure IO APIC ...................................................................... soc/intel/braswell: Configure IO APIC IO APIC is not configured. Add sc_enable_ioapic() copied from fsp_baytrail Soc. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/include/soc/lpc.h M src/soc/intel/braswell/southcluster.c 3 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/29423/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/29423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d Gerrit-Change-Number: 29423 Gerrit-PatchSet: 6 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: src/northbridge: Get rid of device_t
by build bot (Jenkins) (Code Review) 11 Dec '18

11 Dec '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30046 ) Change subject: src/northbridge: Get rid of device_t ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/30046/3/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c: https://review.coreboot.org/#/c/30046/3/src/northbridge/amd/amdmct/mct_ddr3… PS3, Line 152: static uint32_t read_amd_dct_index_register_dct(struct device *dev, uint8_t node, line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/30046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I862bad4e889af3d25a771637a9ffc4f9d0b26d33 Gerrit-Change-Number: 30046 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Dec 2018 07:15:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/asus/maximus_iv_gene-z: Select NO_UART_ON_SUPERIO
by Patrick Rudolph (Code Review) 11 Dec '18

11 Dec '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30148 ) Change subject: mb/asus/maximus_iv_gene-z: Select NO_UART_ON_SUPERIO ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d84f373831381da79022638e1082adf68f47aad Gerrit-Change-Number: 30148 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Dec 2018 06:57:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2018