coreboot-gerrit December 2018

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Change in ...coreboot[master]: Documentation/mainboard/lenovo/t420.md: fix typo
by Michael Bacarella (Code Review) 11 Dec '18

11 Dec '18

Michael Bacarella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30170 Change subject: Documentation/mainboard/lenovo/t420.md: fix typo ...................................................................... Documentation/mainboard/lenovo/t420.md: fix typo Picture of mainboard wasn't displaying. Signed-off-by: Michael Bacarella <michael.bacarella(a)gmail.com> Change-Id: Ia70f5d5ad2fdf4c0e811ab92a817375a89694122 --- M Documentation/mainboard/lenovo/t420.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/30170/1 diff --git a/Documentation/mainboard/lenovo/t420.md b/Documentation/mainboard/lenovo/t420.md index 6ebff0e..9bf90b9 100644 --- a/Documentation/mainboard/lenovo/t420.md +++ b/Documentation/mainboard/lenovo/t420.md @@ -7,7 +7,7 @@ Below is a picture of IC on the mainboard, with the pinouts labeled. -[t420_chip_location]: t420_chip_location.jpg +![t420_chip_location]: t420_chip_location.jpg The chip will either be a Macronix MX25L6404E (shown above) or a Winbond W25Q64CVSIG. Do not rely on dots painted in the corner of the chip (such as -- To view, visit https://review.coreboot.org/c/coreboot/+/30170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia70f5d5ad2fdf4c0e811ab92a817375a89694122 Gerrit-Change-Number: 30170 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Bacarella <michael.bacarella(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Makefile.inc: Avoid race condition when using 'make -j<N>'
by Nico Huber (Code Review) 11 Dec '18

11 Dec '18

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29984 ) Change subject: Makefile.inc: Avoid race condition when using 'make -j<N>' ...................................................................... Makefile.inc: Avoid race condition when using 'make -j<N>' When building coreboot from scratch with 'make -j4', I sometimes see this error: CREATE build/mainboard/emulation/qemu-riscv/cbfs-file.wblRgZ.out (from /.../coreboot/.config) HOSTCC cbfstool/cbfstool (link) make[1]: execvp: build/util/kconfig/conf: Permission denied make[1]: *** [/.../coreboot/util/kconfig/Makefile:92: savedefconfig] Error 127 It happens, I think, because the rule generated by cbfs-files-processor-defconfig runs 'make savedefconfig', which builds build/util/kconfig/conf, and something also builds it, at the same time. Fix this case, by making this rule depend on $(objutil)/kconfig/conf. The same fix is also precautiously applied to the rule for $(KCONFIG_AUTOHEADER) in Makefile. Change-Id: Ie93eda567f88ca08c97df7e70cdff5b07442747d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-on: https://review.coreboot.org/c/29984 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M Makefile M Makefile.inc 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/Makefile b/Makefile index 1d4a488..f12b616 100644 --- a/Makefile +++ b/Makefile @@ -176,7 +176,7 @@ .SECONDEXPANSION: .DELETE_ON_ERROR: -$(KCONFIG_AUTOHEADER): $(KCONFIG_CONFIG) +$(KCONFIG_AUTOHEADER): $(KCONFIG_CONFIG) $(objutil)/kconfig/conf +$(MAKE) oldconfig # Add a new class of source/object files to the build system diff --git a/Makefile.inc b/Makefile.inc index 1d6a671..f684f59 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -287,7 +287,7 @@ # arg1: input # arg2: output cbfs-files-processor-defconfig= \ - $(eval $(2): $(1) $(obj)/build.h; \ + $(eval $(2): $(1) $(obj)/build.h $(objutil)/kconfig/conf; \ +printf " CREATE $(2) (from $(1))\n"; \ printf "\# This image was built using coreboot " > $(2).tmp && \ grep "\<COREBOOT_VERSION\>" $(obj)/build.h |cut -d\" -f2 >> $(2).tmp && \ -- To view, visit https://review.coreboot.org/c/coreboot/+/29984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie93eda567f88ca08c97df7e70cdff5b07442747d Gerrit-Change-Number: 29984 Gerrit-PatchSet: 3 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/hatch: Creating skeleton directories and files
by Shelley Chen (Code Review) 11 Dec '18

11 Dec '18

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30169 Change subject: mb/google/hatch: Creating skeleton directories and files ...................................................................... mb/google/hatch: Creating skeleton directories and files Creating skeleton files and directories in mainboard for the new Hatch board. This is to facilitate development for different parties involved. BUG=None BRANCH=None TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I5fc60c178f83034abe5d846d0f4169072b66f448 Signed-off-by: Shelley Chen <shchen(a)google.com> --- A src/mainboard/google/hatch/Kconfig A src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/Makefile.inc A src/mainboard/google/hatch/acpi_tables.c A src/mainboard/google/hatch/board_info.txt A src/mainboard/google/hatch/bootblock.c A src/mainboard/google/hatch/chromeos.c A src/mainboard/google/hatch/chromeos.fmd A src/mainboard/google/hatch/dsdt.asl A src/mainboard/google/hatch/ramstage.c A src/mainboard/google/hatch/romstage.c A src/mainboard/google/hatch/smihandler.c A src/mainboard/google/hatch/variants/baseboard/Makefile.inc A src/mainboard/google/hatch/variants/baseboard/gpio.c A src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h A src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/hatch/variants/hatch/Makefile.inc A src/mainboard/google/hatch/variants/hatch/gpio.c A src/mainboard/google/hatch/variants/hatch/include/variant/ec.h A src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h A src/mainboard/google/hatch/variants/hatch/overridetree.cb 21 files changed, 652 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/30169/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig new file mode 100644 index 0000000..1028f2f --- /dev/null +++ b/src/mainboard/google/hatch/Kconfig @@ -0,0 +1,78 @@ + +config BOARD_GOOGLE_BASEBOARD_HATCH + def_bool n + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_SPI_ACPI + select EC_GOOGLE_CHROMEEC + select GENERIC_SPD_BIN + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_I2C_TPM_CR50 + select MAINBOARD_HAS_TPM2 + select SOC_INTEL_CANNONLAKE_MEMCFG_INIT + select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK + select SOC_INTEL_COFFEELAKE + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + select TPM2 + +if BOARD_GOOGLE_BASEBOARD_HATCH + +config CHROMEOS + bool + default y + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_DEV_BOOT_LEGACY + select GBB_FLAG_FORCE_MANUAL_RECOVERY + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config GBB_HWID + string + depends on CHROMEOS + default "HATCH TEST 1823" if BOARD_GOOGLE_HATCH + +config MAINBOARD_DIR + string + default "google/hatch" + +config MAINBOARD_FAMILY + string + default "Google_Hatch" if BOARD_GOOGLE_HATCH + +config MAINBOARD_PART_NUMBER + string + default "Hatch" if BOARD_GOOGLE_HATCH + +config MAINBOARD_VENDOR + string + default "Google" + +config MAX_CPUS + int + default 8 + +config VARIANT_DIR + string + default "hatch" if BOARD_GOOGLE_HATCH + +config DEVICETREE + string + default "variants/${CONFIG_VARIANT_DIR}/overridetree.cb" + +config VBOOT + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + select VBOOT_LID_SWITCH + +endif # BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name new file mode 100644 index 0000000..79edb63 --- /dev/null +++ b/src/mainboard/google/hatch/Kconfig.name @@ -0,0 +1,5 @@ +comment "Hatch" + +config BOARD_GOOGLE_HATCH + bool "-> Hatch" + select BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc new file mode 100644 index 0000000..54e4281 --- /dev/null +++ b/src/mainboard/google/hatch/Makefile.inc @@ -0,0 +1,33 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2018 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c + +ramstage-y += ramstage.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +romstage-y += romstage.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/hatch/acpi_tables.c b/src/mainboard/google/hatch/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/hatch/acpi_tables.c diff --git a/src/mainboard/google/hatch/board_info.txt b/src/mainboard/google/hatch/board_info.txt new file mode 100644 index 0000000..4e12c96 --- /dev/null +++ b/src/mainboard/google/hatch/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Hatch +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/hatch/bootblock.c b/src/mainboard/google/hatch/bootblock.c new file mode 100644 index 0000000..d349e587 --- /dev/null +++ b/src/mainboard/google/hatch/bootblock.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <bootblock_common.h> +#include <ec/ec.h> +#include <soc/gpio.h> + +static void early_config_gpio(void) +{ + const struct pad_config *early_gpio_table; + size_t num_gpios = 0; + + early_gpio_table = variant_early_gpio_table(&num_gpios); + gpio_configure_pads(early_gpio_table, num_gpios); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); +} diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c new file mode 100644 index 0000000..644c247 --- /dev/null +++ b/src/mainboard/google/hatch/chromeos.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/variants.h> +#include <boot/coreboot_tables.h> +#include <ec/google/chromeec/ec.h> +#include <gpio.h> +#include <rules.h> +#include <soc/gpio.h> +#include <variant/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {-1, ACTIVE_HIGH, 0, "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +static int cros_get_gpio_value(int type) +{ + const struct cros_gpio *cros_gpios; + size_t i, num_gpios = 0; + + cros_gpios = variant_cros_gpios(&num_gpios); + + for (i = 0; i < num_gpios; i++) { + const struct cros_gpio *gpio = &cros_gpios[i]; + if (gpio->type == type) { + int state = gpio_get(gpio->gpio_num); + if (gpio->polarity == CROS_GPIO_ACTIVE_LOW) + return !state; + else + return state; + } + } + return 0; +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *cros_gpios; + size_t num_gpios = 0; + + cros_gpios = variant_cros_gpios(&num_gpios); + + chromeos_acpi_gpio_generate(cros_gpios, num_gpios); +} + +int get_write_protect_state(void) +{ + return cros_get_gpio_value(CROS_GPIO_WP); +} + +int get_recovery_mode_switch(void) +{ + return cros_get_gpio_value(CROS_GPIO_REC); +} + +int get_lid_switch(void) +{ + return 1; +} diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd new file mode 100644 index 0000000..6631769 --- /dev/null +++ b/src/mainboard/google/hatch/chromeos.fmd @@ -0,0 +1,46 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x1000000 { + SI_DESC@0x0 0x1000 + SI_EC@0x1000 0x100000 + SI_GBE@0x101000 0x2000 + SI_ME@0x103000 0xefd000 + } + SI_BIOS@0x1000000 0x1000000 { + RW_SECTION_A@0x0 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x26ffc0 + RW_FWID_A@0x27ffc0 0x40 + } + RW_SECTION_B@0x280000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x26ffc0 + RW_FWID_B@0x27ffc0 0x40 + } + RW_MISC@0x500000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x28000 0x2000 + RW_NVRAM@0x2a000 0x6000 + } + CONSOLE@0x530000 0x20000 + RW_LEGACY(CBFS)@0x550000 0x6b0000 + WP_RO@0xc00000 0x400000 { + RO_VPD@0x0 0x4000 + RO_UNUSED@0x4000 0xc000 + RO_SECTION@0x10000 0x3f0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x300000 + } + } + } +} diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl new file mode 100644 index 0000000..61d0e86 --- /dev/null +++ b/src/mainboard/google/hatch/dsdt.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variant/ec.h> + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ +} diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c new file mode 100644 index 0000000..0027627 --- /dev/null +++ b/src/mainboard/google/hatch/ramstage.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/variants.h> +#include <soc/ramstage.h> +#include <variant/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + const struct pad_config *gpio_table; + size_t num_gpios; + + gpio_table = variant_base_gpio_table(&num_gpios); + gpio_configure_pads(gpio_table, num_gpios); +} + +static void mainboard_enable(struct device *dev) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c new file mode 100644 index 0000000..ecc8f3c --- /dev/null +++ b/src/mainboard/google/hatch/romstage.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ +} diff --git a/src/mainboard/google/hatch/smihandler.c b/src/mainboard/google/hatch/smihandler.c new file mode 100644 index 0000000..f8f43eb --- /dev/null +++ b/src/mainboard/google/hatch/smihandler.c @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/mainboard/google/hatch/variants/baseboard/Makefile.inc b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc new file mode 100644 index 0000000..dffacbb --- /dev/null +++ b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc @@ -0,0 +1,7 @@ +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c + +verstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c new file mode 100644 index 0000000..a0ac059 --- /dev/null +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +static const struct pad_config gpio_table[] = { +}; + +const struct pad_config *__weak variant_base_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *__weak variant_override_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + +/* GPIOs needed prior to ramstage. */ +static const struct pad_config early_gpio_table[] = { +}; + +const struct pad_config *__weak +variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { +}; + +const struct cros_gpio *__weak variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000..c9f8b4c --- /dev/null +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef BASEBOARD_GPIO_H +#define BASEBOARD_GPIO_H + +#include <soc/gpio.h> + +#endif /* BASEBOARD_GPIO_H */ diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..18f90488 --- /dev/null +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef BASEBOARD_VARIANTS_H +#define BASEBOARD_VARIANTS_H + +#include <soc/gpio.h> +#include <stdint.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* The next set of functions return the gpio table and fill in the number of + * entries for each table. */ +const struct pad_config *variant_base_gpio_table(size_t *num); +const struct pad_config *variant_override_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); +const struct pad_config *variant_sleep_gpio_table(size_t *num, int slp_typ); + +/* Return memory SKU for the board. */ +size_t variant_memory_sku(void); + +/* Return ChromeOS gpio table and fill in number of entries. */ +const struct cros_gpio *variant_cros_gpios(size_t *num); + +/* Modify devictree settings during ramstage. */ +struct device; +void variant_update_devtree(struct device *dev); + +#endif /* BASEBOARD_VARIANTS_H */ diff --git a/src/mainboard/google/hatch/variants/hatch/Makefile.inc b/src/mainboard/google/hatch/variants/hatch/Makefile.inc new file mode 100644 index 0000000..d4d8537 --- /dev/null +++ b/src/mainboard/google/hatch/variants/hatch/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2018 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c new file mode 100644 index 0000000..24535f5 --- /dev/null +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { +}; + +const struct pad_config *variant_base_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/hatch/include/variant/ec.h b/src/mainboard/google/hatch/variants/hatch/include/variant/ec.h new file mode 100644 index 0000000..c1622c6 --- /dev/null +++ b/src/mainboard/google/hatch/variants/hatch/include/variant/ec.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#endif diff --git a/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h b/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h new file mode 100644 index 0000000..49bb48c --- /dev/null +++ b/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +//#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb new file mode 100644 index 0000000..88df092 --- /dev/null +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -0,0 +1,52 @@ +chip soc/intel/cannonlake + device domain 0 on + device pci 00.0 off end # Host Bridge + device pci 02.0 off end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 12.0 off end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 off end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.5 off end # SDCard + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 off end # SATA + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Port 1 (USB) + device pci 1c.1 off end # PCI Express Port 2 (USB) + device pci 1c.2 off end # PCI Express Port 3 (USB) + device pci 1c.3 off end # PCI Express Port 4 (USB) + device pci 1c.4 off end # PCI Express Port 5 (USB) + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 (x4) + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 off end # LPC/eSPI + device pci 1f.1 off end # P2SB + device pci 1f.2 off end # Power Management Controller + device pci 1f.3 off end # Intel HDA + device pci 1f.4 off end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.6 off end # GbE + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/30169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fc60c178f83034abe5d846d0f4169072b66f448 Gerrit-Change-Number: 30169 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [RFC] arch/riscv/stdint.h: Check the size of (u)intptr_t
by build bot (Jenkins) (Code Review) 11 Dec '18

11 Dec '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30168 ) Change subject: [RFC] arch/riscv/stdint.h: Check the size of (u)intptr_t ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/30168/1/src/arch/riscv/include/stdint.h File src/arch/riscv/include/stdint.h: https://review.coreboot.org/#/c/30168/1/src/arch/riscv/include/stdint.h@76 PS1, Line 76: _Static_assert(sizeof(uintptr_t) == sizeof(void *), "Size of uintptr_t is wrong"); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/30168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5583ba58eeca3a37229b41b6517adfc12b2fddce Gerrit-Change-Number: 30168 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Dec 2018 15:50:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [RFC] arch/riscv/stdint.h: Check the size of (u)intptr_t
by Jonathan Neuschäfer (Code Review) 11 Dec '18

11 Dec '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30168 Change subject: [RFC] arch/riscv/stdint.h: Check the size of (u)intptr_t ...................................................................... [RFC] arch/riscv/stdint.h: Check the size of (u)intptr_t TODO: Since (u)intptr_t and these invariants are not architecture specific, the assertions should probably be moved to a central place, but where? Change-Id: I5583ba58eeca3a37229b41b6517adfc12b2fddce Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/arch/riscv/include/stdint.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/30168/1 diff --git a/src/arch/riscv/include/stdint.h b/src/arch/riscv/include/stdint.h index 76f0d1b..0062a8e 100644 --- a/src/arch/riscv/include/stdint.h +++ b/src/arch/riscv/include/stdint.h @@ -72,6 +72,8 @@ /* Types for `void *' pointers. */ typedef long intptr_t; typedef unsigned long uintptr_t; +_Static_assert(sizeof(intptr_t) == sizeof(void *), "Size of intptr_t is wrong"); +_Static_assert(sizeof(uintptr_t) == sizeof(void *), "Size of uintptr_t is wrong"); /* FIXME: This is used in some print code and may be removed in the future. */ #define PRIu64 "llu" -- To view, visit https://review.coreboot.org/c/coreboot/+/30168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5583ba58eeca3a37229b41b6517adfc12b2fddce Gerrit-Change-Number: 30168 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Fix typos involving "the the"
by build bot (Jenkins) (Code Review) 11 Dec '18

11 Dec '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30160 ) Change subject: Fix typos involving "the the" ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/30160/1/src/device/oprom/x86emu/ops.c File src/device/oprom/x86emu/ops.c: https://review.coreboot.org/#/c/30160/1/src/device/oprom/x86emu/ops.c@61 PS1, Line 61: * subroutines fall into the latter category. The decode_* fall space prohibited after that '*' (ctx:ExW) https://review.coreboot.org/#/c/30160/1/src/device/oprom/x86emu/ops.c@61 PS1, Line 61: * subroutines fall into the latter category. The decode_* fall need consistent spacing around '*' (ctx:VxW) -- To view, visit https://review.coreboot.org/c/coreboot/+/30160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I179264ee6681a7ba4488b9f1c6bce1a19b4e1772 Gerrit-Change-Number: 30160 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Dec 2018 15:23:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/lint/spelling.txt: Protect "acknowledgement" entry
by Jonathan Neuschäfer (Code Review) 11 Dec '18

11 Dec '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30167 Change subject: util/lint/spelling.txt: Protect "acknowledgement" entry ...................................................................... util/lint/spelling.txt: Protect "acknowledgement" entry In commit eceba31c7f ("util/lint: Set "acknowledgement" correct"), the word "acknowledgement" was removed from util/lint/spelling.txt. A more robust solution is to comment it out, as done for "sepc" in commit afa5ec8d5f ("util/lint: Update spelling.txt to latest linux version"). Change-Id: Ia976dedc9b31190d22e7b946f14709d5c4577f71 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M util/lint/spelling.txt 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/30167/1 diff --git a/util/lint/spelling.txt b/util/lint/spelling.txt index cc42db4..118a435 100644 --- a/util/lint/spelling.txt +++ b/util/lint/spelling.txt @@ -7,7 +7,7 @@ # The format of each line is: # mistake||correction # -# Note that sepc has been commented out. +# Note that "sepc" and "acknowledgement" have been commented out. abandonning||abandoning abigious||ambiguous abitrate||arbitrate @@ -42,6 +42,7 @@ acitions||actions acitve||active acknowldegement||acknowledgment +#acknowledgement||acknowledgment ackowledge||acknowledge ackowledged||acknowledged acording||according -- To view, visit https://review.coreboot.org/c/coreboot/+/30167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia976dedc9b31190d22e7b946f14709d5c4577f71 Gerrit-Change-Number: 30167 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/kahlee/liara: Document why IOMMU is disabled
by Jonathan Neuschäfer (Code Review) 11 Dec '18

11 Dec '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30166 Change subject: mb/google/kahlee/liara: Document why IOMMU is disabled ...................................................................... mb/google/kahlee/liara: Document why IOMMU is disabled Commit d80884ea5a ("mb/google/kahlee: Disable IOMMU") disabled the IOMMU in all kahlee variants, but omitted the explaining comment only in liara's devicetree.cb. Copy this comment to liara. Change-Id: I564013a16217445003467e2a0579abd50597b205 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/mainboard/google/kahlee/variants/liara/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/30166/1 diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb index eef984a..bc6c643 100644 --- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb @@ -60,7 +60,7 @@ end device domain 0 on device pci 0.0 on end # Root Complex - device pci 0.2 off end # IOMMU + device pci 0.2 off end # IOMMU (Disabled for performance and battery) device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge -- To view, visit https://review.coreboot.org/c/coreboot/+/30166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I564013a16217445003467e2a0579abd50597b205 Gerrit-Change-Number: 30166 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation/lesson2: Add quotes to increase readability
by Jonathan Neuschäfer (Code Review) 11 Dec '18

11 Dec '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30165 Change subject: Documentation/lesson2: Add quotes to increase readability ...................................................................... Documentation/lesson2: Add quotes to increase readability Change-Id: Ibb041965bb9a97d153ace1f697607e524a6f50ac Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M Documentation/lessons/lesson2.md 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/30165/1 diff --git a/Documentation/lessons/lesson2.md b/Documentation/lessons/lesson2.md index a95dd80..d3e0d8c 100644 --- a/Documentation/lessons/lesson2.md +++ b/Documentation/lessons/lesson2.md @@ -65,8 +65,8 @@ to click the next page arrow at the bottom a few times to find it. If you are using SSH keys, select **ssh** from the tabs under "Project -coreboot" and run the clone with commit-msg hook command that's provided. This -should prompt you for your id_rsa passphrase, if you previously set one. +coreboot" and run the "clone with commit-msg hook" command that's provided. +This should prompt you for your id_rsa passphrase, if you previously set one. If you are using HTTP, instead, select **http** from the tabs under "Project coreboot" and run the command that appears -- To view, visit https://review.coreboot.org/c/coreboot/+/30165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb041965bb9a97d153ace1f697607e524a6f50ac Gerrit-Change-Number: 30165 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/riscv: Don't hardcode CSR numbers anymore
by Jonathan Neuschäfer (Code Review) 11 Dec '18

11 Dec '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30164 Change subject: arch/riscv: Don't hardcode CSR numbers anymore ...................................................................... arch/riscv: Don't hardcode CSR numbers anymore They are hopefully stable enough by now. TEST=Building with for emulation/spike-riscv with BUILD_TIMELESS, with and without this patch, results in the same coreboot.rom. Change-Id: Ie6747c7eeea6cd8fd2138c5ba535a08c5add9038 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/arch/riscv/virtual_memory.c 1 file changed, 2 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/30164/1 diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index d9bae2a..0061847 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -59,11 +59,6 @@ set_csr(medeleg, delegate); } - // Enable all user/supervisor-mode counters using - // v1.10 register addresses. - // They moved from the earlier spec. - // Until we trust our toolchain use the hardcoded constants. - // These were in flux and people who get the older toolchain - // will have difficult-to-debug failures. - write_csr(/*mcounteren*/0x306, 7); + // Enable all user/supervisor-mode counters + write_csr(mcounteren, 7); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6747c7eeea6cd8fd2138c5ba535a08c5add9038 Gerrit-Change-Number: 30164 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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