coreboot-gerrit December 2018

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Change in ...coreboot[master]: src/mb/google/*/Kconfig: Consistently use $(...) for variables
by Jonathan Neuschäfer (Code Review) 11 Dec '18

11 Dec '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30163 Change subject: src/mb/google/*/Kconfig: Consistently use $(...) for variables ...................................................................... src/mb/google/*/Kconfig: Consistently use $(...) for variables Using ${...} in some places is slightly confusing. Fixes: 395cbb4f97 ("mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetree") Change-Id: Id0856a10d92786a41d45ca697945699f6f4c1f4c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/mainboard/google/cyan/Kconfig M src/mainboard/google/glados/Kconfig M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/sarien/Kconfig 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/30163/1 diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 917a66e..1d9b7b7 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -73,7 +73,7 @@ config DEVICETREE string - default "variants/${CONFIG_VARIANT_DIR}/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" config VGA_BIOS_FILE string diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index c5a80d4..80cc0f3 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -60,7 +60,7 @@ config DEVICETREE string - default "variants/${CONFIG_VARIANT_DIR}/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" config MAX_CPUS int diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 97d15f5..13ad0b9 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -72,7 +72,7 @@ config DEVICETREE string - default "variants/${CONFIG_VARIANT_DIR}/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" config MAINBOARD_FAMILY string diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index c9e4c0b..c0bd1d8 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -88,7 +88,7 @@ config DEVICETREE string - default "variants/${CONFIG_VARIANT_DIR}/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" config VBOOT select HAS_RECOVERY_MRC_CACHE -- To view, visit https://review.coreboot.org/c/coreboot/+/30163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0856a10d92786a41d45ca697945699f6f4c1f4c Gerrit-Change-Number: 30163 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/util_readme: Don't recommend running this script with "sh"
by Jonathan Neuschäfer (Code Review) 11 Dec '18

11 Dec '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30162 Change subject: util/util_readme: Don't recommend running this script with "sh" ...................................................................... util/util_readme: Don't recommend running this script with "sh" util/util_readme/util_readme.sh is specifically a bash script and requires bash-specific features such as "[[". It doesn't work when run with a "sh" shell that only implements POSIX features, such as dash. Thus, tell the user to run the script directly, in which case the #! line is used. Change-Id: I5706ffe857c5a148e9776571a377ad8647f9a4c2 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M util/util_readme/util_readme.sh 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/30162/1 diff --git a/util/util_readme/util_readme.sh b/util/util_readme/util_readme.sh index cdd94dc..af688c4 100755 --- a/util/util_readme/util_readme.sh +++ b/util/util_readme/util_readme.sh @@ -4,7 +4,7 @@ # in `./util` subdirectories # # Execute from root of project. Example: -# `sh util/util_readme/util_readme.sh` +# `util/util_readme/util_readme.sh` UTIL_README_DIR="$(cd "$(dirname "$0")" || exit; pwd -P)" UTIL_DIR=$(dirname "$UTIL_README_DIR") -- To view, visit https://review.coreboot.org/c/coreboot/+/30162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5706ffe857c5a148e9776571a377ad8647f9a4c2 Gerrit-Change-Number: 30162 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/bucts: Add a description.md file
by Jonathan Neuschäfer (Code Review) 11 Dec '18

11 Dec '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30161 Change subject: util/bucts: Add a description.md file ...................................................................... util/bucts: Add a description.md file Change-Id: I367703ffcd8d10dec0c67b61c9ebbefd497424fd Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M Documentation/util.md M util/README.md A util/bucts/description.md 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/30161/1 diff --git a/Documentation/util.md b/Documentation/util.md index d76c294..c63e801 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -18,6 +18,7 @@ `Yacc` * __board_status__ - Tools to collect logs and upload them to the board status repository `Bash` `Go` +* __bucts__ - A tool to manipulate the BUC.TS bit on Intel targets. `C` * __cavium__ - Devicetree_convert Tool to convert a DTB to a static C file `Python` * __cbfstool__ diff --git a/util/README.md b/util/README.md index 2fe0afc..bd1398b 100644 --- a/util/README.md +++ b/util/README.md @@ -16,6 +16,7 @@ `Yacc` * __board_status__ - Tools to collect logs and upload them to the board status repository `Bash` `Go` +* __bucts__ - A tool to manipulate the BUC.TS bit on Intel targets. `C` * __cavium__ - Devicetree_convert Tool to convert a DTB to a static C file `Python` * __cbfstool__ diff --git a/util/bucts/description.md b/util/bucts/description.md new file mode 100644 index 0000000..e777e5b --- /dev/null +++ b/util/bucts/description.md @@ -0,0 +1 @@ +A tool to manipulate the BUC.TS bit on Intel targets. `C` -- To view, visit https://review.coreboot.org/c/coreboot/+/30161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I367703ffcd8d10dec0c67b61c9ebbefd497424fd Gerrit-Change-Number: 30161 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Fix typos involving "the the"
by Jonathan Neuschäfer (Code Review) 11 Dec '18

11 Dec '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30160 Change subject: Fix typos involving "the the" ...................................................................... Fix typos involving "the the" Change-Id: I179264ee6681a7ba4488b9f1c6bce1a19b4e1772 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M Documentation/Intel/development.html M Documentation/cbfs.txt M Documentation/getting_started/gerrit_guidelines.md M Makefile.inc M payloads/libpayload/curses/PDCurses/pdcurses/clear.c M src/device/oprom/x86emu/ops.c M src/drivers/intel/fsp2_0/hob_verify.c M src/include/cpu/intel/microcode.h M src/northbridge/intel/haswell/gma.c M src/soc/amd/common/block/include/amdblocks/dimm_spd.h M src/soc/amd/stoneyridge/Kconfig M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/pi/hudson/Kconfig M src/vendorcode/amd/agesa/f12/Proc/Mem/mfs3.h M src/vendorcode/amd/agesa/f14/Proc/Mem/mfs3.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfs3.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfs3.h M src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test.c M src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-gsern.h M src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-rvu.h M src/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Uefi/UefiMultiPhase.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/DxeServicesLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/ExtractGuidedSectionLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/UefiLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Smbios.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Uefi/UefiMultiPhase.h M src/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Uefi/UefiMultiPhase.h 27 files changed, 51 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/30160/1 diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index 24b2fa9..92b1d4b 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -264,7 +264,7 @@ <ul> <li>MemoryInit UPD values are correct</li> <li>MemoryInit returns 0 (success) and</li> - <li>The the message "ERROR - coreboot's requirements not met by FSP binary!" + <li>The message "ERROR - coreboot's requirements not met by FSP binary!" is not displayed </li> </ul> @@ -324,7 +324,7 @@ <ul> <li>MemoryInit UPD values are correct</li> <li>MemoryInit returns 0 (success) and</li> - <li>The the message "ERROR - coreboot's requirements not met by FSP binary!" + <li>The message "ERROR - coreboot's requirements not met by FSP binary!" is not displayed </li> </ul> @@ -374,4 +374,4 @@ <hr> <p>Modified: 4 March 2016</p> </body> -</html> \ No newline at end of file +</html> diff --git a/Documentation/cbfs.txt b/Documentation/cbfs.txt index 6d4e387..831e882 100644 --- a/Documentation/cbfs.txt +++ b/Documentation/cbfs.txt @@ -174,7 +174,7 @@ regards to the erase block sizes on the ROM - allowing one to replace a component at runtime without disturbing the others. -'offset' is the offset of the the first CBFS component (from the start of +'offset' is the offset of the first CBFS component (from the start of the ROM). This is to allow for arbitrary space to be left at the beginning of the ROM for things like embedded controller firmware. diff --git a/Documentation/getting_started/gerrit_guidelines.md b/Documentation/getting_started/gerrit_guidelines.md index 9210c84..b0a9609 100644 --- a/Documentation/getting_started/gerrit_guidelines.md +++ b/Documentation/getting_started/gerrit_guidelines.md @@ -150,7 +150,7 @@ gerrit. Topics can be set for individual patches in gerrit by going into the patch and clicking on the icon next to the topic line. Topics can also be set when you push the patches into gerrit. For example, to push a set of -commits with the the i915-kernel-x60 set, use the command: +commits with the i915-kernel-x60 set, use the command: git push origin HEAD:refs/for/master/i915-kernel-x60 * If one of your patches isn't ready to be merged, make sure it's obvious diff --git a/Makefile.inc b/Makefile.inc index 1d6a671..350f4d0 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -120,7 +120,7 @@ # values are space separated if using more than one value # # int-add: adds an arbitrary length list of integers -# int-subtract: subtracts the the second of two integers from the first +# int-subtract: subtracts the second of two integers from the first # int-multiply: multiplies an arbitrary length list of integers # int-divide: divides the first integer by the second # int-remainder: arithmetic remainder of the first number divided by the second diff --git a/payloads/libpayload/curses/PDCurses/pdcurses/clear.c b/payloads/libpayload/curses/PDCurses/pdcurses/clear.c index 75426e2..11295e3 100644 --- a/payloads/libpayload/curses/PDCurses/pdcurses/clear.c +++ b/payloads/libpayload/curses/PDCurses/pdcurses/clear.c @@ -23,7 +23,7 @@ every cell of the window. clear() and wclear() are similar to erase() and werase(), but - they also call clearok() to ensure that the the window is + they also call clearok() to ensure that the window is cleared on the next wrefresh(). clrtobot() and wclrtobot() clear the window from the current diff --git a/src/device/oprom/x86emu/ops.c b/src/device/oprom/x86emu/ops.c index 9f89028..eeaa203 100644 --- a/src/device/oprom/x86emu/ops.c +++ b/src/device/oprom/x86emu/ops.c @@ -58,7 +58,7 @@ * modularize it, was basically: 1) no unnecessary subroutine calls, * 2) no routines more than about 200 lines in size, and 3) modularize * any code that I might not get right the first time. The fetch_* -* subroutines fall into the latter category. The The decode_* fall +* subroutines fall into the latter category. The decode_* fall * into the second category. The coding of the "switch(mod){ .... }" * in many of the subroutines below falls into the first category. * Especially, the coding of {add,and,or,sub,...}_{byte,word} diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c index 2841027..317b2c9 100644 --- a/src/drivers/intel/fsp2_0/hob_verify.c +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -37,7 +37,7 @@ if (fsp_find_reserved_memory(&fsp_mem)) die("9.1: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n"); - /* Verify the the bootloader tolum is above the FSP reserved area */ + /* Verify the bootloader tolum is above the FSP reserved area */ if (range_entry_end(&tolum) <= range_entry_base(&fsp_mem)) { printk(BIOS_CRIT, "TOLUM end: 0x%08llx != 0x%08llx: FSP rsvd base\n", diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index 9170c02..af06dd1 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -31,7 +31,7 @@ * required, will skip microcode update if true. */ int soc_skip_ucode_update(u32 currrent_patch_id, u32 new_patch_id); -/* return the the version of the currently running microcode */ +/* return the version of the currently running microcode */ uint32_t get_current_microcode_rev(void); /* extract microcode revision from the given patch */ diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index f4cec68..6e3f452 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -235,7 +235,7 @@ gtt_poll(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_STATE, HSW_PWR_WELL_STATE); /* In the native graphics case, we've got about 20 ms. - * after we power up the the AUX channel until we can talk to it. + * after we power up the AUX channel until we can talk to it. * So get that going right now. We can't turn on the panel, yet, just VDD. */ if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { diff --git a/src/soc/amd/common/block/include/amdblocks/dimm_spd.h b/src/soc/amd/common/block/include/amdblocks/dimm_spd.h index 60107c9..1ce6d86 100644 --- a/src/soc/amd/common/block/include/amdblocks/dimm_spd.h +++ b/src/soc/amd/common/block/include/amdblocks/dimm_spd.h @@ -22,7 +22,7 @@ /* * Fill the buf and returns 0 on success. - * Return -1 on failure and the the caller tries sb_read_spd() + * Return -1 on failure and the caller tries sb_read_spd() * to get the SPD from I2C. */ int mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len); diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 6255cfc..529d651 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -158,7 +158,7 @@ The XHCI controller must be enabled and the XHCI firmware must be added in order to have USB 3.0 support configured by coreboot. The OS will be responsible for enabling the XHCI - controller if the the XHCI firmware is available but the + controller if the XHCI firmware is available but the XHCI controller is not enabled by coreboot. config STONEYRIDGE_XHCI_FWM diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 8b775c7..b80f734 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -46,7 +46,7 @@ The XHCI controller must be enabled and the XHCI firmware must be added in order to have USB 3.0 support configured by coreboot. The OS will be responsible for enabling the XHCI - controller if the the XHCI firmware is available but the + controller if the XHCI firmware is available but the XHCI controller is not enabled by coreboot. config HUDSON_XHCI_FWM diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index d0e42d9..3c70c2a 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -49,7 +49,7 @@ The XHCI controller must be enabled and the XHCI firmware must be added in order to have USB 3.0 support configured by coreboot. The OS will be responsible for enabling the XHCI - controller if the the XHCI firmware is available but the + controller if the XHCI firmware is available but the XHCI controller is not enabled by coreboot. config HUDSON_XHCI_FWM diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/mfs3.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/mfs3.h index 63c03b5..1ea8aef 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/mfs3.h +++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/mfs3.h @@ -103,7 +103,7 @@ /// Header for heap space to store the special case register. typedef struct _S3_SPECIAL_CASE_HEAP_HEADER { - UINT8 Node; ///< Node ID for the the header + UINT8 Node; ///< Node ID for the header UINT8 Offset; ///< Offset for the target node } S3_SPECIAL_CASE_HEAP_HEADER; /*---------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mfs3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mfs3.h index fe362dd..6a00dce 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/mfs3.h +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mfs3.h @@ -105,7 +105,7 @@ /// Header for heap space to store the special case register. typedef struct _S3_SPECIAL_CASE_HEAP_HEADER { - UINT8 Node; ///< Node ID for the the header + UINT8 Node; ///< Node ID for the header UINT8 Offset; ///< Offset for the target node } S3_SPECIAL_CASE_HEAP_HEADER; /*---------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfs3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfs3.h index 673d921..657c8df 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfs3.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfs3.h @@ -103,7 +103,7 @@ /// Header for heap space to store the special case register. typedef struct _S3_SPECIAL_CASE_HEAP_HEADER { - UINT8 Node; ///< Node ID for the the header + UINT8 Node; ///< Node ID for the header UINT8 Offset; ///< Offset for the target node } S3_SPECIAL_CASE_HEAP_HEADER; /*---------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfs3.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfs3.h index 4b30237..3ccd06a 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfs3.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfs3.h @@ -106,7 +106,7 @@ /// Header for heap space to store the special case register. typedef struct _S3_SPECIAL_CASE_HEAP_HEADER { - UINT8 Node; ///< Node ID for the the header + UINT8 Node; ///< Node ID for the header UINT8 Offset; ///< Offset for the target node } S3_SPECIAL_CASE_HEAP_HEADER; diff --git a/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test.c b/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test.c index 4f54b69..b9c81ce 100644 --- a/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test.c +++ b/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test.c @@ -150,7 +150,7 @@ * variables at the beginning of this file. * * @param arg Number of the region we should check - * @param arg1 Pointer the the test_info structure + * @param arg1 Pointer the test_info structure */ static void dram_test_thread(int arg, void *arg1) { diff --git a/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-gsern.h b/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-gsern.h index d1b23fc..1efb6f3 100644 --- a/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-gsern.h +++ b/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-gsern.h @@ -11862,7 +11862,7 @@ FIXME no such field RECALIBRATION_OOB_COUNT_ADDER then remove above exempt attribute. */ uint64_t reserved_40_60 : 21; uint64_t max_oob_adder_count : 8; /**< [ 39: 32](R/W) Maximum number of OOB forced pushouts of the idle recalibrations allowed. If the - number of pushouts matches this number, the the idle offset is forced to recalibrate + number of pushouts matches this number, the idle offset is forced to recalibrate regardless of the state of the link. */ uint64_t oob_delay_adder_count : 32; /**< [ 31: 0](R/W) Number of svc_clk ticks allowed to delay the idle recalibration. Default is equal to 1 second based on a 10 ns service clock cycle time. */ @@ -11870,7 +11870,7 @@ uint64_t oob_delay_adder_count : 32; /**< [ 31: 0](R/W) Number of svc_clk ticks allowed to delay the idle recalibration. Default is equal to 1 second based on a 10 ns service clock cycle time. */ uint64_t max_oob_adder_count : 8; /**< [ 39: 32](R/W) Maximum number of OOB forced pushouts of the idle recalibrations allowed. If the - number of pushouts matches this number, the the idle offset is forced to recalibrate + number of pushouts matches this number, the idle offset is forced to recalibrate regardless of the state of the link. */ uint64_t reserved_40_60 : 21; uint64_t idle_oob_adder_counter_clear : 1;/**< [ 61: 61](R/W) This bit one set to high, forces the counter counting the number of OOB caused diff --git a/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-rvu.h b/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-rvu.h index 4a0c33d..c50d3b2 100644 --- a/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-rvu.h +++ b/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-rvu.h @@ -1616,13 +1616,13 @@ uint64_t reserved_9_10 : 2; uint64_t num_lfs : 9; /**< [ 8: 0](RO/H) Number of local functions from the block that are provisioned to the VF/PF. When non-zero, the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in - the the block. + the block. Returns 0 for block types that do not have local functions, 0 or 1 for single-slot blocks; see RVU_BLOCK_TYPE_E. */ #else /* Word 0 - Little Endian */ uint64_t num_lfs : 9; /**< [ 8: 0](RO/H) Number of local functions from the block that are provisioned to the VF/PF. When non-zero, the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in - the the block. + the block. Returns 0 for block types that do not have local functions, 0 or 1 for single-slot blocks; see RVU_BLOCK_TYPE_E. */ uint64_t reserved_9_10 : 2; @@ -2972,10 +2972,10 @@ #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */ uint64_t reserved_9_63 : 55; uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero, - the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the the block. */ + the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */ #else /* Word 0 - Little Endian */ uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero, - the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the the block. */ + the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */ uint64_t reserved_9_63 : 55; #endif /* Word 0 - End */ } s; @@ -3140,10 +3140,10 @@ #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */ uint64_t reserved_9_63 : 55; uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero, - the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the the block. */ + the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */ #else /* Word 0 - Little Endian */ uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero, - the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the the block. */ + the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */ uint64_t reserved_9_63 : 55; #endif /* Word 0 - End */ } s; @@ -3180,10 +3180,10 @@ #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */ uint64_t reserved_9_63 : 55; uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero, - the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the the block. */ + the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */ #else /* Word 0 - Little Endian */ uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero, - the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the the block. */ + the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */ uint64_t reserved_9_63 : 55; #endif /* Word 0 - End */ } s; @@ -3220,10 +3220,10 @@ #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */ uint64_t reserved_9_63 : 55; uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero, - the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the the block. */ + the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */ #else /* Word 0 - Little Endian */ uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero, - the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the the block. */ + the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */ uint64_t reserved_9_63 : 55; #endif /* Word 0 - End */ } s; @@ -3357,10 +3357,10 @@ #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */ uint64_t reserved_9_63 : 55; uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero, - the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the the block. */ + the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */ #else /* Word 0 - Little Endian */ uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero, - the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the the block. */ + the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */ uint64_t reserved_9_63 : 55; #endif /* Word 0 - End */ } s; @@ -3660,10 +3660,10 @@ #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */ uint64_t reserved_9_63 : 55; uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero, - the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the the block. */ + the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */ #else /* Word 0 - Little Endian */ uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero, - the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the the block. */ + the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */ uint64_t reserved_9_63 : 55; #endif /* Word 0 - End */ } s; @@ -3700,10 +3700,10 @@ #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */ uint64_t reserved_9_63 : 55; uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero, - the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the the block. */ + the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */ #else /* Word 0 - Little Endian */ uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero, - the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the the block. */ + the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */ uint64_t reserved_9_63 : 55; #endif /* Word 0 - End */ } s; @@ -3740,10 +3740,10 @@ #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */ uint64_t reserved_9_63 : 55; uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero, - the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the the block. */ + the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */ #else /* Word 0 - Little Endian */ uint64_t num_lfs : 9; /**< [ 8: 0](R/W) Number of LFs from the block that are provisioned to the PF/VF. When non-zero, - the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the the block. */ + the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in the block. */ uint64_t reserved_9_63 : 55; #endif /* Word 0 - End */ } s; @@ -3792,13 +3792,13 @@ uint64_t reserved_9_10 : 2; uint64_t num_lfs : 9; /**< [ 8: 0](RO/H) Number of local functions from the block that are provisioned to the VF/PF. When non-zero, the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in - the the block. + the block. Returns 0 for block types that do not have local functions, 0 or 1 for single-slot blocks; see RVU_BLOCK_TYPE_E. */ #else /* Word 0 - Little Endian */ uint64_t num_lfs : 9; /**< [ 8: 0](RO/H) Number of local functions from the block that are provisioned to the VF/PF. When non-zero, the provisioned LFs are mapped to slots 0 to [NUM_LFS]-1 in - the the block. + the block. Returns 0 for block types that do not have local functions, 0 or 1 for single-slot blocks; see RVU_BLOCK_TYPE_E. */ uint64_t reserved_9_10 : 2; diff --git a/src/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Uefi/UefiMultiPhase.h b/src/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Uefi/UefiMultiPhase.h index 58cb051..6d96c12 100644 --- a/src/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Uefi/UefiMultiPhase.h +++ b/src/vendorcode/intel/edk2/UDK2015/MdePkg/Include/Uefi/UefiMultiPhase.h @@ -180,7 +180,7 @@ /// EFI_CERT_TYPE_RSA2048_SHA256_GUID. If the attribute specifies /// authenticated access, then the Data buffer should begin with an /// authentication descriptor prior to the data payload and DataSize -/// should reflect the the data.and descriptor size. The caller +/// should reflect the data.and descriptor size. The caller /// shall digest the Monotonic Count value and the associated data /// for the variable update using the SHA-256 1-way hash algorithm. /// The ensuing the 32-byte digest will be signed using the private diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/DxeServicesLib.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/DxeServicesLib.h index 48cb703..0ec4fe1 100644 --- a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/DxeServicesLib.h +++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/DxeServicesLib.h @@ -177,7 +177,7 @@ /** - Searches the FFS file the the currently executing module was loaded from and returns the first matching FFS section. + Searches the FFS file the currently executing module was loaded from and returns the first matching FFS section. This function searches the FFS file that the currently executing module was loaded from for a FFS sections of type SectionType. If the FFS file contains at least SectionInstance instances of the FFS section specified by SectionType, diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/ExtractGuidedSectionLib.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/ExtractGuidedSectionLib.h index 73dfed2..ac35a33 100644 --- a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/ExtractGuidedSectionLib.h +++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/ExtractGuidedSectionLib.h @@ -119,7 +119,7 @@ If GetInfoHandler is NULL, then ASSERT(). If DecodeHandler is NULL, then ASSERT(). - @param[in] SectionGuid A pointer to the GUID associated with the the handlers + @param[in] SectionGuid A pointer to the GUID associated with the handlers of the GUIDed section type being registered. @param[in] GetInfoHandler Pointer to a function that examines a GUIDed section and returns the size of the decoded buffer and the size of an optional scratch buffer @@ -168,7 +168,7 @@ Examines a GUIDed section specified by InputSection. If GUID for InputSection does not match any of the GUIDs registered through ExtractGuidedSectionRegisterHandlers(), then RETURN_UNSUPPORTED is returned. - If the GUID of InputSection does match the GUID that this handler supports, then the the associated handler + If the GUID of InputSection does match the GUID that this handler supports, then the associated handler of type EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER that was registered with ExtractGuidedSectionRegisterHandlers() is used to retrieve the OututBufferSize, ScratchSize, and Attributes values. The return status from the handler of type EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER is returned. @@ -211,7 +211,7 @@ Decodes the GUIDed section specified by InputSection. If GUID for InputSection does not match any of the GUIDs registered through ExtractGuidedSectionRegisterHandlers(), then RETURN_UNSUPPORTED is returned. - If the GUID of InputSection does match the GUID that this handler supports, then the the associated handler + If the GUID of InputSection does match the GUID that this handler supports, then the associated handler of type EXTRACT_GUIDED_SECTION_DECODE_HANDLER that was registered with ExtractGuidedSectionRegisterHandlers() is used to decode InputSection into the buffer specified by OutputBuffer and the authentication status of this decode operation is returned in AuthenticationStatus. If the decoded buffer is identical to the data in InputSection, diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/UefiLib.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/UefiLib.h index d91bcf8..0e9ac67 100644 --- a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/UefiLib.h +++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/UefiLib.h @@ -409,7 +409,7 @@ This function tests whether the driver specified by DriverBindingHandle is currently managing the controller specified by ControllerHandle. This test - is performed by evaluating if the the protocol specified by ProtocolGuid is + is performed by evaluating if the protocol specified by ProtocolGuid is present on ControllerHandle and is was opened by DriverBindingHandle with an attribute of EFI_OPEN_PROTOCOL_BY_DRIVER. If ProtocolGuid is NULL, then ASSERT(). diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Smbios.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Smbios.h index 1860ba5..d03380c 100644 --- a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Smbios.h +++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Smbios.h @@ -180,7 +180,7 @@ @param[in] Type On entry, it points to the type of the next SMBIOS record to return. If NULL, it indicates that the next record of any type will be returned. Type is not modified by the this function. - @param[out] Record On exit, points to a pointer to the the SMBIOS Record consisting of the formatted area + @param[out] Record On exit, points to a pointer to the SMBIOS Record consisting of the formatted area followed by the unformatted area. The unformatted area optionally contains text strings. @param[out] ProducerHandle On exit, points to the ProducerHandle registered by Add(). If no ProducerHandle was passed into Add() NULL is returned. If a NULL pointer is diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Uefi/UefiMultiPhase.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Uefi/UefiMultiPhase.h index 3419762..73daf8b 100644 --- a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Uefi/UefiMultiPhase.h +++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Uefi/UefiMultiPhase.h @@ -182,7 +182,7 @@ /// EFI_CERT_TYPE_RSA2048_SHA256_GUID. If the attribute specifies /// authenticated access, then the Data buffer should begin with an /// authentication descriptor prior to the data payload and DataSize -/// should reflect the the data.and descriptor size. The caller +/// should reflect the data.and descriptor size. The caller /// shall digest the Monotonic Count value and the associated data /// for the variable update using the SHA-256 1-way hash algorithm. /// The ensuing the 32-byte digest will be signed using the private diff --git a/src/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Uefi/UefiMultiPhase.h b/src/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Uefi/UefiMultiPhase.h index 8b1de79..6c0f051 100644 --- a/src/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Uefi/UefiMultiPhase.h +++ b/src/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Uefi/UefiMultiPhase.h @@ -142,7 +142,7 @@ /// EFI_CERT_TYPE_RSA2048_SHA256_GUID. If the attribute specifies /// authenticated access, then the Data buffer should begin with an /// authentication descriptor prior to the data payload and DataSize -/// should reflect the the data.and descriptor size. The caller +/// should reflect the data.and descriptor size. The caller /// shall digest the Monotonic Count value and the associated data /// for the variable update using the SHA-256 1-way hash algorithm. /// The ensuing the 32-byte digest will be signed using the private -- To view, visit https://review.coreboot.org/c/coreboot/+/30160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I179264ee6681a7ba4488b9f1c6bce1a19b4e1772 Gerrit-Change-Number: 30160 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: soc/amd/stoneyridge: Improve grammar through punctuation
by Jonathan Neuschäfer (Code Review) 11 Dec '18

11 Dec '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30159 Change subject: soc/amd/stoneyridge: Improve grammar through punctuation ...................................................................... soc/amd/stoneyridge: Improve grammar through punctuation Change-Id: Iebae12f0b0397b5d4ad1fb09b5d9b847bc63c5d1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/soc/amd/stoneyridge/include/soc/gpio.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/30159/1 diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index b758309..5609ca6 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -491,7 +491,7 @@ /* * Several macros are available to declare programming of GPIO pins, and if - * needed more than 1 macro can be used for any pin. However, some macros + * needed, more than 1 macro can be used for any pin. However, some macros * will have no effect if combined. For example debounce only affects input * or one of the interrupts. Some macros should not be combined, such as SMI * and regular interrupt. The defined macros and their parameters are: -- To view, visit https://review.coreboot.org/c/coreboot/+/30159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebae12f0b0397b5d4ad1fb09b5d9b847bc63c5d1 Gerrit-Change-Number: 30159 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: Makefile.inc: Avoid race condition when using 'make -j<N>'
by Nico Huber (Code Review) 11 Dec '18

11 Dec '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29984 ) Change subject: Makefile.inc: Avoid race condition when using 'make -j<N>' ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie93eda567f88ca08c97df7e70cdff5b07442747d Gerrit-Change-Number: 29984 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Dec 2018 14:50:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/icelake: Select SOC_INTEL_USES_MP_SERVICES_PPI Kconfig
by Subrata Banik (Code Review) 11 Dec '18

11 Dec '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30158 Change subject: soc/intel/icelake: Select SOC_INTEL_USES_MP_SERVICES_PPI Kconfig ...................................................................... soc/intel/icelake: Select SOC_INTEL_USES_MP_SERVICES_PPI Kconfig This patch selects required Kconfig to publish mp services ppi for intel fsp consumption. Change-Id: Ife0c133ddbf2e0fa14f94ffec15d11830cfaf7b3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/icelake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/30158/1 diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 727fccee..8aa71c7 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -54,6 +54,7 @@ select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET + select SOC_INTEL_USES_MP_SERVICES_PPI select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_CONSTANT_RATE -- To view, visit https://review.coreboot.org/c/coreboot/+/30158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife0c133ddbf2e0fa14f94ffec15d11830cfaf7b3 Gerrit-Change-Number: 30158 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: Documentation/soc/intel/icelake: Fix references between documents
by Jonathan Neuschäfer (Code Review) 11 Dec '18

11 Dec '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30157 Change subject: Documentation/soc/intel/icelake: Fix references between documents ...................................................................... Documentation/soc/intel/icelake: Fix references between documents Change-Id: Ifbdab15b1183998712f92d1f2f5340d2ad1451dc Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M Documentation/mainboard/google/dragonegg.md M Documentation/mainboard/intel/icelake_rvp.md M Documentation/soc/intel/icelake/iceLake_coreboot_development.md 3 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/30157/1 diff --git a/Documentation/mainboard/google/dragonegg.md b/Documentation/mainboard/google/dragonegg.md index df4fe16..ef7e61b 100644 --- a/Documentation/mainboard/google/dragonegg.md +++ b/Documentation/mainboard/google/dragonegg.md @@ -4,14 +4,14 @@ Dragonegg is based on Intel Ice Lake platform, please refer to below link to get more details ```eval_rst -:doc:`../../soc/intel/iceLake_coreboot_development.md` +:doc:`../../soc/intel/icelake/iceLake_coreboot_development` ``` ## Building coreboot * Follow build instructions mentioned in Ice Lake document ```eval_rst -:doc:`../../soc/intel/iceLake_coreboot_development.md` +:doc:`../../soc/intel/icelake/iceLake_coreboot_development` ``` * The default options for this board should result in a fully working image: diff --git a/Documentation/mainboard/intel/icelake_rvp.md b/Documentation/mainboard/intel/icelake_rvp.md index 09f2185..514ba6b 100644 --- a/Documentation/mainboard/intel/icelake_rvp.md +++ b/Documentation/mainboard/intel/icelake_rvp.md @@ -4,14 +4,14 @@ Ice Lake RVP is based on Intel Ice Lake platform, please refer to below link to get more details ```eval_rst -:doc:`../../soc/intel/iceLake_coreboot_development.md` +:doc:`../../soc/intel/icelake/iceLake_coreboot_development` ``` ## Building coreboot * Follow build instructions mentioned in Ice Lake document ```eval_rst -:doc:`../../soc/intel/iceLake_coreboot_development.md` +:doc:`../../soc/intel/icelake/iceLake_coreboot_development` ``` * The default options for this board should result in a fully working image: diff --git a/Documentation/soc/intel/icelake/iceLake_coreboot_development.md b/Documentation/soc/intel/icelake/iceLake_coreboot_development.md index 6f194ca..5f8e279 100644 --- a/Documentation/soc/intel/icelake/iceLake_coreboot_development.md +++ b/Documentation/soc/intel/icelake/iceLake_coreboot_development.md @@ -17,12 +17,12 @@ 2. Additionally provides Firmware code support for Intel Reference Platform (RVP), known as Ice lake RVP with same SoC. ```eval_rst - :doc:`../../../mainboard/intel/icelake_rvp.md` + :doc:`../../../mainboard/intel/icelake_rvp` ``` 3. OEMs to design based on reference platform and make use of mainboard sample code. Dragonegg is Ice Lake based mainboard developed by Google ```eval_rst - :doc:`../../../mainboard/google/dragonegg.md` + :doc:`../../../mainboard/google/dragonegg` ``` ### Summary: -- To view, visit https://review.coreboot.org/c/coreboot/+/30157 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbdab15b1183998712f92d1f2f5340d2ad1451dc Gerrit-Change-Number: 30157 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation/soc/intel/icelake: Fix indentation in numbered list
by Jonathan Neuschäfer (Code Review) 11 Dec '18

11 Dec '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30156 Change subject: Documentation/soc/intel/icelake: Fix indentation in numbered list ...................................................................... Documentation/soc/intel/icelake: Fix indentation in numbered list Without this patch, the numbers restart at 1 at several points in the HTML output. Change-Id: Ie3634775ed9f993b1181785c58d72834183336e1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M Documentation/soc/intel/icelake/iceLake_coreboot_development.md 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/30156/1 diff --git a/Documentation/soc/intel/icelake/iceLake_coreboot_development.md b/Documentation/soc/intel/icelake/iceLake_coreboot_development.md index 59b013d..6f194ca 100644 --- a/Documentation/soc/intel/icelake/iceLake_coreboot_development.md +++ b/Documentation/soc/intel/icelake/iceLake_coreboot_development.md @@ -33,27 +33,27 @@ ## Create coreboot Image 1. Clone latest coreboot code as below -```bash -$ git clone https://review.coreboot.org/coreboot.git -``` + ```bash + $ git clone https://review.coreboot.org/coreboot.git + ``` 2. Place blobs (ucode, me.bin and FSP packages) in appropriate locations -Note: -Consider the fact that ucode and ME kit for Ice Lake SoC will be available from Intel VIP site. -After product launch, FSP binary will be available externally as any other program. + Note: + Consider the fact that ucode and ME kit for Ice Lake SoC will be available from Intel VIP site. + After product launch, FSP binary will be available externally as any other program. 3. Create coreboot .config 4. Build toolchain -```bash -CPUS=$(nproc--ignore=1) make crossgcc-i386 iasl -``` + ```bash + CPUS=$(nproc--ignore=1) make crossgcc-i386 iasl + ``` 5. Build image -```bash -$ make # the image is generated as build/coreboot.rom -``` + ```bash + $ make # the image is generated as build/coreboot.rom + ``` ## Flashing coreboot -- To view, visit https://review.coreboot.org/c/coreboot/+/30156 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3634775ed9f993b1181785c58d72834183336e1 Gerrit-Change-Number: 30156 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Makefile.inc: Avoid race condition when using 'make -j<N>'
by Jonathan Neuschäfer (Code Review) 11 Dec '18

11 Dec '18

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29984 to look at the new patch set (#2). Change subject: Makefile.inc: Avoid race condition when using 'make -j<N>' ...................................................................... Makefile.inc: Avoid race condition when using 'make -j<N>' When building coreboot from scratch with 'make -j4', I sometimes see this error: CREATE build/mainboard/emulation/qemu-riscv/cbfs-file.wblRgZ.out (from /.../coreboot/.config) HOSTCC cbfstool/cbfstool (link) make[1]: execvp: build/util/kconfig/conf: Permission denied make[1]: *** [/.../coreboot/util/kconfig/Makefile:92: savedefconfig] Error 127 It happens, I think, because the rule generated by cbfs-files-processor-defconfig runs 'make savedefconfig', which builds build/util/kconfig/conf, and something also builds it, at the same time. Fix this case, by making this rule depend on $(objutil)/kconfig/conf. The same fix is also precautiously applied to the rule for $(KCONFIG_AUTOHEADER) in Makefile. Change-Id: Ie93eda567f88ca08c97df7e70cdff5b07442747d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M Makefile M Makefile.inc 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/29984/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie93eda567f88ca08c97df7e70cdff5b07442747d Gerrit-Change-Number: 29984 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2018