coreboot-gerrit November 2018

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Change in ...coreboot[master]: nb/intel/gm45: Make fetching the blc_pwm freq global
by Arthur Heymans (Code Review) 29 Nov '18

29 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29925 Change subject: nb/intel/gm45: Make fetching the blc_pwm freq global ...................................................................... nb/intel/gm45: Make fetching the blc_pwm freq global This can be used to select the proper VBT. Change-Id: Id3f6ba3ae31a5ab47f44d207678c1c4a6a43b7ec Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/gma.c 2 files changed, 8 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/29925/1 diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 95863d9..37e1ddc 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -443,6 +443,7 @@ int pwm_freq; /* In Hz */ }; int get_blc_values(const struct blc_pwm_t **entries); +int get_blc_pwm_freq_value(void); #if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 34cf367..511225f 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -41,6 +41,8 @@ static struct resource *gtt_res = NULL; +char edid_ascii_string[EDID_ASCII_STRING_LENGTH + 1]; + u32 gtt_read(u32 reg) { return read32(res2mmio(gtt_res, reg, 0)); @@ -668,7 +670,7 @@ return (blc_mod << 16) | blc_mod; } -static int get_blc_pwm_freq_value(const char *edid_ascii_string) +int get_blc_pwm_freq_value(void) { static int blc_pwm_freq = -1; const struct blc_pwm_t *blc_pwm; @@ -701,8 +703,7 @@ return blc_pwm_freq; } -static void gma_pm_init_post_vbios(struct device *const dev, - const char *edid_ascii_string) +static void gma_pm_init_post_vbios(struct device *const dev) { const struct northbridge_intel_gm45_config *const conf = dev->chip_info; @@ -739,7 +740,7 @@ reg8 = 100; if (conf->duty_cycle != 0) reg8 = conf->duty_cycle; - pwm_freq = get_blc_pwm_freq_value(edid_ascii_string); + pwm_freq = get_blc_pwm_freq_value(); if (pwm_freq < 0 && conf->default_pwm_freq != 0) pwm_freq = conf->default_pwm_freq; @@ -780,7 +781,8 @@ decode_edid(edid_data_lvds, sizeof(edid_data_lvds), &edid_lvds); /* Post VBIOS init */ - gma_pm_init_post_vbios(dev, edid_lvds.ascii_string); + memcpy(edid_ascii_string, edid_lvds.ascii_string, sizeof(edid_ascii_string)); + gma_pm_init_post_vbios(dev); int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/29925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3f6ba3ae31a5ab47f44d207678c1c4a6a43b7ec Gerrit-Change-Number: 29925 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/gm45: Make fetching the blc_pwm freq its own function
by Arthur Heymans (Code Review) 29 Nov '18

29 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29924 Change subject: nb/intel/gm45: Make fetching the blc_pwm freq its own function ...................................................................... nb/intel/gm45: Make fetching the blc_pwm freq its own function Change-Id: I9ad364f84f3658be98ce7ad3a6f0f0fe3247fc41 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/gma.c 1 file changed, 37 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/29924/1 diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index b86e2b3..34cf367 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -668,6 +668,39 @@ return (blc_mod << 16) | blc_mod; } +static int get_blc_pwm_freq_value(const char *edid_ascii_string) +{ + static int blc_pwm_freq = -1; + const struct blc_pwm_t *blc_pwm; + int i; + int blc_array_len; + + if (blc_pwm_freq > 0) + return blc_pwm_freq; + + blc_array_len = get_blc_values(&blc_pwm); + /* Find EDID string and pwm freq in lookup table */ + for (i = 0; i < blc_array_len; i++) { + if (!strcmp(blc_pwm[i].ascii_string, edid_ascii_string)) { + blc_pwm_freq = blc_pwm[i].pwm_freq; + printk(BIOS_DEBUG, "Found EDID string: %s in lookup table, pwm: %dHz\n", + blc_pwm[i].ascii_string, blc_pwm_freq); + break; + } + } + + if (i == blc_array_len) + printk(BIOS_NOTICE, "Your panels EDID `%s` wasn't found in the" + "lookup table.\n You may have issues with your panels" + "backlight.\n If you want to help improving coreboot" + "please report: this EDID string\n and the result" + "of `intel_read read BLC_PWM_CTL`" + "(from intel-gpu-tools)\n while running vendor BIOS\n", + edid_ascii_string); + + return blc_pwm_freq; +} + static void gma_pm_init_post_vbios(struct device *const dev, const char *edid_ascii_string) { @@ -675,9 +708,7 @@ u32 reg32; u8 reg8; - const struct blc_pwm_t *blc_pwm; - int blc_array_len, i; - u16 pwm_freq = 0; + u16 pwm_freq; /* Setup Panel Power On Delays */ reg32 = gtt_read(PP_ON_DELAYS); @@ -708,31 +739,11 @@ reg8 = 100; if (conf->duty_cycle != 0) reg8 = conf->duty_cycle; - blc_array_len = get_blc_values(&blc_pwm); - if (conf->default_pwm_freq != 0) + pwm_freq = get_blc_pwm_freq_value(edid_ascii_string); + if (pwm_freq < 0 && conf->default_pwm_freq != 0) pwm_freq = conf->default_pwm_freq; - /* Find EDID string and pwm freq in lookup table */ - for (i = 0; i < blc_array_len; i++) { - if (!strncmp(blc_pwm[i].ascii_string, edid_ascii_string, - strlen(blc_pwm[i].ascii_string))) { - pwm_freq = blc_pwm[i].pwm_freq; - printk(BIOS_DEBUG, "Found EDID string: %s in lookup table, pwm: %dHz\n", - blc_pwm[i].ascii_string, pwm_freq); - break; - } - } - - if (i == blc_array_len) - printk(BIOS_NOTICE, "Your panels EDID `%s` wasn't found in the" - "lookup table.\n You may have issues with your panels" - "backlight.\n If you want to help improving coreboot" - "please report: this EDID string\n and the result" - "of `intel_read read BLC_PWM_CTL`" - "(from intel-gpu-tools)\n while running vendor BIOS\n", - edid_ascii_string); - - if (pwm_freq == 0) + if (pwm_freq < 0) gtt_write(BLC_PWM_CTL, 0x06100610); else gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev, pwm_freq, -- To view, visit https://review.coreboot.org/c/coreboot/+/29924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ad364f84f3658be98ce7ad3a6f0f0fe3247fc41 Gerrit-Change-Number: 29924 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: TEST COMMIT
by Name of user not set (Code Review) 29 Nov '18

29 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29923 Change subject: TEST COMMIT ...................................................................... TEST COMMIT Change-Id: Ic95fb9cbeb98c6f6f502619b7f4921bc5febb7cd Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M Makefile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/29923/1 diff --git a/Makefile b/Makefile index 1d4a488..53c8251 100644 --- a/Makefile +++ b/Makefile @@ -1,3 +1,4 @@ + ## ## This file is part of the coreboot project. ## -- To view, visit https://review.coreboot.org/c/coreboot/+/29923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic95fb9cbeb98c6f6f502619b7f4921bc5febb7cd Gerrit-Change-Number: 29923 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: riscv: add support to select the privilege level of the payload running
by build bot (Jenkins) (Code Review) 29 Nov '18

29 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29494 ) Change subject: riscv: add support to select the privilege level of the payload running ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/#/c/29494/7/src/arch/riscv/boot.c File src/arch/riscv/boot.c: https://review.coreboot.org/#/c/29494/7/src/arch/riscv/boot.c@50 PS7, Line 50: void (*doit)(void *) = prog_entry(prog); function definition argument 'void *' should also have an identifier name -- To view, visit https://review.coreboot.org/c/coreboot/+/29494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96961246cd257b63cf167238aa0cf6e65272b951 Gerrit-Change-Number: 29494 Gerrit-PatchSet: 7 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 29 Nov 2018 10:34:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/dragonegg: Don't use device_t
by Patrick Georgi (Code Review) 29 Nov '18

29 Nov '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29915 ) Change subject: mb/google/dragonegg: Don't use device_t ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief858f6612d1c7b4b0c286cf5938f8c29055f1b5 Gerrit-Change-Number: 29915 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 09:30:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: include/device/smbus.h: Don't use device_t
by Patrick Georgi (Code Review) 29 Nov '18

29 Nov '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29914 ) Change subject: include/device/smbus.h: Don't use device_t ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c88642133d3cbf33015e3e1e855fb2c786878d6 Gerrit-Change-Number: 29914 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 09:30:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86/Makefile.inc: Fix typo
by Patrick Georgi (Code Review) 29 Nov '18

29 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29878 ) Change subject: arch/x86/Makefile.inc: Fix typo ...................................................................... arch/x86/Makefile.inc: Fix typo Link 32bit ramstage if CONFIG_ARCH_RAMSTAGE_X86_32 is set. Required for 64bit ramstage support. Change-Id: Ib0c06f494dcc035d182ab9034e910ceceb236198 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/c/29878 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index fcc57c5..c5cf625 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -398,7 +398,7 @@ $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs) @printf " CC $(subst $(obj)/,,$(@))\n" -ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) $(LD_ramstage) -m elf_i386 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) --no-whole-archive $(COMPILER_RT_ramstage) --end-group else $(LD_ramstage) -m elf_x86_64 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) --no-whole-archive $(COMPILER_RT_ramstage) --end-group -- To view, visit https://review.coreboot.org/c/coreboot/+/29878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0c06f494dcc035d182ab9034e910ceceb236198 Gerrit-Change-Number: 29878 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: MAINTAINERS: Add myself as a maintainer
by Angel Pons (Code Review) 29 Nov '18

29 Nov '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29913 ) Change subject: MAINTAINERS: Add myself as a maintainer ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70df3b9e4e36c2e5d73f8888fe0ec220aa8a91b7 Gerrit-Change-Number: 29913 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 09:25:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mediatek/mt8183: Add external interrupts (EINT) support
by Tristan Hsieh (Code Review) 29 Nov '18

29 Nov '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29921 Change subject: mediatek/mt8183: Add external interrupts (EINT) support ...................................................................... mediatek/mt8183: Add external interrupts (EINT) support To communicate with TPM, We need EINT dirver for TPM intterupt. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot Change-Id: I730ee52226d17bf4ab51aa0ec09ea331766548ab Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/addressmap.h 2 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/29921/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index b981e45..244b2c4 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -2,7 +2,7 @@ bootblock-y += auxadc.c bootblock-y += bootblock.c -bootblock-y += ../common/gpio.c gpio.c +bootblock-y += ../common/eint.c ../common/gpio.c gpio.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c @@ -14,7 +14,7 @@ decompressor-y += ../common/timer.c verstage-y += auxadc.c -verstage-y += ../common/gpio.c gpio.c +verstage-y += ../common/eint.c ../common/gpio.c gpio.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c verstage-y += ../common/uart.c @@ -26,7 +26,7 @@ romstage-y += dramc_pi_basic_api.c romstage-y += dramc_pi_calibration_api.c romstage-y += memory.c -romstage-y += ../common/gpio.c gpio.c +romstage-y += ../common/eint.c ../common/gpio.c gpio.c romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c @@ -36,7 +36,7 @@ ramstage-y += auxadc.c ramstage-y += ../common/cbmem.c emi.c -ramstage-y += ../common/gpio.c gpio.c +ramstage-y += ../common/eint.c ../common/gpio.c gpio.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index 7578c28..2b2c8e8 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -28,6 +28,7 @@ SPM_BASE = IO_PHYS + 0x00006000, RGU_BASE = IO_PHYS + 0x00007000, GPT_BASE = IO_PHYS + 0x00008000, + EINT_BASE = IO_PHYS + 0x0000B000, APMIXED_BASE = IO_PHYS + 0x0000C000, PWRAP_BASE = IO_PHYS + 0x0000D000, EMI_BASE = IO_PHYS + 0x00219000, -- To view, visit https://review.coreboot.org/c/coreboot/+/29921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I730ee52226d17bf4ab51aa0ec09ea331766548ab Gerrit-Change-Number: 29921 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: broadcom: Remove SoC and board support
by Angel Pons (Code Review) 29 Nov '18

29 Nov '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29905 ) Change subject: broadcom: Remove SoC and board support ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I148dd7eb0192d396cb69bc26c4062f88a764771a Gerrit-Change-Number: 29905 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 09:20:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2018