coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

1 participants
1699 discussions

Change in ...coreboot[master]: soc/intel/broadwell: Implement postcar stage
by Matt DeVillier (Code Review) 29 Nov '18

29 Nov '18

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29927 ) Change subject: soc/intel/broadwell: Implement postcar stage ...................................................................... Patch Set 1: Code-Review+1 google/guado builds/boots normally -- To view, visit https://review.coreboot.org/c/coreboot/+/29927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I428832a2d7e46ce61a7f9bd498b609feb4518eb0 Gerrit-Change-Number: 29927 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 16:23:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: Untangle CBFS microcode updates
by Nico Huber (Code Review) 29 Nov '18

29 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29934 ) Change subject: Untangle CBFS microcode updates ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29934/1/src/cpu/Kconfig File src/cpu/Kconfig: https://review.coreboot.org/#/c/29934/1/src/cpu/Kconfig@107 PS1, Line 107: select USE_CPU_MICROCODE_CBFS_BINS depends on !POOR_MICROCODE_MAINTENANCE -- To view, visit https://review.coreboot.org/c/coreboot/+/29934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib403402e240d3531640a62ce93b7a93b4ef6ca5e Gerrit-Change-Number: 29934 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Comment-Date: Thu, 29 Nov 2018 16:10:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: Untangle CBFS microcode updates
by Nico Huber (Code Review) 29 Nov '18

29 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29934 Change subject: Untangle CBFS microcode updates ...................................................................... Untangle CBFS microcode updates Change-Id: Ib403402e240d3531640a62ce93b7a93b4ef6ca5e Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M Makefile.inc M src/cpu/Kconfig M src/cpu/Makefile.inc M src/cpu/amd/family_10h-family_15h/Kconfig M src/cpu/amd/family_10h-family_15h/Makefile.inc M src/cpu/intel/fsp_model_406dx/Kconfig M src/cpu/intel/microcode/Makefile.inc M src/soc/intel/apollolake/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_broadwell_de/Kconfig M src/soc/intel/icelake/Kconfig 12 files changed, 61 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/29934/1 diff --git a/Makefile.inc b/Makefile.inc index aaae7bc..e24c859 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1048,7 +1048,7 @@ $(FIT_OPTIONS) endif -ifeq ($(CONFIG_CPU_MICROCODE_CBFS_GENERATE),y) +ifeq ($(CONFIG_USE_CPU_MICROCODE_CBFS_BINS),y) @printf " UPDATE-FIT\n" $(CBFSTOOL) $@.tmp update-fit -n cpu_microcode_blob.bin -x $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \ $(FIT_OPTIONS) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index a7cb99e..807a4ce 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -84,14 +84,27 @@ This is selected by a board or chipset to set the default for the microcode source choice to a list of external microcode headers +config POOR_MICROCODE_MAINTENANCE + bool + help + Selected by platforms that don't maintain microcode updates in the + blobs repo. + +config USE_CPU_MICROCODE_CBFS_BINS + bool + help + Selected to add binary microcode files (`cpu_microcode_bins` in the + makefiles) to CBFS. + choice prompt "Include CPU microcode in CBFS" if ARCH_X86 default CPU_MICROCODE_CBFS_EXTERNAL_HEADER if USES_MICROCODE_HEADER_FILES - default CPU_MICROCODE_CBFS_GENERATE if SUPPORT_CPU_UCODE_IN_CBFS && USE_BLOBS - default CPU_MICROCODE_CBFS_NONE if !SUPPORT_CPU_UCODE_IN_CBFS + default CPU_MICROCODE_CBFS_NONE if POOR_MICROCODE_MAINTENANCE + depends on SUPPORT_CPU_UCODE_IN_CBFS -config CPU_MICROCODE_CBFS_GENERATE +config CPU_MICROCODE_CBFS_DEFAULT_BINS bool "Generate from tree" + select USE_CPU_MICROCODE_CBFS_BINS help Select this option if you want microcode updates to be assembled when building coreboot and included in the final image as a separate CBFS @@ -102,8 +115,27 @@ If unsure, select this option. +config CPU_MICROCODE_CBFS_EXTERNAL_BINS + bool "Include external microcode binary" + select USE_CPU_MICROCODE_CBFS_BINS + depends on !CPU_MICROCODE_MULTIPLE_FILES + help + Select this option if you want to include external binary files + in the CPUs native format. They will be included as a separate + file in CBFS. + + A word of caution: only select this option if you are sure the + microcode that you have is newer than the microcode shipping with + coreboot. + + The microcode file may be removed from the ROM image at a later + time with cbfstool, if desired. + + If unsure, and applicable, select "Generate from tree" + config CPU_MICROCODE_CBFS_EXTERNAL_HEADER bool "Include external microcode header files" + depends on !CPU_MICROCODE_MULTIPLE_FILES help Select this option if you want to include external c header files containing the CPU microcode. This will be included as a separate @@ -116,25 +148,17 @@ The microcode file may be removed from the ROM image at a later time with cbfstool, if desired. - If unsure, select "Generate from tree" + If unsure, and applicable, select "Generate from tree" config CPU_MICROCODE_CBFS_NONE bool "Do not include microcode updates" help Select this option if you do not want CPU microcode included in CBFS. - Note that for some CPUs, the microcode is hard-coded into the source - tree and is not loaded from CBFS. In this case, microcode will still - be updated. There is a push to move all microcode to CBFS, but this - change is not implemented for all CPUs. - - This option currently applies to: - - Intel SandyBridge/IvyBridge - - VIA Nano Microcode may be added to the ROM image at a later time with cbfstool, if desired. - If unsure, select "Generate from tree" + If unsure, and applicable, select "Generate from tree" The GOOD: Microcode updates intend to solve issues that have been discovered @@ -164,8 +188,6 @@ config CPU_MICROCODE_MULTIPLE_FILES bool - default n - depends on CPU_MICROCODE_CBFS_GENERATE help Select this option to install separate microcode container files into CBFS instead of using the traditional monolithic microcode file format. @@ -179,7 +201,7 @@ config CPU_UCODE_BINARIES string "Microcode binary path and filename" - depends on CPU_MICROCODE_CBFS_GENERATE + depends on CPU_MICROCODE_CBFS_EXTERNAL_BINS default "" help Some platforms have microcode in the blobs directory, and these can diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 72fc29c..57241f6 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -17,7 +17,7 @@ ################################################################################ ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y) -cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += cpu_microcode_blob.bin +cbfs-files-$(CONFIG_USE_CPU_MICROCODE_CBFS_BINS) += cpu_microcode_blob.bin endif ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) @@ -29,6 +29,11 @@ util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES) endif +ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS),y) +cpu_microcode_bins := $(call strip_quotes,$(CONFIG_CPU_UCODE_BINARIES)) +endif +# otherwise `cpu_microcode_bins` should be filled by platform makefiles + # We just mash all microcode binaries together into one binary to rule them all. # This approach assumes that the microcode binaries are properly padded, and # their headers specify the correct size. This works fairly well on isolatied @@ -37,21 +42,26 @@ # there is only one microcode binary (i.e. one container), then we don't have # this issue, and this rule will continue to work. $(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins)) + NO_MICROCODE_BINS=1; \ for bin in $(cpu_microcode_bins); do \ + NO_MICROCODE_BINS=0; \ if [ ! -f "$$bin" ]; then \ echo "Microcode error: $$bin does not exist"; \ NO_MICROCODE_FILE=1; \ fi; \ done; \ if [ -n "$$NO_MICROCODE_FILE" ]; then \ - if [ -z "$(CONFIG_USE_BLOBS)" ] && [ -n "$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)" ]; then \ + if [ -z "$(CONFIG_USE_BLOBS)" ] && [ -n "$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS)" ]; then \ echo "Try enabling binary-only repository in Kconfig 'General setup' menu."; \ fi; \ false; \ fi + if [ "$$NO_MICROCODE_BINS" -eq 1 ]; then \ + false; \ + fi @printf " MICROCODE $(subst $(obj)/,,$(@))\n" @echo $(cpu_microcode_bins) - cat /dev/null $+ > $@ + cat $+ > $@ cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin cpu_microcode_blob.bin-type := microcode diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index 8e90247..5193d1d 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -10,7 +10,7 @@ select UDELAY_LAPIC select HAVE_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS - select CPU_MICROCODE_MULTIPLE_FILES if !CPU_MICROCODE_CBFS_NONE + select CPU_MICROCODE_MULTIPLE_FILES select ACPI_HUGE_LOWMEM_BACKUP if CPU_AMD_MODEL_10XXX diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc index 2ed76e1..7035323 100644 --- a/src/cpu/amd/family_10h-family_15h/Makefile.inc +++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc @@ -15,11 +15,11 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c # Microcode for Family 10h, 11h, 12h, and 14h -cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin +cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd.bin microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin microcode_amd.bin-type := microcode # Microcode for Family 15h -cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin +cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd_fam15h.bin microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin microcode_amd_fam15h.bin-type := microcode diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 4c79b23..1f73749 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -29,6 +29,7 @@ select SSE2 select UDELAY_LAPIC select SUPPORT_CPU_UCODE_IN_CBFS + select POOR_MICROCODE_MAINTENANCE select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index b56e6a7..f589430 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -4,5 +4,3 @@ ################################################################################ ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c romstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c - -cpu_microcode_bins += $(call strip_quotes,$(CONFIG_CPU_UCODE_BINARIES)) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4a841be..66db8db 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -31,6 +31,7 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select IOAPIC select PCR_COMMON_IOSF_1_0 + select POOR_MICROCODE_MAINTENANCE select SMP select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 9452b6d..a9a511e 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -46,6 +46,7 @@ select PARALLEL_MP select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 + select POOR_MICROCODE_MAINTENANCE select POSTCAR_CONSOLE select POSTCAR_STAGE select REG_SCRIPT diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 7d82f3f..a8d9fd4 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -41,6 +41,7 @@ select TSC_SYNC_MFENCE select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS + select POOR_MICROCODE_MAINTENANCE select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SPI_CONSOLE_SUPPORT diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index fe0fa8d..88ba382 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -21,6 +21,7 @@ select IOAPIC select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS + select POOR_MICROCODE_MAINTENANCE # Microcode header files are delivered in FSP package select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN select INTEL_DESCRIPTOR_MODE_CAPABLE diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 727fccee..bd53c8b 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -33,6 +33,7 @@ select PARALLEL_MP select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 + select POOR_MICROCODE_MAINTENANCE select POSTCAR_CONSOLE select POSTCAR_STAGE select REG_SCRIPT -- To view, visit https://review.coreboot.org/c/coreboot/+/29934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib403402e240d3531640a62ce93b7a93b4ef6ca5e Gerrit-Change-Number: 29934 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: sb/intel/lynxpoint/usb_ehci.c: Don't use device_t
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29933 Change subject: sb/intel/lynxpoint/usb_ehci.c: Don't use device_t ...................................................................... sb/intel/lynxpoint/usb_ehci.c: Don't use device_t Use of device_t is deprecated. Change-Id: If2c24bbe6181ea6cf484c33a9fbf119f853efcf4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/lynxpoint/usb_ehci.c 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/29933/1 diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index e2486cf..7f300d6 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -25,7 +25,7 @@ #ifdef __SMM__ -void usb_ehci_disable(device_t dev) +void usb_ehci_disable(pci_devfn_t dev) { u16 reg16; u32 reg32; @@ -57,7 +57,7 @@ } /* Handler for EHCI controller on entry to S3/S4/S5 */ -void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ) +void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) { u32 reg32; u8 *bar0_base; @@ -164,7 +164,8 @@ printk(BIOS_DEBUG, "done.\n"); } -static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { u8 access_cntl; -- To view, visit https://review.coreboot.org/c/coreboot/+/29933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2c24bbe6181ea6cf484c33a9fbf119f853efcf4 Gerrit-Change-Number: 29933 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: src/soc/intel/braswell: Remove disabled LPE acpi code
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29414 ) Change subject: src/soc/intel/braswell: Remove disabled LPE acpi code ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29414/2/src/mainboard/intel/strago/ssdtlpe.… File src/mainboard/intel/strago/ssdtlpe.asl: https://review.coreboot.org/#/c/29414/2/src/mainboard/intel/strago/ssdtlpe.… PS2, Line 19: 1 2 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/29414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Gerrit-Change-Number: 29414 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 29 Nov 2018 15:20:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: sb/intel/lynxpoint/usb_xhci.c: Don't use device_t
by HAOUAS Elyes (Code Review) 29 Nov '18

29 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29932 Change subject: sb/intel/lynxpoint/usb_xhci.c: Don't use device_t ...................................................................... sb/intel/lynxpoint/usb_xhci.c: Don't use device_t Use of device_t is deprecated. Change-Id: Ie75450c844e2317ded157465eb0fc6a9ec1b3ab0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/lynxpoint/usb_xhci.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/29932/1 diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index af0e56f..186e3f9 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -154,7 +154,7 @@ #ifdef __SMM__ /* Handler for XHCI controller on entry to S3/S4/S5 */ -void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) +void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) { u16 reg16; u32 reg32; @@ -238,7 +238,7 @@ #else /* !__SMM__ */ -static void usb_xhci_clock_gating(device_t dev) +static void usb_xhci_clock_gating(struct device *dev) { u32 reg32; u16 reg16; @@ -285,7 +285,7 @@ pci_write_config32(dev, 0xa4, reg32); } -static void usb_xhci_init(device_t dev) +static void usb_xhci_init(struct device *dev) { u32 reg32; u16 reg16; @@ -359,8 +359,8 @@ } } -static void usb_xhci_set_subsystem(device_t dev, unsigned vendor, - unsigned device) +static void usb_xhci_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, -- To view, visit https://review.coreboot.org/c/coreboot/+/29932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie75450c844e2317ded157465eb0fc6a9ec1b3ab0 Gerrit-Change-Number: 29932 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: src/soc/intel/braswell: Remove disabled LPE acpi code
by Frans Hendriks (Code Review) 29 Nov '18

29 Nov '18

Hello Hannah Williams, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29414 to look at the new patch set (#2). Change subject: src/soc/intel/braswell: Remove disabled LPE acpi code ...................................................................... src/soc/intel/braswell: Remove disabled LPE acpi code The ACPI code for LPE device was included regardless of the availability of the LPE controller. Move the LPE ACPI code to seperate SSDT and hide it when LPE is disabled. BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/google/cyan/Makefile.inc M src/mainboard/google/cyan/acpi/codec_maxim.asl M src/mainboard/google/cyan/acpi/codec_realtek.asl A src/mainboard/google/cyan/ssdtlpe.asl M src/mainboard/intel/strago/Makefile.inc M src/mainboard/intel/strago/acpi/mainboard.asl A src/mainboard/intel/strago/ssdtlpe.asl M src/soc/intel/braswell/acpi/southcluster.asl M src/soc/intel/braswell/include/soc/acpi.h M src/soc/intel/braswell/lpe.c 10 files changed, 143 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/29414/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Gerrit-Change-Number: 29414 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: cpu/intel/fsp_model_406dx: Drop dead microcode reference
by Nico Huber (Code Review) 29 Nov '18

29 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29931 Change subject: cpu/intel/fsp_model_406dx: Drop dead microcode reference ...................................................................... cpu/intel/fsp_model_406dx: Drop dead microcode reference The referenced Kconfig symbols don't exist (anymore?). Change-Id: Ia724262a526fe960c17ae4b248acfa42fc342331 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/cpu/intel/fsp_model_406dx/Makefile.inc 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/29931/1 diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc index d82ddd6..26f4633 100644 --- a/src/cpu/intel/fsp_model_406dx/Makefile.inc +++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc @@ -19,8 +19,4 @@ ramstage-y += acpi.c -ifeq ($(CONFIG_HAVE_CPU_MICROCODE_FILE), y) -cpu_microcode_bins += $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE)) -endif - CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx -- To view, visit https://review.coreboot.org/c/coreboot/+/29931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia724262a526fe960c17ae4b248acfa42fc342331 Gerrit-Change-Number: 29931 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: nb/intel/gm45: Make fetching the blc_pwm freq global
by Nico Huber (Code Review) 29 Nov '18

29 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29925 ) Change subject: nb/intel/gm45: Make fetching the blc_pwm freq global ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3f6ba3ae31a5ab47f44d207678c1c4a6a43b7ec Gerrit-Change-Number: 29925 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 14:42:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: nb/intel/gm45: Make fetching the blc_pwm freq its own function
by Nico Huber (Code Review) 29 Nov '18

29 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29924 ) Change subject: nb/intel/gm45: Make fetching the blc_pwm freq its own function ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ad364f84f3658be98ce7ad3a6f0f0fe3247fc41 Gerrit-Change-Number: 29924 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Nov 2018 14:41:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2018