coreboot-gerrit October 2018

coreboot-gerrit@coreboot.org

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1285 discussions

Change in coreboot[master]: sifive/fu540: correct cbmem support
by build bot (Jenkins) (Code Review) 20 Oct '18

20 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29197 ) Change subject: sifive/fu540: correct cbmem support ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29197/1/src/soc/sifive/fu540/cbmem.c File src/soc/sifive/fu540/cbmem.c: https://review.coreboot.org/#/c/29197/1/src/soc/sifive/fu540/cbmem.c@25 PS1, Line 25: FU540_MAXDRAM); code indent should use tabs where possible -- To view, visit https://review.coreboot.org/29197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If7f490a46edebb04c2280bf317d1adacef08f30d Gerrit-Change-Number: 29197 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 19 Oct 2018 16:56:44 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: sifive/fu540: correct cbmem support
by Philipp Hug (Code Review) 20 Oct '18

20 Oct '18

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/29197 Change subject: sifive/fu540: correct cbmem support ...................................................................... sifive/fu540: correct cbmem support Return correct memory location for cbmem instead of incorrectly returning memory size. Change-Id: If7f490a46edebb04c2280bf317d1adacef08f30d Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/soc/sifive/fu540/cbmem.c M src/soc/sifive/fu540/include/soc/addressmap.h 2 files changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/29197/1 diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c index 8648370..61bff89 100644 --- a/src/soc/sifive/fu540/cbmem.c +++ b/src/soc/sifive/fu540/cbmem.c @@ -14,9 +14,13 @@ */ #include <cbmem.h> +#include <soc/addressmap.h> +#include <soc/sdram.h> +#include <stdlib.h> +#include <symbols.h> void *cbmem_top(void) { - /* dummy value */ - return (void *)(4ULL * GiB); + return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB, + FU540_MAXDRAM); } diff --git a/src/soc/sifive/fu540/include/soc/addressmap.h b/src/soc/sifive/fu540/include/soc/addressmap.h index 21709b5..7493630 100644 --- a/src/soc/sifive/fu540/include/soc/addressmap.h +++ b/src/soc/sifive/fu540/include/soc/addressmap.h @@ -34,3 +34,4 @@ #define FU540_QSPI0FLASH 0x20000000 #define FU540_QSPI1FLASH 0x30000000 #define FU540_DRAM 0x80000000 +#define FU540_MAXDRAM 0x2000000000 -- To view, visit https://review.coreboot.org/29197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If7f490a46edebb04c2280bf317d1adacef08f30d Gerrit-Change-Number: 29197 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

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Change in coreboot[master]: mb/lenovo/*/romstage: No need to specify board's model in comments
by Angel Pons (Code Review) 20 Oct '18

20 Oct '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/29180 ) Change subject: mb/lenovo/*/romstage: No need to specify board's model in comments ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I26b9296b402d98bcf048580da51da7bbb0c237e4 Gerrit-Change-Number: 29180 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 19 Oct 2018 15:43:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Typo fix (cosmetic)
by build bot (Jenkins) (Code Review) 19 Oct '18

19 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29196 ) Change subject: Typo fix (cosmetic) ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29196/1/src/northbridge/amd/amdht/h3finit.c File src/northbridge/amd/amdht/h3finit.c: https://review.coreboot.org/#/c/29196/1/src/northbridge/amd/amdht/h3finit.c… PS1, Line 1604: if (pDat->PortList[i].Link < 4) /* Only look for sublink1's */ line over 80 characters -- To view, visit https://review.coreboot.org/29196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I81985bd2836bdeb369587f170504a8a048ee496b Gerrit-Change-Number: 29196 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 19 Oct 2018 14:59:42 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: Typo fix (cosmetic)
by Peter Lemenkov (Code Review) 19 Oct '18

19 Oct '18

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/29196 Change subject: Typo fix (cosmetic) ...................................................................... Typo fix (cosmetic) Change-Id: I81985bd2836bdeb369587f170504a8a048ee496b Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/northbridge/amd/amdht/h3finit.c M src/southbridge/amd/sb800/hda.c M src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c M src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c M src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c M src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c M src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c M src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h 9 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/29196/1 diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index fc0c2d2..1e2d1a0 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -1601,7 +1601,7 @@ { if (pDat->PortList[i].Type != PORTLIST_TYPE_CPU) /* Must be a CPU link */ continue; - if (pDat->PortList[i].Link < 4) /* Only look for for sublink1's */ + if (pDat->PortList[i].Link < 4) /* Only look for sublink1's */ continue; for (j = 0; j < pDat->TotalLinks*2; j++) diff --git a/src/southbridge/amd/sb800/hda.c b/src/southbridge/amd/sb800/hda.c index 78e9862..feb0eb2 100644 --- a/src/southbridge/amd/sb800/hda.c +++ b/src/southbridge/amd/sb800/hda.c @@ -89,7 +89,7 @@ } /** - * Wait 50usec for for the codec to indicate it is ready + * Wait 50usec for the codec to indicate it is ready * no response would imply that the codec is non-operative */ static int wait_for_ready(void *base) @@ -110,7 +110,7 @@ } /** - * Wait 50usec for for the codec to indicate that it accepted + * Wait 50usec for the codec to indicate that it accepted * the previous command. No response would imply that the code * is non-operative */ diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c index ba4d4e7..2f4e098 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c +++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c @@ -115,7 +115,7 @@ /*---------------------------------------------------------------------------------------*/ /** - * BSC entry point for for enabling Core Performance Boost. + * BSC entry point for enabling Core Performance Boost. * * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG. * diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c index c7efe43..6d28bfe 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c @@ -113,7 +113,7 @@ /*---------------------------------------------------------------------------------------*/ /** - * BSC entry point for for enabling Core Performance Boost. + * BSC entry point for enabling Core Performance Boost. * * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG. * diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c index 77f0b65..1660c49 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c @@ -85,7 +85,7 @@ /*---------------------------------------------------------------------------------------*/ /** - * BSC entry point for for adding MMIO map + * BSC entry point for adding MMIO map * * program MMIO base/limit registers * diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c index db00c58..8d2fa34 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c @@ -141,7 +141,7 @@ /*---------------------------------------------------------------------------------------*/ /** - * BSC entry point for for enabling Core Performance Boost. + * BSC entry point for enabling Core Performance Boost. * * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG. * diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c index cf1d0d8..714f970 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c @@ -85,7 +85,7 @@ /*---------------------------------------------------------------------------------------*/ /** - * BSC entry point for for adding MMIO map + * BSC entry point for adding MMIO map * * program MMIO base/limit registers * diff --git a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c index 192a8a9..0fcc180 100644 --- a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c +++ b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c @@ -3295,7 +3295,7 @@ mem_size_mbytes *= 2; } - /* Mask with 1 bits set for for each active rank, allowing 2 bits per dimm. + /* Mask with 1 bits set for each active rank, allowing 2 bits per dimm. ** This makes later calculations simpler, as a variety of CSRs use this layout. ** This init needs to be updated for dual configs (ie non-identical DIMMs). ** Bit 0 = dimm0, rank 0 diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h index 12c6e44..d03a844 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h @@ -2978,8 +2978,8 @@ **/ UINT8 ThreeStrikeCounterDisable; -/** Offset 0x0899 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable. +/** Offset 0x0899 - Set HW P-State Interrupts Enabled for MISC_PWR_MGMT + Set HW P-State Interrupts Enabled for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable. $EN_DIS **/ UINT8 HwpInterruptControl; -- To view, visit https://review.coreboot.org/29196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I81985bd2836bdeb369587f170504a8a048ee496b Gerrit-Change-Number: 29196 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com>

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Change in coreboot[master]: Use standard pci_dev_set_subsystem function where possible
by Peter Lemenkov (Code Review) 19 Oct '18

19 Oct '18

Peter Lemenkov has posted comments on this change. ( https://review.coreboot.org/29195 ) Change subject: Use standard pci_dev_set_subsystem function where possible ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/29195/1/src/soc/intel/baytrail/pcie.c File src/soc/intel/baytrail/pcie.c: https://review.coreboot.org/#/c/29195/1/src/soc/intel/baytrail/pcie.c@242 PS1, Line 242: static void pcie_root_set_subsystem(struct device *dev, unsigned int vendor, > Prefer 'unsigned int' to bare use of 'unsigned' Done https://review.coreboot.org/#/c/29195/1/src/soc/intel/baytrail/pcie.c@243 PS1, Line 243: unsigned int device) > Prefer 'unsigned int' to bare use of 'unsigned' Done -- To view, visit https://review.coreboot.org/29195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I90c1ee9ddf8341291ccb82c1f699410c6e9fc104 Gerrit-Change-Number: 29195 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 19 Oct 2018 14:25:00 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: Use standard pci_dev_set_subsystem function where possible
by Peter Lemenkov (Code Review) 19 Oct '18

19 Oct '18

Peter Lemenkov has uploaded a new patch set (#2). ( https://review.coreboot.org/29195 ) Change subject: Use standard pci_dev_set_subsystem function where possible ...................................................................... Use standard pci_dev_set_subsystem function where possible We use the following pattern in many places: static void subsystemname_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, pci_read_config32(dev, PCI_VENDOR_ID)); } else { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } } Surprisingly but since commit fd891291 with Change-Id I5027331a6adf9109767415ba22dfcb17b35ef54b ("pci_device: Write vendor ID to subsystem vendor ID") pci_dev_enable_resources function does these checks and fills dev struct fields with vendor and device. So neither vendor nor device cannot be NULL. Let's use this generic function and avoid code duplication. We can replace set_subsystem function entirely in case of a standard address PCI_SUBSYSTEM_VENDOR_ID (0x2C), or at least simplify it (see src/drivers/ricoh/rce822/rce822.c for example). I've skipped three files: * src/southbridge/intel/i82801gx/pci.c * src/southbridge/intel/bd82x6x/pci.c * src/southbridge/intel/lynxpoint/pci.c These three files have calls to the set_subsystem function inside their own code, and I am not yet familiar with the codebase well enough to say for certain if it's fine or no to remove these checks for NULL. Change-Id: I90c1ee9ddf8341291ccb82c1f699410c6e9fc104 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/drivers/ricoh/rce822/rce822.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/fsp_rangeley/northbridge.c M src/northbridge/intel/fsp_sandybridge/gma.c M src/northbridge/intel/fsp_sandybridge/northbridge.c M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/nehalem/gma.c M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/pcie.c M src/northbridge/intel/x4x/gma.c M src/soc/intel/baytrail/chip.c M src/soc/intel/baytrail/pcie.c M src/soc/intel/braswell/chip.c M src/soc/intel/braswell/pcie.c M src/soc/intel/broadwell/chip.c M src/soc/intel/broadwell/ehci.c M src/soc/intel/broadwell/pcie.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/denverton_ns/chip.c M src/soc/intel/fsp_baytrail/chip.c M src/soc/intel/fsp_broadwell_de/chip.c M src/southbridge/amd/amd8111/ac97.c M src/southbridge/broadcom/bcm5785/sb_pci_main.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/pcie.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/bd82x6x/smbus.c M src/southbridge/intel/bd82x6x/usb_ehci.c M src/southbridge/intel/bd82x6x/usb_xhci.c M src/southbridge/intel/fsp_bd82x6x/azalia.c M src/southbridge/intel/fsp_bd82x6x/lpc.c M src/southbridge/intel/fsp_bd82x6x/me.c M src/southbridge/intel/fsp_bd82x6x/me_8.x.c M src/southbridge/intel/fsp_bd82x6x/sata.c M src/southbridge/intel/fsp_i89xx/lpc.c M src/southbridge/intel/fsp_i89xx/me.c M src/southbridge/intel/fsp_i89xx/me_8.x.c M src/southbridge/intel/fsp_i89xx/sata.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/fsp_rangeley/sata.c M src/southbridge/intel/fsp_rangeley/smbus.c M src/southbridge/intel/i82801gx/ac97.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801gx/ide.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/pcie.c M src/southbridge/intel/i82801gx/sata.c M src/southbridge/intel/i82801gx/smbus.c M src/southbridge/intel/i82801gx/usb.c M src/southbridge/intel/i82801gx/usb_ehci.c M src/southbridge/intel/i82801ix/hdaudio.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/pci.c M src/southbridge/intel/i82801ix/pcie.c M src/southbridge/intel/i82801ix/sata.c M src/southbridge/intel/i82801ix/smbus.c M src/southbridge/intel/i82801ix/thermal.c M src/southbridge/intel/i82801ix/usb_ehci.c M src/southbridge/intel/i82801jx/hdaudio.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/pci.c M src/southbridge/intel/i82801jx/pcie.c M src/southbridge/intel/i82801jx/sata.c M src/southbridge/intel/i82801jx/smbus.c M src/southbridge/intel/i82801jx/thermal.c M src/southbridge/intel/i82801jx/usb_ehci.c M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/ibexpeak/smbus.c M src/southbridge/intel/ibexpeak/thermal.c M src/southbridge/intel/ibexpeak/usb_ehci.c M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/smbus.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c M src/southbridge/nvidia/mcp55/azalia.c 94 files changed, 118 insertions(+), 1,080 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/29195/2 -- To view, visit https://review.coreboot.org/29195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I90c1ee9ddf8341291ccb82c1f699410c6e9fc104 Gerrit-Change-Number: 29195 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: Use standard pci_dev_set_subsystem function where possible
by build bot (Jenkins) (Code Review) 19 Oct '18

19 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29195 ) Change subject: Use standard pci_dev_set_subsystem function where possible ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/29195/1/src/soc/intel/baytrail/pcie.c File src/soc/intel/baytrail/pcie.c: https://review.coreboot.org/#/c/29195/1/src/soc/intel/baytrail/pcie.c@242 PS1, Line 242: static void pcie_root_set_subsystem(struct device *dev, unsigned vendor, Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29195/1/src/soc/intel/baytrail/pcie.c@243 PS1, Line 243: unsigned device) Prefer 'unsigned int' to bare use of 'unsigned' -- To view, visit https://review.coreboot.org/29195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I90c1ee9ddf8341291ccb82c1f699410c6e9fc104 Gerrit-Change-Number: 29195 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 19 Oct 2018 14:23:08 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: Use standard pci_dev_set_subsystem function where possible
by Peter Lemenkov (Code Review) 19 Oct '18

19 Oct '18

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/29195 Change subject: Use standard pci_dev_set_subsystem function where possible ...................................................................... Use standard pci_dev_set_subsystem function where possible We use the following pattern in many places: static void subsystemname_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, pci_read_config32(dev, PCI_VENDOR_ID)); } else { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } } Surprisingly but since commit fd891291 with Change-Id I5027331a6adf9109767415ba22dfcb17b35ef54b ("pci_device: Write vendor ID to subsystem vendor ID") pci_dev_enable_resources function does these checks and fills dev struct fields with vendor and device. So neither vendor nor device cannot be NULL. Let's use this generic function and avoid code duplication. We can replace set_subsystem function entirely in case of a standard address PCI_SUBSYSTEM_VENDOR_ID (0x2C), or at least simplify it (see src/drivers/ricoh/rce822/rce822.c for example). I've skipped three files: * src/southbridge/intel/i82801gx/pci.c * src/southbridge/intel/bd82x6x/pci.c * src/southbridge/intel/lynxpoint/pci.c These three files have calls to the set_subsystem function inside their own code, and I am not yet familiar with the codebase well enough to say for certain if it's fine or no to remove these checks for NULL. Change-Id: I90c1ee9ddf8341291ccb82c1f699410c6e9fc104 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/drivers/ricoh/rce822/rce822.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/fsp_rangeley/northbridge.c M src/northbridge/intel/fsp_sandybridge/gma.c M src/northbridge/intel/fsp_sandybridge/northbridge.c M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/nehalem/gma.c M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/pcie.c M src/northbridge/intel/x4x/gma.c M src/soc/intel/baytrail/chip.c M src/soc/intel/baytrail/pcie.c M src/soc/intel/braswell/chip.c M src/soc/intel/braswell/pcie.c M src/soc/intel/broadwell/chip.c M src/soc/intel/broadwell/ehci.c M src/soc/intel/broadwell/pcie.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/denverton_ns/chip.c M src/soc/intel/fsp_baytrail/chip.c M src/soc/intel/fsp_broadwell_de/chip.c M src/southbridge/amd/amd8111/ac97.c M src/southbridge/broadcom/bcm5785/sb_pci_main.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/pcie.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/bd82x6x/smbus.c M src/southbridge/intel/bd82x6x/usb_ehci.c M src/southbridge/intel/bd82x6x/usb_xhci.c M src/southbridge/intel/fsp_bd82x6x/azalia.c M src/southbridge/intel/fsp_bd82x6x/lpc.c M src/southbridge/intel/fsp_bd82x6x/me.c M src/southbridge/intel/fsp_bd82x6x/me_8.x.c M src/southbridge/intel/fsp_bd82x6x/sata.c M src/southbridge/intel/fsp_i89xx/lpc.c M src/southbridge/intel/fsp_i89xx/me.c M src/southbridge/intel/fsp_i89xx/me_8.x.c M src/southbridge/intel/fsp_i89xx/sata.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/fsp_rangeley/sata.c M src/southbridge/intel/fsp_rangeley/smbus.c M src/southbridge/intel/i82801gx/ac97.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801gx/ide.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/pcie.c M src/southbridge/intel/i82801gx/sata.c M src/southbridge/intel/i82801gx/smbus.c M src/southbridge/intel/i82801gx/usb.c M src/southbridge/intel/i82801gx/usb_ehci.c M src/southbridge/intel/i82801ix/hdaudio.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/pci.c M src/southbridge/intel/i82801ix/pcie.c M src/southbridge/intel/i82801ix/sata.c M src/southbridge/intel/i82801ix/smbus.c M src/southbridge/intel/i82801ix/thermal.c M src/southbridge/intel/i82801ix/usb_ehci.c M src/southbridge/intel/i82801jx/hdaudio.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/pci.c M src/southbridge/intel/i82801jx/pcie.c M src/southbridge/intel/i82801jx/sata.c M src/southbridge/intel/i82801jx/smbus.c M src/southbridge/intel/i82801jx/thermal.c M src/southbridge/intel/i82801jx/usb_ehci.c M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/ibexpeak/smbus.c M src/southbridge/intel/ibexpeak/thermal.c M src/southbridge/intel/ibexpeak/usb_ehci.c M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/smbus.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c M src/southbridge/nvidia/mcp55/azalia.c 94 files changed, 118 insertions(+), 1,080 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/29195/1 diff --git a/src/drivers/ricoh/rce822/rce822.c b/src/drivers/ricoh/rce822/rce822.c index b364946..6e314ef 100644 --- a/src/drivers/ricoh/rce822/rce822.c +++ b/src/drivers/ricoh/rce822/rce822.c @@ -41,13 +41,8 @@ static void rce822_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { - if (!vendor || !device) { - pci_write_config32(dev, 0xac, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, 0xac, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } + pci_write_config32(dev, 0xac, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index a5dc6cd..c50efc0 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -75,15 +75,8 @@ assign_resources(dev->link_list); } -static void intel_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - static struct pci_operations intel_pci_ops = { - .set_subsystem = intel_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations pci_domain_ops = { diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 72b2761..2337ab4 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -173,18 +173,6 @@ pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void northbridge_init(struct device *dev) { } @@ -194,7 +182,7 @@ } static struct pci_operations intel_pci_ops = { - .set_subsystem = intel_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations pci_domain_ops = { diff --git a/src/northbridge/intel/fsp_sandybridge/gma.c b/src/northbridge/intel/fsp_sandybridge/gma.c index cba5869..8fd200f 100644 --- a/src/northbridge/intel/fsp_sandybridge/gma.c +++ b/src/northbridge/intel/fsp_sandybridge/gma.c @@ -66,18 +66,6 @@ gnvs_ptr->aslb = aslb; } -static void gma_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { @@ -153,7 +141,7 @@ } static struct pci_operations gma_pci_ops = { - .set_subsystem = gma_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations gma_func0_ops = { diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index 111c201..0f0cb56 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -248,18 +248,6 @@ } } -static void intel_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void northbridge_init(struct device *dev) { u8 bios_reset_cpl; @@ -302,7 +290,7 @@ } static struct pci_operations intel_pci_ops = { - .set_subsystem = intel_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations mc_ops = { diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index b86e2b3..ef9fd24 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -788,19 +788,6 @@ intel_gma_restore_opregion(); } -static void gma_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & - 0xffff)); - } -} - const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { @@ -854,7 +841,7 @@ } static struct pci_operations gma_pci_ops = { - .set_subsystem = gma_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations gma_func0_ops = { diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index efc9fa3..582d32b 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -494,18 +494,6 @@ intel_gma_restore_opregion(); } -static void gma_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { @@ -553,7 +541,7 @@ } static struct pci_operations gma_pci_ops = { - .set_subsystem = gma_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations gma_func0_ops = { diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index 52710bb..ebd8b64 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -103,20 +103,8 @@ } } -static void minihd_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations minihd_pci_ops = { - .set_subsystem = minihd_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations minihd_ops = { diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 0453246..d8cb375 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -408,18 +408,6 @@ mc_add_dram_resources(dev, &index); } -static void intel_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void northbridge_init(struct device *dev) { u8 bios_reset_cpl, pair; @@ -448,7 +436,7 @@ } static struct pci_operations intel_pci_ops = { - .set_subsystem = intel_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations mc_ops = { diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 83dc42e..011d4b5 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -754,18 +754,6 @@ pci_write_config8(dev, 0xf4, 0xff); } -static void gma_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { @@ -832,7 +820,7 @@ } static struct pci_operations gma_pci_ops = { - .set_subsystem = gma_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations gma_func0_ops = { diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index d3539b8..c03f547 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -160,19 +160,8 @@ } } -static void intel_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} static struct pci_operations intel_pci_ops = { - .set_subsystem = intel_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations mc_ops = { diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index b89215d..b376955 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -623,19 +623,6 @@ intel_gma_restore_opregion(); } -static void gma_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & - 0xffff)); - } -} - static void gma_read_resources(struct device *dev) { pci_dev_read_resources(dev); @@ -703,7 +690,7 @@ } static struct pci_operations gma_pci_ops = { - .set_subsystem = gma_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations gma_func0_ops = { diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 4c6cdd4..44e399f 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -191,19 +191,6 @@ pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & - 0xffff)); - } -} - static void northbridge_dmi_init(struct device *dev) { u32 reg32; @@ -305,7 +292,7 @@ } static struct pci_operations intel_pci_ops = { - .set_subsystem = intel_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations mc_ops = { diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index e075ac1..2478179 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -304,19 +304,6 @@ intel_gma_restore_opregion(); } -static void gma_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & - 0xffff)); - } -} - const struct i915_gpu_controller_info *intel_gma_get_controller_info(void) { struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); @@ -360,7 +347,7 @@ } static struct pci_operations gma_pci_ops = { - .set_subsystem = gma_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations gma_func0_ops = { diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index cd8f7b9..57d3308 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -669,18 +669,6 @@ intel_gma_restore_opregion(); } -static void gma_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { @@ -747,7 +735,7 @@ } static struct pci_operations gma_pci_ops = { - .set_subsystem = gma_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations gma_func0_ops = { diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index cb0e5db..8b86ed2 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -287,18 +287,6 @@ } } -static void intel_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void northbridge_dmi_init(struct device *dev) { u32 reg32; @@ -486,7 +474,7 @@ } static struct pci_operations intel_pci_ops = { - .set_subsystem = intel_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations mc_ops = { diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c index bb88c7a..694d72e 100644 --- a/src/northbridge/intel/sandybridge/pcie.c +++ b/src/northbridge/intel/sandybridge/pcie.c @@ -65,15 +65,11 @@ #endif static void -pcie_set_subsystem(struct device *dev, unsigned int ven, unsigned int device) +pcie_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) { /* NOTE: This is not the default position! */ - if (!ven || !device) - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - else - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (ven & 0xffff)); + pci_write_config32(dev, 0x94, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations pci_ops = { diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 1fcc682..b1b88db 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -101,19 +101,6 @@ pci_write_config16(dev_host, D0F0_GGC, ggc); } -static void gma_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & - 0xffff)); - } -} - const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { @@ -165,7 +152,7 @@ } static struct pci_operations gma_pci_ops = { - .set_subsystem = gma_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations gma_func0_ops = { diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index 94a5a8e..0d165b5 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -72,18 +72,6 @@ .init = soc_init, }; -static void pci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - struct pci_operations soc_pci_ops = { - .set_subsystem = &pci_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 7208e88..4f786dc 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -239,14 +239,11 @@ do_pci_scan_bridge(dev, pciexp_scan_bus); } -static void pcie_root_set_subsystem(struct device *dev, unsigned vid, - unsigned did) +static void pcie_root_set_subsystem(struct device *dev, unsigned vendor, + unsigned device) { - uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff); - - if (!didvid) - didvid = pci_read_config32(dev, PCI_VENDOR_ID); - pci_write_config32(dev, 0x94, didvid); + pci_write_config32(dev, 0x94, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations pcie_root_ops = { diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 4d13539..2a72811 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -381,22 +381,8 @@ .init = soc_init, }; -static void pci_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n", - __FILE__, __func__, dev_name(dev), vendor, device); - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - struct pci_operations soc_pci_ops = { - .set_subsystem = &pci_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; /** diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c index 1a127f4..799c79f 100644 --- a/src/soc/intel/braswell/pcie.c +++ b/src/soc/intel/braswell/pcie.c @@ -159,16 +159,11 @@ southcluster_enable_dev(dev); } -static void pcie_root_set_subsystem(struct device *dev, unsigned int vid, - unsigned int did) +static void pcie_root_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { - printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n", - __FILE__, __func__, dev_name(dev), vid, did); - uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff); - - if (!didvid) - didvid = pci_read_config32(dev, PCI_VENDOR_ID); - pci_write_config32(dev, 0x94, didvid); + pci_write_config32(dev, 0x94, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations pcie_root_ops = { diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c index 70afa0d..6bdc23a 100644 --- a/src/soc/intel/broadwell/chip.c +++ b/src/soc/intel/broadwell/chip.c @@ -64,17 +64,6 @@ .init = &broadwell_init_pre_device, }; -static void pci_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - else - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - (device << 16) | vendor); -} - struct pci_operations broadwell_pci_ops = { - .set_subsystem = &pci_set_subsystem + .set_subsystem = pci_dev_set_subsystem, }; diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/ehci.c index b1ead77..a8ff621 100644 --- a/src/soc/intel/broadwell/ehci.c +++ b/src/soc/intel/broadwell/ehci.c @@ -34,13 +34,8 @@ /* Enable writes to protected registers. */ pci_write_config8(dev, 0x80, access_cntl | 1); - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); /* Restore protection. */ pci_write_config8(dev, 0x80, access_cntl); diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 3fd5ea4..5ea94ca 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -653,10 +653,8 @@ unsigned int device) { /* NOTE: This is not the default position! */ - if (!vendor || !device) - pci_write_config32(dev, 0x94, pci_read_config32(dev, 0)); - else - pci_write_config32(dev, 0x94, (device << 16) | vendor); + pci_write_config32(dev, 0x94, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off) diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 2ec37e2..9bd6548 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -72,16 +72,9 @@ PCIE_LTR_MAX_SNOOP_LATENCY_VALUE); } -static void pcie_dev_set_subsystem(struct device *dev, - unsigned vendor, unsigned device) -{ - pci_write_config32(dev, PCIE_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - static struct pci_operations pcie_ops = { .set_L1_ss_latency = pcie_set_L1_ss_max_latency, - .set_subsystem = pcie_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index 05dcb76..4618632 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -130,21 +130,8 @@ .final = &soc_final }; -static void soc_set_subsystem(struct device *dev, uint32_t vendor, - uint32_t device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | - (vendor & 0xffff)); - } -} - struct pci_operations soc_pci_ops = { - .set_subsystem = soc_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; /* diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c index a041b81..ece6e60 100644 --- a/src/soc/intel/fsp_baytrail/chip.c +++ b/src/soc/intel/fsp_baytrail/chip.c @@ -73,17 +73,6 @@ .init = soc_init, }; -static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - struct pci_operations soc_pci_ops = { - .set_subsystem = &pci_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; diff --git a/src/soc/intel/fsp_broadwell_de/chip.c b/src/soc/intel/fsp_broadwell_de/chip.c index 2564944..f542ec1 100644 --- a/src/soc/intel/fsp_broadwell_de/chip.c +++ b/src/soc/intel/fsp_broadwell_de/chip.c @@ -89,18 +89,6 @@ .init = soc_init, }; -static void pci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - struct pci_operations soc_pci_ops = { - .set_subsystem = &pci_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; diff --git a/src/southbridge/amd/amd8111/ac97.c b/src/southbridge/amd/amd8111/ac97.c index ce5911f..d1beb79 100644 --- a/src/southbridge/amd/amd8111/ac97.c +++ b/src/southbridge/amd/amd8111/ac97.c @@ -20,15 +20,8 @@ #include <device/pci_ops.h> #include "amd8111.h" -static void lpci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - pci_write_config32(dev, 0x2c, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations ac97audio_ops = { diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c index 5d98e7b..604cc20 100644 --- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c @@ -135,15 +135,8 @@ .write_byte = lsmbus_write_byte, }; -static void lpci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - pci_write_config32(dev, 0x2c, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations sb_ops = { diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index d5721e6..4f407d2 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -336,20 +336,8 @@ return "HDEF"; } -static void azalia_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations azalia_pci_ops = { - .set_subsystem = azalia_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations azalia_ops = { diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 271b5b0..5feadab 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -710,17 +710,6 @@ pch_enable(dev); } -static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void southbridge_inject_dsdt(struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); @@ -938,7 +927,7 @@ } static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index da1c7e4..eb73be7 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -736,19 +736,8 @@ } } -static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 1a59dc4..e527167 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -739,19 +739,8 @@ } } -static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 5605841..80961fe 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -309,13 +309,8 @@ unsigned device) { /* NOTE: This is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } + pci_write_config32(dev, 0x94, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations pci_ops = { diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 00a65c8..7c20055 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -233,18 +233,6 @@ pci_write_config16(dev, 0x90, map); } -static void sata_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static const char *sata_acpi_name(const struct device *dev) { return "SATA"; @@ -257,7 +245,7 @@ } static struct pci_operations sata_pci_ops = { - .set_subsystem = sata_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index 1754734..d0fd505 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -72,20 +72,8 @@ .write_byte = lsmbus_write_byte, }; -static void smbus_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations smbus_pci_ops = { - .set_subsystem = smbus_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static void smbus_read_resources(struct device *dev) diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index 996c89c..c64f09a 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -83,13 +83,8 @@ /* Enable writes to protected registers. */ pci_write_config8(dev, 0x80, access_cntl | 1); - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); /* Restore protection. */ pci_write_config8(dev, 0x80, access_cntl); diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c index 1b2755b..b8c722a 100644 --- a/src/southbridge/intel/bd82x6x/usb_xhci.c +++ b/src/southbridge/intel/bd82x6x/usb_xhci.c @@ -56,20 +56,8 @@ return "XHC"; } -static void xhci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations xhci_pci_ops = { - .set_subsystem = xhci_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations usb_xhci_ops = { diff --git a/src/southbridge/intel/fsp_bd82x6x/azalia.c b/src/southbridge/intel/fsp_bd82x6x/azalia.c index a152796..3ca7393 100644 --- a/src/southbridge/intel/fsp_bd82x6x/azalia.c +++ b/src/southbridge/intel/fsp_bd82x6x/azalia.c @@ -334,20 +334,8 @@ pci_write_config8(dev, 0x43, reg8); } -static void azalia_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations azalia_pci_ops = { - .set_subsystem = azalia_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations azalia_ops = { diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index 431587d..97aaf55 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -575,17 +575,6 @@ pch_enable(dev); } -static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void southbridge_inject_dsdt(struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); @@ -751,7 +740,7 @@ } static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c index f3a7824..be54d90 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.c +++ b/src/southbridge/intel/fsp_bd82x6x/me.c @@ -735,19 +735,8 @@ } } -static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c index fb68d6d..75c361e 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c +++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c @@ -737,19 +737,8 @@ } } -static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/fsp_bd82x6x/sata.c b/src/southbridge/intel/fsp_bd82x6x/sata.c index 656dfde..acfb0e4 100644 --- a/src/southbridge/intel/fsp_bd82x6x/sata.c +++ b/src/southbridge/intel/fsp_bd82x6x/sata.c @@ -82,20 +82,8 @@ { } -static void sata_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations sata_pci_ops = { - .set_subsystem = sata_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/fsp_i89xx/lpc.c b/src/southbridge/intel/fsp_i89xx/lpc.c index f584f36..7e59b7e 100644 --- a/src/southbridge/intel/fsp_i89xx/lpc.c +++ b/src/southbridge/intel/fsp_i89xx/lpc.c @@ -487,17 +487,6 @@ pch_enable(dev); } -static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void southbridge_inject_dsdt(struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); @@ -652,7 +641,7 @@ } static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/fsp_i89xx/me.c b/src/southbridge/intel/fsp_i89xx/me.c index 5dfd70d..db93b92 100644 --- a/src/southbridge/intel/fsp_i89xx/me.c +++ b/src/southbridge/intel/fsp_i89xx/me.c @@ -702,19 +702,8 @@ } } -static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/fsp_i89xx/me_8.x.c b/src/southbridge/intel/fsp_i89xx/me_8.x.c index b2f3076..03b6de0 100644 --- a/src/southbridge/intel/fsp_i89xx/me_8.x.c +++ b/src/southbridge/intel/fsp_i89xx/me_8.x.c @@ -692,19 +692,8 @@ } } -static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/fsp_i89xx/sata.c b/src/southbridge/intel/fsp_i89xx/sata.c index bbd21e0..33d3ebd 100644 --- a/src/southbridge/intel/fsp_i89xx/sata.c +++ b/src/southbridge/intel/fsp_i89xx/sata.c @@ -82,20 +82,8 @@ { } -static void sata_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations sata_pci_ops = { - .set_subsystem = sata_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 88cc73f..260e116 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -416,17 +416,6 @@ soc_enable(dev); } -static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void southbridge_inject_dsdt(struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); @@ -447,7 +436,7 @@ } static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c index c1d5749..658c7a7 100644 --- a/src/southbridge/intel/fsp_rangeley/sata.c +++ b/src/southbridge/intel/fsp_rangeley/sata.c @@ -95,19 +95,8 @@ { } -static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations sata_pci_ops = { - .set_subsystem = sata_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/fsp_rangeley/smbus.c b/src/southbridge/intel/fsp_rangeley/smbus.c index 0ffe45e..fadd2d7 100644 --- a/src/southbridge/intel/fsp_rangeley/smbus.c +++ b/src/southbridge/intel/fsp_rangeley/smbus.c @@ -42,20 +42,8 @@ .read_byte = lsmbus_read_byte, }; -static void smbus_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations smbus_pci_ops = { - .set_subsystem = smbus_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static void rangeley_smbus_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801gx/ac97.c b/src/southbridge/intel/i82801gx/ac97.c index 9bf9456..0713572 100644 --- a/src/southbridge/intel/i82801gx/ac97.c +++ b/src/southbridge/intel/i82801gx/ac97.c @@ -246,20 +246,8 @@ } } -static void ac97_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations ac97_pci_ops = { - .set_subsystem = ac97_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations ac97_audio_ops = { diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index f1866a5..6bd6247 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -303,20 +303,8 @@ } } -static void azalia_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations azalia_pci_ops = { - .set_subsystem = azalia_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations azalia_ops = { diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c index 9709272..43c7080 100644 --- a/src/southbridge/intel/i82801gx/ide.c +++ b/src/southbridge/intel/i82801gx/ide.c @@ -91,20 +91,8 @@ printk(BIOS_DEBUG, "\n"); } -static void ide_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations ide_pci_ops = { - .set_subsystem = ide_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations ide_ops = { diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 6c8331f..32427a2 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -680,18 +680,6 @@ outb(POST_OS_BOOT, 0x80); } -static void set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void southbridge_inject_dsdt(struct device *dev) { global_nvs_t *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); @@ -730,7 +718,7 @@ } static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 7de9890..52f2a31 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -93,13 +93,8 @@ unsigned int device) { /* NOTE: This is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } + pci_write_config32(dev, 0x94, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations pci_ops = { diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 588d687..0c6cddf 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -199,20 +199,8 @@ pci_write_config32(dev, SATA_IR, reg32); } -static void sata_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations sata_pci_ops = { - .set_subsystem = sata_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c index 917321c..b7c3690 100644 --- a/src/southbridge/intel/i82801gx/smbus.c +++ b/src/southbridge/intel/i82801gx/smbus.c @@ -82,20 +82,8 @@ .block_write = lsmbus_block_write, }; -static void smbus_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations smbus_pci_ops = { - .set_subsystem = smbus_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static void smbus_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c index eaa2cf1..61da57e 100644 --- a/src/southbridge/intel/i82801gx/usb.c +++ b/src/southbridge/intel/i82801gx/usb.c @@ -42,20 +42,8 @@ printk(BIOS_DEBUG, "done.\n"); } -static void usb_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations usb_pci_ops = { - .set_subsystem = usb_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations usb_ops = { diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index b40c83d..7ea43d2 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -68,13 +68,8 @@ /* Enable writes to protected registers. */ pci_write_config8(dev, 0x80, access_cntl | 1); - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); /* Restore protection. */ pci_write_config8(dev, 0x80, access_cntl); diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c index 607604b..faca0c9 100644 --- a/src/southbridge/intel/i82801ix/hdaudio.c +++ b/src/southbridge/intel/i82801ix/hdaudio.c @@ -287,20 +287,8 @@ } } -static void azalia_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations azalia_pci_ops = { - .set_subsystem = azalia_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations azalia_ops = { diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 18bfcf3..f9a0f6e 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -526,17 +526,6 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void southbridge_inject_dsdt(struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); @@ -575,7 +564,7 @@ } static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/i82801ix/pci.c b/src/southbridge/intel/i82801ix/pci.c index 13f92f0..71637cd 100644 --- a/src/southbridge/intel/i82801ix/pci.c +++ b/src/southbridge/intel/i82801ix/pci.c @@ -46,13 +46,8 @@ static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { /* NOTE: 0x54 is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x54, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, 0x54, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } + pci_write_config32(dev, 0x54, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations pci_ops = { diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index 04eb9b9..26c00b4 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -98,13 +98,8 @@ unsigned device) { /* NOTE: 0x94 is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } + pci_write_config32(dev, 0x94, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static void pch_pciexp_scan_bridge(struct device *dev) diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index dcdeeb4..f4ab1c3 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -252,20 +252,8 @@ pci_write_config16(dev, 0x90, map); } -static void sata_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations sata_pci_ops = { - .set_subsystem = sata_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/i82801ix/smbus.c b/src/southbridge/intel/i82801ix/smbus.c index dc45510..46a3546 100644 --- a/src/southbridge/intel/i82801ix/smbus.c +++ b/src/southbridge/intel/i82801ix/smbus.c @@ -66,20 +66,8 @@ .write_byte = lsmbus_write_byte, }; -static void smbus_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations smbus_pci_ops = { - .set_subsystem = smbus_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static void smbus_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801ix/thermal.c b/src/southbridge/intel/i82801ix/thermal.c index 5f40d2e..49ddefa 100644 --- a/src/southbridge/intel/i82801ix/thermal.c +++ b/src/southbridge/intel/i82801ix/thermal.c @@ -50,20 +50,8 @@ pci_write_config32(dev, 0x10, 0); } -static void thermal_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations thermal_pci_ops = { - .set_subsystem = thermal_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/i82801ix/usb_ehci.c b/src/southbridge/intel/i82801ix/usb_ehci.c index e386f82..5074bf1 100644 --- a/src/southbridge/intel/i82801ix/usb_ehci.c +++ b/src/southbridge/intel/i82801ix/usb_ehci.c @@ -43,13 +43,8 @@ /* Enable writes to protected registers. */ pci_write_config8(dev, 0x80, access_cntl | 1); - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); /* Restore protection. */ pci_write_config8(dev, 0x80, access_cntl); diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/hdaudio.c index 0c9d39c..eeec3f6 100644 --- a/src/southbridge/intel/i82801jx/hdaudio.c +++ b/src/southbridge/intel/i82801jx/hdaudio.c @@ -287,20 +287,8 @@ } } -static void azalia_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations azalia_pci_ops = { - .set_subsystem = azalia_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations azalia_ops = { diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index cd5e307..7dd707e 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -688,17 +688,6 @@ } } -static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void southbridge_inject_dsdt(struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); @@ -736,7 +725,7 @@ } static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/i82801jx/pci.c b/src/southbridge/intel/i82801jx/pci.c index cfafda0..8927319 100644 --- a/src/southbridge/intel/i82801jx/pci.c +++ b/src/southbridge/intel/i82801jx/pci.c @@ -46,13 +46,8 @@ static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { /* NOTE: 0x54 is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x54, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, 0x54, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } + pci_write_config32(dev, 0x54, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations pci_ops = { diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c index f5eaca5..2b21ae6 100644 --- a/src/southbridge/intel/i82801jx/pcie.c +++ b/src/southbridge/intel/i82801jx/pcie.c @@ -98,13 +98,8 @@ unsigned device) { /* NOTE: 0x94 is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } + pci_write_config32(dev, 0x94, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static void pch_pciexp_scan_bridge(struct device *dev) diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index b511c54..3ed1c38 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -252,20 +252,8 @@ pci_write_config16(dev, 0x90, map); } -static void sata_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations sata_pci_ops = { - .set_subsystem = sata_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/i82801jx/smbus.c b/src/southbridge/intel/i82801jx/smbus.c index d3f0711..a76628d 100644 --- a/src/southbridge/intel/i82801jx/smbus.c +++ b/src/southbridge/intel/i82801jx/smbus.c @@ -93,20 +93,8 @@ .block_write = lsmbus_block_write, }; -static void smbus_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations smbus_pci_ops = { - .set_subsystem = smbus_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static void smbus_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801jx/thermal.c b/src/southbridge/intel/i82801jx/thermal.c index ae111a6..9e2d5b4 100644 --- a/src/southbridge/intel/i82801jx/thermal.c +++ b/src/southbridge/intel/i82801jx/thermal.c @@ -50,20 +50,8 @@ pci_write_config32(dev, 0x10, 0); } -static void thermal_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations thermal_pci_ops = { - .set_subsystem = thermal_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/i82801jx/usb_ehci.c b/src/southbridge/intel/i82801jx/usb_ehci.c index 0aad672..7ee189e 100644 --- a/src/southbridge/intel/i82801jx/usb_ehci.c +++ b/src/southbridge/intel/i82801jx/usb_ehci.c @@ -43,13 +43,8 @@ /* Enable writes to protected registers. */ pci_write_config8(dev, 0x80, access_cntl | 1); - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); /* Restore protection. */ pci_write_config8(dev, 0x80, access_cntl); diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 9e3ed43..7178cf2 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -313,20 +313,8 @@ pci_write_config8(dev, 0x43, reg8); } -static void azalia_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations azalia_pci_ops = { - .set_subsystem = azalia_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations azalia_ops = { diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index b09951f..23c6959 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -607,18 +607,6 @@ pch_enable(dev); } -static void set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void southbridge_inject_dsdt(struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); @@ -802,7 +790,7 @@ } static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 0d75350..21656ae 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -611,20 +611,8 @@ } } -static void set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 3833e12..8400b06 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -234,19 +234,6 @@ pci_write_config16(dev, 0x90, map); } -static void sata_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & - 0xffff)); - } -} - static void sata_fill_ssdt(struct device *dev) { config_t *config = dev->chip_info; @@ -254,7 +241,7 @@ } static struct pci_operations sata_pci_ops = { - .set_subsystem = sata_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c index 53aecef..71dd3a6 100644 --- a/src/southbridge/intel/ibexpeak/smbus.c +++ b/src/southbridge/intel/ibexpeak/smbus.c @@ -72,20 +72,8 @@ .write_byte = lsmbus_write_byte, }; -static void smbus_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations smbus_pci_ops = { - .set_subsystem = smbus_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static void smbus_read_resources(struct device *dev) diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c index 374cbf1..4bdd946 100644 --- a/src/southbridge/intel/ibexpeak/thermal.c +++ b/src/southbridge/intel/ibexpeak/thermal.c @@ -44,21 +44,8 @@ printk(BIOS_DEBUG, "Thermal init done.\n"); } -static void set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & - 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations thermal_ops = { diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index 13670b8..b3e4bef 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -77,14 +77,8 @@ /* Enable writes to protected registers. */ pci_write_config8(dev, 0x80, access_cntl | 1); - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & - 0xffff)); - } + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); /* Restore protection. */ pci_write_config8(dev, 0x80, access_cntl); diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index 38db1a4..a07e078 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -154,20 +154,8 @@ } } -static void azalia_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations azalia_pci_ops = { - .set_subsystem = azalia_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations azalia_ops = { diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 5b09fed..c175827 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -738,17 +738,6 @@ pch_enable(dev); } -static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void southbridge_inject_dsdt(struct device *dev) { global_nvs_t *gnvs; @@ -828,7 +817,7 @@ static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 6168498..7351e46 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -858,19 +858,8 @@ */ } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static void intel_me_enable(device_t dev) diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index a7966f1..7262e82 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -719,13 +719,8 @@ unsigned device) { /* NOTE: This is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } + pci_write_config32(dev, 0x94, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations pci_ops = { diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 30e8aa8..581674d 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -322,20 +322,8 @@ pci_write_config16(dev, 0x90, map); } -static void sata_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations sata_pci_ops = { - .set_subsystem = sata_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 92fa950..19860fb 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -237,20 +237,8 @@ } } -static void serialio_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = serialio_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index f9deb7d..2858dc9 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -70,20 +70,8 @@ .write_byte = lsmbus_write_byte, }; -static void smbus_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations smbus_pci_ops = { - .set_subsystem = smbus_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static void smbus_read_resources(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index e2486cf..1a4c929 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -173,13 +173,8 @@ /* Enable writes to protected registers. */ pci_write_config8(dev, 0x80, access_cntl | 1); - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); /* Restore protection. */ pci_write_config8(dev, 0x80, access_cntl); diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 28e6521..26634ab 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -361,20 +361,8 @@ } } -static void usb_xhci_set_subsystem(device_t dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations lops_pci = { - .set_subsystem = &usb_xhci_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations usb_xhci_ops = { diff --git a/src/southbridge/nvidia/mcp55/azalia.c b/src/southbridge/nvidia/mcp55/azalia.c index cc2c729..cf40219 100644 --- a/src/southbridge/nvidia/mcp55/azalia.c +++ b/src/southbridge/nvidia/mcp55/azalia.c @@ -254,20 +254,8 @@ #endif } -static void azalia_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations azalia_pci_ops = { - .set_subsystem = azalia_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations azalia_ops = { -- To view, visit https://review.coreboot.org/29195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I90c1ee9ddf8341291ccb82c1f699410c6e9fc104 Gerrit-Change-Number: 29195 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com>

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Change in coreboot[master]: drivers/spi: Winbond specific write-protection enable
by Philipp Deppenwiese (Code Review) 19 Oct '18

19 Oct '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/25105 ) Change subject: drivers/spi: Winbond specific write-protection enable ...................................................................... Patch Set 31: Code-Review+2 -- To view, visit https://review.coreboot.org/25105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie3765b013855538eca37bc7800d3f9d5d09b8402 Gerrit-Change-Number: 25105 Gerrit-PatchSet: 31 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph (1001864) Gerrit-Comment-Date: Fri, 19 Oct 2018 13:46:29 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit October 2018