coreboot-gerrit October 2018

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Change in coreboot[master]: src: Remove unneeded include <cbmem.h>
by Elyes HAOUAS (Code Review) 27 Oct '18

27 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29302 to look at the new patch set (#2). Change subject: src: Remove unneeded include <cbmem.h> ...................................................................... src: Remove unneeded include <cbmem.h> Change-Id: I89e03b6def5c78415bf73baba55941953a70d8de Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/armv7/mmu.c M src/arch/arm64/arm_tf.c M src/arch/arm64/boot.c M src/cpu/allwinner/a10/cpu.c M src/cpu/amd/car/post_cache_as_ram.c M src/drivers/amd/agesa/state_machine.c M src/drivers/intel/fsp1_1/hob.c M src/drivers/intel/fsp1_1/ramstage.c M src/drivers/intel/fsp1_1/stack.c M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/emulation/qemu-i440fx/romstage.c M src/mainboard/emulation/qemu-q35/romstage.c M src/mainboard/google/slippy/acpi_tables.c M src/mainboard/via/epia-m850/romstage.c M src/northbridge/amd/agesa/family12/northbridge.c M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/fsp_rangeley/northbridge.c M src/northbridge/intel/fsp_sandybridge/northbridge.c M src/northbridge/intel/fsp_sandybridge/raminit.c M src/northbridge/intel/gm45/acpi.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i440bx/northbridge.c M src/northbridge/intel/i945/acpi.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/x4x/acpi.c M src/northbridge/intel/x4x/early_init.c M src/northbridge/via/vx900/early_vx900.h M src/northbridge/via/vx900/northbridge.c M src/security/vboot/vboot_loader.c M src/soc/amd/common/block/s3/s3_resume.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/broadwell/systemagent.c M src/soc/intel/cannonlake/romstage/power_state.c M src/soc/intel/denverton_ns/chip.c M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/fsp_baytrail/southcluster.c M src/soc/intel/icelake/romstage/power_state.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/nvidia/tegra124/display.c M src/soc/nvidia/tegra124/sor.c M src/soc/nvidia/tegra210/soc.c M src/soc/nvidia/tegra210/sor.c M src/soc/rockchip/rk3288/soc.c M src/soc/samsung/exynos5250/cpu.c M src/soc/samsung/exynos5420/cpu.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/hudson.c M src/southbridge/amd/cimx/sb800/cfg.c M src/southbridge/amd/cimx/sb800/lpc.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/amd/sb700/lpc.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/madt.c 65 files changed, 3 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/29302/2 -- To view, visit https://review.coreboot.org/29302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I89e03b6def5c78415bf73baba55941953a70d8de Gerrit-Change-Number: 29302 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: src: Remove unneeded include <cbmem.h>
by Elyes HAOUAS (Code Review) 27 Oct '18

27 Oct '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29302 Change subject: src: Remove unneeded include <cbmem.h> ...................................................................... src: Remove unneeded include <cbmem.h> Change-Id: I89e03b6def5c78415bf73baba55941953a70d8de Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/armv7/mmu.c M src/arch/arm64/arm_tf.c M src/arch/arm64/boot.c M src/cpu/allwinner/a10/cpu.c M src/cpu/amd/car/post_cache_as_ram.c M src/drivers/amd/agesa/state_machine.c M src/drivers/intel/fsp1_1/hob.c M src/drivers/intel/fsp1_1/ramstage.c M src/drivers/intel/fsp1_1/stack.c M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/google/slippy/acpi_tables.c M src/northbridge/amd/agesa/family12/northbridge.c M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/fsp_rangeley/northbridge.c M src/northbridge/intel/fsp_sandybridge/northbridge.c M src/northbridge/intel/fsp_sandybridge/raminit.c M src/northbridge/intel/gm45/acpi.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i440bx/northbridge.c M src/northbridge/intel/i945/acpi.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/x4x/acpi.c M src/northbridge/intel/x4x/early_init.c M src/northbridge/via/vx900/early_vx900.h M src/northbridge/via/vx900/northbridge.c M src/security/vboot/vboot_loader.c M src/soc/amd/common/block/s3/s3_resume.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/broadwell/systemagent.c M src/soc/intel/cannonlake/romstage/power_state.c M src/soc/intel/denverton_ns/chip.c M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/fsp_baytrail/southcluster.c M src/soc/intel/icelake/romstage/power_state.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/nvidia/tegra124/display.c M src/soc/nvidia/tegra124/sor.c M src/soc/nvidia/tegra210/soc.c M src/soc/nvidia/tegra210/sor.c M src/soc/rockchip/rk3288/soc.c M src/soc/samsung/exynos5250/cpu.c M src/soc/samsung/exynos5420/cpu.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/hudson.c M src/southbridge/amd/cimx/sb800/cfg.c M src/southbridge/amd/cimx/sb800/lpc.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/amd/sb700/lpc.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/madt.c 62 files changed, 0 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/29302/1 diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index 935f778..b63497c 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -33,7 +33,6 @@ #include <stdint.h> #include <symbols.h> -#include <cbmem.h> #include <console/console.h> #include <arch/cache.h> diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/arm_tf.c index 384b1b7..eaf8739 100644 --- a/src/arch/arm64/arm_tf.c +++ b/src/arch/arm64/arm_tf.c @@ -20,7 +20,6 @@ #include <arm_tf.h> #include <assert.h> #include <cbfs.h> -#include <cbmem.h> #include <program_loading.h> /* diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index d8a4630..cd98b03 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -18,7 +18,6 @@ #include <arch/stages.h> #include <arch/transition.h> #include <arm_tf.h> -#include <cbmem.h> #include <console/console.h> #include <program_loading.h> #include <rules.h> diff --git a/src/cpu/allwinner/a10/cpu.c b/src/cpu/allwinner/a10/cpu.c index 60b93be..eac8da6 100644 --- a/src/cpu/allwinner/a10/cpu.c +++ b/src/cpu/allwinner/a10/cpu.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <device/device.h> #include <cpu/cpu.h> -#include <cbmem.h> #include <symbols.h> diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index adf959c..e55ef40 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -26,7 +26,6 @@ #include <cpu/amd/msr.h> #include <arch/acpi.h> #include <romstage_handoff.h> -#include <cbmem.h> #include "cpu/amd/car/disable_cache_as_ram.c" diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index e1fdd42..b9cb090 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -20,7 +20,6 @@ #include <arch/acpi.h> #include <bootstate.h> #include <cbfs.h> -#include <cbmem.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h> diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c index 85d0f35..032d275 100644 --- a/src/drivers/intel/fsp1_1/hob.c +++ b/src/drivers/intel/fsp1_1/hob.c @@ -17,7 +17,6 @@ #include <arch/early_variables.h> #include <arch/hlt.h> #include <bootstate.h> -#include <cbmem.h> #include <console/console.h> #include <fsp/util.h> #include <ip_checksum.h> diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 2b857ab..312ef1e 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -16,7 +16,6 @@ #include <bootmode.h> #include <arch/acpi.h> -#include <cbmem.h> #include <cbfs.h> #include <console/console.h> #include <fsp/memmap.h> diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c index e4b30dd..bbbd599 100644 --- a/src/drivers/intel/fsp1_1/stack.c +++ b/src/drivers/intel/fsp1_1/stack.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <cbmem.h> #include <console/console.h> #include <cpu/x86/mtrr.h> #include <fsp/memmap.h> diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index aa309de..ee02726 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -23,7 +23,6 @@ #include <string.h> #include <delay.h> #include <smbios.h> -#include <cbmem.h> #include "fw_cfg.h" #include "fw_cfg_if.h" diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index 4036f1b..63ff7bc 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -15,7 +15,6 @@ #include <types.h> #include <string.h> -#include <cbmem.h> #include <console/console.h> #include <arch/acpi.h> #include <arch/ioapic.h> diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 1851118..ff011e3 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -26,7 +26,6 @@ #include <string.h> #include <lib.h> #include <cpu/cpu.h> -#include <cbmem.h> #include <cpu/x86/lapic.h> #include <cpu/amd/msr.h> diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 0a56d18..b843c79 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -26,7 +26,6 @@ #include <string.h> #include <lib.h> #include <cpu/cpu.h> -#include <cbmem.h> #include <cpu/x86/lapic.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 7248eb7..0361a77 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -27,7 +27,6 @@ #include <string.h> #include <lib.h> #include <cpu/cpu.h> -#include <cbmem.h> #include <AGESA.h> #include <cpu/x86/lapic.h> #include <cpu/amd/msr.h> diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index a42ee5c..b3b0ba1 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -26,7 +26,6 @@ #include <string.h> #include <lib.h> #include <cpu/cpu.h> -#include <cbmem.h> #include <cpu/x86/lapic.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index f6cb285..f42bba1 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -25,7 +25,6 @@ #include <string.h> #include <lib.h> #include <cpu/cpu.h> -#include <cbmem.h> #include <Porting.h> #include <AGESA.h> #include <FieldAccessors.h> diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index fb3610d..8488ba0 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -25,7 +25,6 @@ #include <string.h> #include <lib.h> #include <cpu/cpu.h> -#include <cbmem.h> #include <Porting.h> #include <AGESA.h> #include <FieldAccessors.h> diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 7125e1e..f4cb9a0 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -27,7 +27,6 @@ #include <string.h> #include <lib.h> #include <cpu/cpu.h> -#include <cbmem.h> #include <Porting.h> #include <AGESA.h> #include <FieldAccessors.h> diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index a5dc6cd..b4752c4 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -20,7 +20,6 @@ #include <stdlib.h> #include <string.h> #include "e7505.h" -#include <cbmem.h> #include <arch/acpi.h> unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 5dcc1fa..215464c 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -38,7 +38,6 @@ #include <assert.h> #include <spd.h> #include <sdram_mode.h> -#include <cbmem.h> #include "raminit.h" #include "e7505.h" diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 94855cf..93d9c63 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -27,7 +27,6 @@ #include <stdlib.h> #include <string.h> #include <cpu/cpu.h> -#include <cbmem.h> #include "chip.h" #include "northbridge.h" #include <drivers/intel/fsp1_0/fsp_util.h> diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index 111c201..c468e25 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -27,7 +27,6 @@ #include <stdlib.h> #include <string.h> #include <cpu/cpu.h> -#include <cbmem.h> #include "chip.h" #include "northbridge.h" #include <fsp_util.h> diff --git a/src/northbridge/intel/fsp_sandybridge/raminit.c b/src/northbridge/intel/fsp_sandybridge/raminit.c index f67d405..a9648ed 100644 --- a/src/northbridge/intel/fsp_sandybridge/raminit.c +++ b/src/northbridge/intel/fsp_sandybridge/raminit.c @@ -16,7 +16,6 @@ #include <console/console.h> #include <string.h> #include <arch/io.h> -#include <cbmem.h> #include <device/pci_def.h> #include "raminit.h" #include "northbridge.h" diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index d208eed..3df37e8 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -22,7 +22,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <cbmem.h> #include <arch/acpigen.h> #include <cpu/cpu.h> #include "gm45.h" diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 0453246..53583f8 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -28,7 +28,6 @@ #include <cpu/cpu.h> #include <cpu/x86/smm.h> #include <boot/tables.h> -#include <cbmem.h> #include "chip.h" #include "haswell.h" diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index affd8a1..b8aa4a4 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -19,7 +19,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <cbmem.h> #include <cpu/cpu.h> #include <pc80/keyboard.h> #include "northbridge.h" diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index 990d3de..d2a426f 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -22,7 +22,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <cbmem.h> #include <arch/acpigen.h> #include <cpu/cpu.h> #include "i945.h" diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index c259530..ad4c6ed 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -27,7 +27,6 @@ #include "raminit.h" #include "i945.h" #include "chip.h" -#include <cbmem.h> #include <device/dram/ddr2.h> /* Debugging macros. */ diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 4c6cdd4..00f6913 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -28,7 +28,6 @@ #include <stdlib.h> #include <string.h> #include <cpu/cpu.h> -#include <cbmem.h> #include "chip.h" #include "nehalem.h" #include <cpu/intel/smm/gen1/smi.h> diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 7b4b3be..f8ecc1a 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -21,7 +21,6 @@ #include <arch/acpi.h> #include <device/pci_def.h> #include <elog.h> -#include <cbmem.h> #include <pc80/mc146818rtc.h> #include <romstage_handoff.h> #include "sandybridge.h" diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index cb0e5db..5ec8292 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -27,7 +27,6 @@ #include <stdlib.h> #include <string.h> #include <cpu/cpu.h> -#include <cbmem.h> #include "chip.h" #include "sandybridge.h" #include <cpu/intel/smm/gen1/smi.h> diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c index 678486c..182e092 100644 --- a/src/northbridge/intel/x4x/acpi.c +++ b/src/northbridge/intel/x4x/acpi.c @@ -23,7 +23,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <cbmem.h> #include <arch/acpigen.h> #include <cpu/cpu.h> #include "x4x.h" diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index d410259..c6eb383 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -24,7 +24,6 @@ #endif #include <pc80/mc146818rtc.h> #include "x4x.h" -#include <cbmem.h> #include <console/console.h> #include <halt.h> #include <romstage_handoff.h> diff --git a/src/northbridge/via/vx900/early_vx900.h b/src/northbridge/via/vx900/early_vx900.h index 11c561a..2caa763 100644 --- a/src/northbridge/via/vx900/early_vx900.h +++ b/src/northbridge/via/vx900/early_vx900.h @@ -21,7 +21,6 @@ #include "vx900.h" #include <arch/io.h> -#include <cbmem.h> #include <stdint.h> #include <arch/io.h> diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index a699d86..3315524 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -22,7 +22,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/cpu.h> -#include <cbmem.h> #include <cf9_reset.h> #include <lib.h> #include <reset.h> diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 17ea0a9..57a3b49 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -15,7 +15,6 @@ #include <arch/early_variables.h> #include <cbfs.h> -#include <cbmem.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> #include <rmodule.h> diff --git a/src/soc/amd/common/block/s3/s3_resume.c b/src/soc/amd/common/block/s3/s3_resume.c index 1ba9468..04414e8 100644 --- a/src/soc/amd/common/block/s3/s3_resume.c +++ b/src/soc/amd/common/block/s3/s3_resume.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <cbmem.h> #include <stage_cache.h> #include <mrc_cache.h> #include <console/console.h> diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index ca87d63..e079aad 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -19,7 +19,6 @@ #include <arch/acpi.h> #include <arch/acpigen.h> #include <bootstate.h> -#include <cbmem.h> #include "chip.h" #include <console/console.h> #include <cpu/x86/smm.h> diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 3abc853..49edd03 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -22,7 +22,6 @@ #include <bootmode.h> #include <console/console.h> #include <cbfs.h> -#include <cbmem.h> #include <cpu/x86/mtrr.h> #include <elog.h> #include <program_loading.h> diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index afb6038..7147750 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <cbmem.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/cpu.h> #include <soc/iomap.h> diff --git a/src/soc/intel/cannonlake/romstage/power_state.c b/src/soc/intel/cannonlake/romstage/power_state.c index 838a056..72361ff 100644 --- a/src/soc/intel/cannonlake/romstage/power_state.c +++ b/src/soc/intel/cannonlake/romstage/power_state.c @@ -16,7 +16,6 @@ #include <arch/early_variables.h> #include <arch/io.h> -#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <intelblocks/pmclib.h> diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index 05dcb76..0cf8d8c 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -18,7 +18,6 @@ #include <arch/acpi.h> #include <bootstate.h> #include <cbfs.h> -#include <cbmem.h> #include <console/console.h> #include <cpu/cpu.h> #include <device/device.h> diff --git a/src/soc/intel/denverton_ns/systemagent.c b/src/soc/intel/denverton_ns/systemagent.c index 6b72a0c..3df7f87 100644 --- a/src/soc/intel/denverton_ns/systemagent.c +++ b/src/soc/intel/denverton_ns/systemagent.c @@ -25,7 +25,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <cbmem.h> #include <romstage_handoff.h> #include <delay.h> #include <timer.h> diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 6fa2192..7bde8d9 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> #include <arch/ioapic.h> -#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/soc/intel/icelake/romstage/power_state.c b/src/soc/intel/icelake/romstage/power_state.c index 3b6d5f2..17ed36a 100644 --- a/src/soc/intel/icelake/romstage/power_state.c +++ b/src/soc/intel/icelake/romstage/power_state.c @@ -15,7 +15,6 @@ #include <arch/early_variables.h> #include <arch/io.h> -#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <intelblocks/pmclib.h> diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 215b07c..cf9192e 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -20,7 +20,6 @@ #include <arch/stages.h> #include <arch/early_variables.h> #include <assert.h> -#include <cbmem.h> #include <chip.h> #include <console/console.h> #include <cpu/x86/mtrr.h> diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index c90e392..6150dbd 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -15,7 +15,6 @@ #include <arch/io.h> #include <boot/tables.h> -#include <cbmem.h> #include <console/console.h> #include <cpu/cpu.h> #include <delay.h> diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c index d9137ad..f031741 100644 --- a/src/soc/nvidia/tegra124/sor.c +++ b/src/soc/nvidia/tegra124/sor.c @@ -18,7 +18,6 @@ #include <arch/io.h> #include <boot/tables.h> -#include <cbmem.h> #include <console/console.h> #include <cpu/cpu.h> #include <delay.h> diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index a8f111b..a7c3550 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -19,7 +19,6 @@ #include <cpu/cpu.h> #include <bootmode.h> #include <bootstate.h> -#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <soc/nvidia/tegra/dc.h> diff --git a/src/soc/nvidia/tegra210/sor.c b/src/soc/nvidia/tegra210/sor.c index a00bdad..7b6134c 100644 --- a/src/soc/nvidia/tegra210/sor.c +++ b/src/soc/nvidia/tegra210/sor.c @@ -28,7 +28,6 @@ #include <string.h> #include <cpu/cpu.h> #include <boot/tables.h> -#include <cbmem.h> #include <soc/nvidia/tegra/dc.h> #include <soc/nvidia/tegra/types.h> #include <soc/sor.h> diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index eadbfc8..c0a2ed0 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -15,7 +15,6 @@ #include <arch/cache.h> #include <bootmode.h> -#include <cbmem.h> #include <console/console.h> #include <delay.h> #include <device/device.h> diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index 2196144..aed1114 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -15,7 +15,6 @@ */ #include <arch/cache.h> -#include <cbmem.h> #include <console/console.h> #include <delay.h> #include <device/device.h> diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index cab23a6..ecda54b 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -15,7 +15,6 @@ */ #include <arch/cache.h> -#include <cbmem.h> #include <console/console.h> #include <delay.h> #include <device/device.h> diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 75da9dd..da214a1 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <reset.h> #include <arch/cpu.h> -#include <cbmem.h> #include "hudson.h" void hudson_pci_port80(void) diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index 4fc473b..5d32a83 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <cbmem.h> #include "hudson.h" #include "imc.h" #include "smbus.h" diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 9f8b3ab..7956961 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -17,7 +17,6 @@ #include "SBPLATFORM.h" #include "cfg.h" #include "OEM.h" -#include <cbmem.h> #include <arch/io.h> #include <arch/acpi.h> diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index 40c0739..2759af6 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -20,7 +20,6 @@ #include <arch/ioapic.h> #include "lpc.h" #include <arch/io.h> -#include <cbmem.h> void lpc_read_resources(struct device *dev) { diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 47d20af..99cad96 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -23,7 +23,6 @@ #include <console/console.h> #include <reset.h> #include <arch/cpu.h> -#include <cbmem.h> #include "hudson.h" #include "pci_devs.h" #include <Fch/Fch.h> diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index ecf041a..bf9cad0 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <cbmem.h> #include "hudson.h" #include "smbus.h" #include "smi.h" diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 6569e39..857503a 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -28,7 +28,6 @@ #include <pc80/isa-dma.h> #include <arch/io.h> #include <arch/ioapic.h> -#include <cbmem.h> #include <cpu/amd/powernow.h> #include "sb700.h" diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 1254a16..dbead5b 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -15,7 +15,6 @@ #include <string.h> #include <arch/io.h> -#include <cbmem.h> #include <arch/cbfs.h> #include <cbfs.h> #include <ip_checksum.h> diff --git a/src/southbridge/intel/bd82x6x/madt.c b/src/southbridge/intel/bd82x6x/madt.c index afa15ae..e0026f5 100644 --- a/src/southbridge/intel/bd82x6x/madt.c +++ b/src/southbridge/intel/bd82x6x/madt.c @@ -15,7 +15,6 @@ #include <types.h> #include <string.h> -#include <cbmem.h> #include <console/console.h> #include <arch/acpi.h> #include <arch/ioapic.h> -- To view, visit https://review.coreboot.org/29302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I89e03b6def5c78415bf73baba55941953a70d8de Gerrit-Change-Number: 29302 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

1 0

Change in coreboot[master]: src: Remove unneeded include <reset.h>
by Elyes HAOUAS (Code Review) 27 Oct '18

27 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29301 to look at the new patch set (#3). Change subject: src: Remove unneeded include <reset.h> ...................................................................... src: Remove unneeded include <reset.h> Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/cf9_reset.c M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/cpu/amd/family_10h-family_15h/init_cpus.h M src/cpu/intel/fsp_model_406dx/bootblock.c M src/drivers/intel/fsp2_0/stage_cache.c M src/ec/google/chromeec/ec.c M src/lib/hardwaremain.c M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/google/foster/pmic.c M src/mainboard/google/smaug/pmic.c M src/mainboard/google/veyron/bootblock.c M src/mainboard/google/veyron_mickey/bootblock.c M src/mainboard/google/veyron_rialto/bootblock.c M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/intel/stargo2/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c M src/security/tpm/tspi/tspi.c M src/security/vboot/common.c M src/soc/cavium/common/bdk-coreboot.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/fsp_baytrail/bootblock/bootblock.c M src/soc/intel/skylake/romstage/romstage.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/sb700/early_setup.c 39 files changed, 19 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/29301/3 -- To view, visit https://review.coreboot.org/29301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 Gerrit-Change-Number: 29301 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: src: Remove unneeded include <reset.h>
by Elyes HAOUAS (Code Review) 27 Oct '18

27 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29301 to look at the new patch set (#2). Change subject: src: Remove unneeded include <reset.h> ...................................................................... src: Remove unneeded include <reset.h> Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/cf9_reset.c M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/cpu/amd/family_10h-family_15h/init_cpus.h M src/cpu/intel/fsp_model_406dx/bootblock.c M src/drivers/intel/fsp2_0/stage_cache.c M src/ec/google/chromeec/ec.c M src/lib/hardwaremain.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/google/foster/pmic.c M src/mainboard/google/smaug/pmic.c M src/mainboard/google/veyron/bootblock.c M src/mainboard/google/veyron_mickey/bootblock.c M src/mainboard/google/veyron_rialto/bootblock.c M src/mainboard/intel/stargo2/romstage.c M src/security/tpm/tspi/tspi.c M src/security/vboot/common.c M src/soc/cavium/common/bdk-coreboot.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/fsp_baytrail/bootblock/bootblock.c M src/soc/intel/skylake/romstage/romstage.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/sb700/early_setup.c 27 files changed, 7 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/29301/2 -- To view, visit https://review.coreboot.org/29301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 Gerrit-Change-Number: 29301 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: src: Remove unneeded include <reset.h>
by Elyes HAOUAS (Code Review) 27 Oct '18

27 Oct '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29301 Change subject: src: Remove unneeded include <reset.h> ...................................................................... src: Remove unneeded include <reset.h> Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/cf9_reset.c M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/cpu/amd/family_10h-family_15h/init_cpus.h M src/cpu/intel/fsp_model_406dx/bootblock.c M src/drivers/intel/fsp2_0/stage_cache.c M src/ec/google/chromeec/ec.c M src/lib/hardwaremain.c M src/mainboard/google/foster/pmic.c M src/mainboard/google/smaug/pmic.c M src/mainboard/google/veyron/bootblock.c M src/mainboard/google/veyron_mickey/bootblock.c M src/mainboard/google/veyron_rialto/bootblock.c M src/mainboard/intel/stargo2/romstage.c M src/security/tpm/tspi/tspi.c M src/security/vboot/common.c M src/soc/cavium/common/bdk-coreboot.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/fsp_baytrail/bootblock/bootblock.c M src/soc/intel/skylake/romstage/romstage.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/sb700/early_setup.c 23 files changed, 3 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/29301/1 diff --git a/src/arch/x86/cf9_reset.c b/src/arch/x86/cf9_reset.c index c28e448..d1e5704 100644 --- a/src/arch/x86/cf9_reset.c +++ b/src/arch/x86/cf9_reset.c @@ -18,7 +18,6 @@ #include <cf9_reset.h> #include <console/console.h> #include <halt.h> -#include <reset.h> /* * A system reset in terms of the CF9 register asserts the INIT# diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 1247e60..7f441c0 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -15,6 +15,7 @@ */ #include <cpu/amd/msr.h> +#include <reset.h> #include "init_cpus.h" #if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.h b/src/cpu/amd/family_10h-family_15h/init_cpus.h index d4bff0b..ddae9a6 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.h +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.h @@ -23,7 +23,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/msr.h> #include <cpu/amd/multicore.h> -#include <reset.h> #include <northbridge/amd/amdfam10/raminit.h> #include "defaults.h" diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c index 327c4a4..e7b017f 100644 --- a/src/cpu/intel/fsp_model_406dx/bootblock.c +++ b/src/cpu/intel/fsp_model_406dx/bootblock.c @@ -21,7 +21,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <arch/io.h> -#include <reset.h> #include <southbridge/intel/fsp_rangeley/soc.h> #include "model_406dx.h" diff --git a/src/drivers/intel/fsp2_0/stage_cache.c b/src/drivers/intel/fsp2_0/stage_cache.c index 434eae9..a9ec154 100644 --- a/src/drivers/intel/fsp2_0/stage_cache.c +++ b/src/drivers/intel/fsp2_0/stage_cache.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <fsp/memmap.h> #include <stage_cache.h> -#include <reset.h> #include <program_loading.h> void stage_cache_external_region(void **base, size_t *size) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 75d9da1..6efe139 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -25,7 +25,6 @@ #include <delay.h> #include <elog.h> #include <halt.h> -#include <reset.h> #include <rtc.h> #include <stdlib.h> #include <security/vboot/vboot_common.h> diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index a26d678..05164b0 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -29,7 +29,6 @@ #include <device/pci.h> #include <delay.h> #include <stdlib.h> -#include <reset.h> #include <boot/tables.h> #include <program_loading.h> #include <lib.h> diff --git a/src/mainboard/google/foster/pmic.c b/src/mainboard/google/foster/pmic.c index 8d4f855..d8b1fa0 100644 --- a/src/mainboard/google/foster/pmic.c +++ b/src/mainboard/google/foster/pmic.c @@ -20,6 +20,7 @@ #include <device/i2c_simple.h> #include <stdint.h> #include <stdlib.h> +#include <reset.h> #include "pmic.h" #include "reset.h" diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c index 75075ad..a6e4574 100644 --- a/src/mainboard/google/smaug/pmic.c +++ b/src/mainboard/google/smaug/pmic.c @@ -20,6 +20,7 @@ #include <device/i2c_simple.h> #include <stdint.h> #include <stdlib.h> +#include <reset.h> #include "pmic.h" #include "reset.h" diff --git a/src/mainboard/google/veyron/bootblock.c b/src/mainboard/google/veyron/bootblock.c index 1f4eec20..a36d9b0 100644 --- a/src/mainboard/google/veyron/bootblock.c +++ b/src/mainboard/google/veyron/bootblock.c @@ -19,7 +19,6 @@ #include <bootblock_common.h> #include <console/console.h> #include <delay.h> -#include <reset.h> #include <soc/clock.h> #include <soc/i2c.h> #include <soc/grf.h> diff --git a/src/mainboard/google/veyron_mickey/bootblock.c b/src/mainboard/google/veyron_mickey/bootblock.c index b95a265..73fd544 100644 --- a/src/mainboard/google/veyron_mickey/bootblock.c +++ b/src/mainboard/google/veyron_mickey/bootblock.c @@ -19,7 +19,6 @@ #include <bootblock_common.h> #include <console/console.h> #include <delay.h> -#include <reset.h> #include <soc/clock.h> #include <soc/i2c.h> #include <soc/grf.h> diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c index dae046b..474f6ec 100644 --- a/src/mainboard/google/veyron_rialto/bootblock.c +++ b/src/mainboard/google/veyron_rialto/bootblock.c @@ -19,7 +19,6 @@ #include <bootblock_common.h> #include <console/console.h> #include <delay.h> -#include <reset.h> #include <soc/clock.h> #include <soc/i2c.h> #include <soc/grf.h> diff --git a/src/mainboard/intel/stargo2/romstage.c b/src/mainboard/intel/stargo2/romstage.c index cdf087a..f5b84fd 100644 --- a/src/mainboard/intel/stargo2/romstage.c +++ b/src/mainboard/intel/stargo2/romstage.c @@ -25,7 +25,6 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <halt.h> -#include <reset.h> #include <fsp_util.h> #include <northbridge/intel/fsp_sandybridge/northbridge.h> #include <northbridge/intel/fsp_sandybridge/raminit.h> diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index d9cade9..33eaa06 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -16,7 +16,6 @@ #include <console/cbmem_console.h> #include <console/console.h> -#include <reset.h> #include <security/tpm/tspi.h> #include <security/tpm/tss.h> #include <stdlib.h> diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index 72228e4..a909312 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -17,7 +17,6 @@ #include <cbfs.h> #include <cbmem.h> #include <console/console.h> -#include <reset.h> #include <string.h> #include <vb2_api.h> #include <security/vboot/misc.h> diff --git a/src/soc/cavium/common/bdk-coreboot.c b/src/soc/cavium/common/bdk-coreboot.c index ff30edf..b322a0c 100644 --- a/src/soc/cavium/common/bdk-coreboot.c +++ b/src/soc/cavium/common/bdk-coreboot.c @@ -23,7 +23,6 @@ #include <endian.h> #include <arch/io.h> #include <delay.h> -#include <reset.h> #include <soc/timer.h> // BDK diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index f485dfd..17d4074 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -32,7 +32,6 @@ #include <romstage_handoff.h> #include <string.h> #include <timestamp.h> -#include <reset.h> #include <vendorcode/google/chromeos/chromeos.h> #include <fsp/util.h> #include <soc/gpio.h> diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index ebbdabd..8496536 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -24,7 +24,6 @@ #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> #include <lib.h> -#include <reset.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/pm.h> diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c index 8ce0a1d..81f5dfb 100644 --- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c +++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c @@ -25,7 +25,6 @@ #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/gpio.h> -#include <reset.h> /* * check for a warm reset and do a hard reset instead. diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 215b07c..99a8957 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -30,7 +30,6 @@ #include <elog.h> #include <intelblocks/fast_spi.h> #include <intelblocks/pmclib.h> -#include <reset.h> #include <romstage_handoff.h> #include <soc/pci_devs.h> #include <soc/pei_wrapper.h> diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 75da9dd..cfd6d0e 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -20,7 +20,6 @@ #include <arch/io.h> #include <arch/acpi.h> #include <console/console.h> -#include <reset.h> #include <arch/cpu.h> #include <cbmem.h> #include "hudson.h" diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 47d20af..cd1ff85 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -21,7 +21,6 @@ #include <arch/io.h> #include <arch/acpi.h> #include <console/console.h> -#include <reset.h> #include <arch/cpu.h> #include <cbmem.h> #include "hudson.h" diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index a656921..011a056 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -24,7 +24,6 @@ #include <console/console.h> #include <cpu/x86/msr.h> -#include <reset.h> #include "sb700.h" #include "smbus.h" -- To view, visit https://review.coreboot.org/29301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 Gerrit-Change-Number: 29301 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

1 0

Change in coreboot[master]: src: Remove unneeded include "{arch, cpu}/cpu.h"
by Elyes HAOUAS (Code Review) 27 Oct '18

27 Oct '18

Hello build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29300 to look at the new patch set (#7). Change subject: src: Remove unneeded include "{arch,cpu}/cpu.h" ...................................................................... src: Remove unneeded include "{arch,cpu}/cpu.h" Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/acpi_s3.c M src/arch/x86/mpspec.c M src/arch/x86/tables.c M src/cpu/allwinner/a10/cpu.c M src/cpu/amd/car/disable_cache_as_ram.c M src/cpu/amd/family_10h-family_15h/init_cpus.h M src/cpu/amd/family_10h-family_15h/processor_name.c M src/cpu/amd/family_10h-family_15h/ram_calc.c M src/cpu/amd/quadcore/amd_sibling.c M src/cpu/amd/quadcore/quadcore.c M src/cpu/amd/smm/smm_init.c M src/cpu/intel/car/romstage.c M src/cpu/intel/fsp_model_206ax/finalize.c M src/cpu/intel/fsp_model_406dx/bootblock.c M src/cpu/intel/haswell/bootblock.c M src/cpu/intel/haswell/finalize.c M src/cpu/intel/haswell/romstage.c M src/cpu/intel/haswell/smmrelocate.c M src/cpu/intel/hyperthreading/intel_sibling.c M src/cpu/intel/microcode/microcode.c M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_206ax/finalize.c M src/cpu/intel/slot_1/l2_cache.c M src/cpu/intel/smm/gen1/smmrelocate.c M src/cpu/via/nano/update_ucode.c M src/cpu/x86/mtrr/mtrr.c M src/cpu/x86/name/name.c M src/cpu/x86/pae/pgtbl.c M src/drivers/amd/agesa/state_machine.c M src/drivers/gic/gic.c M src/drivers/i2c/w83793/w83793.c M src/drivers/intel/fsp1_1/stack.c M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/notify.c M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/fsp2_0/upd_display.c M src/include/cpu/amd/model_10xxx_rev.h M src/include/cpu/x86/cr.h M src/lib/selfboot.c M src/mainboard/adi/rcc-dff/romstage.c M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/bettong/mptable.c M src/mainboard/amd/bettong/romstage.c M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/amd/db-ft3b-lc/mptable.c M src/mainboard/amd/gardenia/mptable.c M src/mainboard/amd/lamar/mptable.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/olivehill/mptable.c M src/mainboard/amd/olivehillplus/mptable.c M src/mainboard/amd/parmer/mptable.c M src/mainboard/amd/parmer/romstage.c M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c M src/mainboard/amd/thatcher/mptable.c M src/mainboard/amd/thatcher/romstage.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/aopen/dxplplusu/romstage.c M src/mainboard/asrock/imb-a180/mptable.c M src/mainboard/asus/am1i-a/mptable.c M src/mainboard/asus/f2a85-m/mptable.c M src/mainboard/asus/kcma-d8/resourcemap.c M src/mainboard/asus/kcma-d8/romstage.c M src/mainboard/asus/kfsn4-dre/romstage.c M src/mainboard/asus/kgpe-d16/resourcemap.c M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/bap/ode_e20XX/mptable.c M src/mainboard/bap/ode_e21XX/mptable.c M src/mainboard/biostar/a68n_5200/mptable.c M src/mainboard/biostar/am1ml/mptable.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/gizmosphere/gizmo2/mptable.c M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/kahlee/mptable.c M src/mainboard/google/link/romstage.c M src/mainboard/google/nyan/romstage.c M src/mainboard/google/nyan_big/romstage.c M src/mainboard/google/nyan_blaze/romstage.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/stout/romstage.c M src/mainboard/hp/abm/mptable.c M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/hp/pavilion_m6_1035dx/mptable.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/intel/bayleybay_fsp/romstage.c M src/mainboard/intel/cougar_canyon2/romstage.c M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/intel/harcuvar/acpi_tables.c M src/mainboard/intel/littleplains/romstage.c M src/mainboard/intel/mohonpeak/romstage.c M src/mainboard/intel/stargo2/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/kontron/ktqm77/romstage.c M src/mainboard/lenovo/g505s/mptable.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/lenovo/x220/romstage.c M src/mainboard/lenovo/x230/romstage.c M src/mainboard/msi/ms7721/mptable.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/romstage.c M src/mainboard/scaleway/tagada/acpi_tables.c M src/mainboard/siemens/mc_tcu3/romstage.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c M src/northbridge/amd/amdfam10/raminit_amdmct.c M src/northbridge/amd/amdht/h3finit.c M src/northbridge/amd/amdht/h3ncmn.c M src/northbridge/amd/amdht/ht_wrapper.c M src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c M src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c M src/northbridge/amd/amdmct/mct_ddr3/mctrci.c M src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c M src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c M src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c M src/northbridge/amd/amdmct/mct_ddr3/mctwl.c M src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c M src/northbridge/amd/amdmct/wrappers/mcti_d.c M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/fsp_rangeley/northbridge.c M src/northbridge/intel/fsp_sandybridge/northbridge.c M src/northbridge/intel/gm45/acpi.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i945/acpi.c M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/nehalem/raminit.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/x4x/acpi.c M src/northbridge/intel/x4x/raminit.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/mca.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/smi.c M src/soc/cavium/cn81xx/soc.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/car.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/include/soc/romstage.h M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/placeholders.c M src/soc/intel/baytrail/smm.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/include/soc/romstage.h M src/soc/intel/braswell/placeholders.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/braswell/smm.c M src/soc/intel/broadwell/bootblock/cpu.c M src/soc/intel/broadwell/cpu_info.c M src/soc/intel/broadwell/include/soc/cpu.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/broadwell/smi.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/include/soc/cpu.h M src/soc/intel/cannonlake/include/soc/romstage.h M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/util.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/bootblock/bootblock.c M src/soc/intel/denverton_ns/chip.c M src/soc/intel/denverton_ns/include/soc/romstage.h M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/smm.c M src/soc/intel/denverton_ns/tsc_freq.c M src/soc/intel/denverton_ns/upd_display.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/include/soc/romstage.h M src/soc/intel/fsp_baytrail/placeholders.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_baytrail/smm.c M src/soc/intel/fsp_baytrail/southcluster.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/fsp_broadwell_de/include/soc/romstage.h M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/smmrelocate.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/include/soc/cpu.h M src/soc/intel/icelake/include/soc/romstage.h M src/soc/intel/quark/include/soc/cpu.h M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/include/fsp20/soc/romstage.h M src/soc/intel/skylake/include/soc/cpu.h M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/smmrelocate.c M src/soc/mediatek/mt8173/soc.c M src/soc/nvidia/tegra124/display.c M src/soc/nvidia/tegra210/ramstage.c M src/soc/nvidia/tegra210/soc.c M src/soc/nvidia/tegra210/sor.c M src/soc/rockchip/rk3399/soc.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/smi.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/smi.c M src/southbridge/amd/rs780/cmn.c M src/southbridge/amd/sb700/early_setup.c M src/southbridge/amd/sb800/early_setup.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/common/smi.c M src/southbridge/intel/fsp_bd82x6x/lpc.c M src/southbridge/intel/fsp_bd82x6x/smi.c M src/southbridge/intel/fsp_i89xx/lpc.c M src/southbridge/intel/fsp_i89xx/romstage.c M src/southbridge/intel/fsp_i89xx/romstage.h M src/southbridge/intel/fsp_i89xx/smi.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/fsp_rangeley/romstage.h M src/southbridge/intel/i82801dx/smi.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/smi.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/smi.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/smi.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/smi.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smi.c 235 files changed, 77 insertions(+), 196 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/29300/7 -- To view, visit https://review.coreboot.org/29300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Gerrit-Change-Number: 29300 Gerrit-PatchSet: 7 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/lenovo/x1_carbon_gen1/cmos: Port USB Always On
by Patrick Rudolph (Code Review) 27 Oct '18

27 Oct '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/29032 ) Change subject: mb/lenovo/x1_carbon_gen1/cmos: Port USB Always On ...................................................................... Patch Set 3: Code-Review+1 Needs test on x1_carbon -- To view, visit https://review.coreboot.org/29032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib9070b659b0c9ad5dde4200ec2845c6fa2b78b25 Gerrit-Change-Number: 29032 Gerrit-PatchSet: 3 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 27 Oct 2018 13:20:12 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/lenovo/t430: Set USB always on when calling SMI sleep
by Patrick Rudolph (Code Review) 27 Oct '18

27 Oct '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/29031 ) Change subject: mb/lenovo/t430: Set USB always on when calling SMI sleep ...................................................................... Patch Set 2: Code-Review+2 The whole USB always on stuff should be replaced by ACPI methods, but this is out of scope of this patch. -- To view, visit https://review.coreboot.org/29031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic4851022267caca267b667b4e3c327838e0a0b66 Gerrit-Change-Number: 29031 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 27 Oct 2018 13:18:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src: Remove unneeded include "{arch, cpu}/cpu.h"
by Elyes HAOUAS (Code Review) 27 Oct '18

27 Oct '18

Hello build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29300 to look at the new patch set (#6). Change subject: src: Remove unneeded include "{arch,cpu}/cpu.h" ...................................................................... src: Remove unneeded include "{arch,cpu}/cpu.h" Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/acpi_s3.c M src/arch/x86/mpspec.c M src/arch/x86/tables.c M src/cpu/allwinner/a10/cpu.c M src/cpu/amd/car/disable_cache_as_ram.c M src/cpu/amd/family_10h-family_15h/init_cpus.h M src/cpu/amd/family_10h-family_15h/processor_name.c M src/cpu/amd/family_10h-family_15h/ram_calc.c M src/cpu/amd/quadcore/amd_sibling.c M src/cpu/amd/quadcore/quadcore.c M src/cpu/amd/smm/smm_init.c M src/cpu/intel/car/romstage.c M src/cpu/intel/fsp_model_206ax/finalize.c M src/cpu/intel/fsp_model_406dx/bootblock.c M src/cpu/intel/haswell/bootblock.c M src/cpu/intel/haswell/finalize.c M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/romstage.c M src/cpu/intel/haswell/smmrelocate.c M src/cpu/intel/hyperthreading/intel_sibling.c M src/cpu/intel/microcode/microcode.c M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_206ax/finalize.c M src/cpu/intel/slot_1/l2_cache.c M src/cpu/intel/smm/gen1/smmrelocate.c M src/cpu/via/nano/update_ucode.c M src/cpu/x86/mtrr/mtrr.c M src/cpu/x86/name/name.c M src/cpu/x86/pae/pgtbl.c M src/drivers/amd/agesa/state_machine.c M src/drivers/gic/gic.c M src/drivers/i2c/w83793/w83793.c M src/drivers/intel/fsp1_1/stack.c M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/notify.c M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/fsp2_0/upd_display.c M src/include/cpu/amd/model_10xxx_rev.h M src/include/cpu/x86/cr.h M src/lib/selfboot.c M src/mainboard/adi/rcc-dff/romstage.c M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/bettong/mptable.c M src/mainboard/amd/bettong/romstage.c M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/amd/db-ft3b-lc/mptable.c M src/mainboard/amd/gardenia/mptable.c M src/mainboard/amd/lamar/mptable.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/olivehill/mptable.c M src/mainboard/amd/olivehillplus/mptable.c M src/mainboard/amd/parmer/mptable.c M src/mainboard/amd/parmer/romstage.c M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c M src/mainboard/amd/thatcher/mptable.c M src/mainboard/amd/thatcher/romstage.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/aopen/dxplplusu/romstage.c M src/mainboard/asrock/imb-a180/mptable.c M src/mainboard/asus/am1i-a/mptable.c M src/mainboard/asus/f2a85-m/mptable.c M src/mainboard/asus/kcma-d8/resourcemap.c M src/mainboard/asus/kcma-d8/romstage.c M src/mainboard/asus/kfsn4-dre/romstage.c M src/mainboard/asus/kgpe-d16/resourcemap.c M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/bap/ode_e20XX/mptable.c M src/mainboard/bap/ode_e21XX/mptable.c M src/mainboard/biostar/a68n_5200/mptable.c M src/mainboard/biostar/am1ml/mptable.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/gizmosphere/gizmo2/mptable.c M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/kahlee/mptable.c M src/mainboard/google/link/romstage.c M src/mainboard/google/nyan/romstage.c M src/mainboard/google/nyan_big/romstage.c M src/mainboard/google/nyan_blaze/romstage.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/stout/romstage.c M src/mainboard/hp/abm/mptable.c M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/hp/pavilion_m6_1035dx/mptable.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/intel/bayleybay_fsp/romstage.c M src/mainboard/intel/cougar_canyon2/romstage.c M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/intel/harcuvar/acpi_tables.c M src/mainboard/intel/littleplains/romstage.c M src/mainboard/intel/mohonpeak/romstage.c M src/mainboard/intel/stargo2/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/kontron/ktqm77/romstage.c M src/mainboard/lenovo/g505s/mptable.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/lenovo/x220/romstage.c M src/mainboard/lenovo/x230/romstage.c M src/mainboard/msi/ms7721/mptable.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/romstage.c M src/mainboard/scaleway/tagada/acpi_tables.c M src/mainboard/siemens/mc_tcu3/romstage.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c M src/northbridge/amd/amdfam10/raminit_amdmct.c M src/northbridge/amd/amdht/h3finit.c M src/northbridge/amd/amdht/h3ncmn.c M src/northbridge/amd/amdht/ht_wrapper.c M src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c M src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c M src/northbridge/amd/amdmct/mct_ddr3/mctrci.c M src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c M src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c M src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c M src/northbridge/amd/amdmct/mct_ddr3/mctwl.c M src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c M src/northbridge/amd/amdmct/wrappers/mcti_d.c M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/fsp_rangeley/northbridge.c M src/northbridge/intel/fsp_sandybridge/northbridge.c M src/northbridge/intel/gm45/acpi.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i945/acpi.c M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/nehalem/raminit.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/x4x/acpi.c M src/northbridge/intel/x4x/raminit.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/mca.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/smi.c M src/soc/cavium/cn81xx/soc.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/car.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/include/soc/romstage.h M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/placeholders.c M src/soc/intel/baytrail/smm.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/include/soc/romstage.h M src/soc/intel/braswell/placeholders.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/braswell/smm.c M src/soc/intel/broadwell/bootblock/cpu.c M src/soc/intel/broadwell/cpu_info.c M src/soc/intel/broadwell/include/soc/cpu.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/broadwell/smi.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/include/soc/cpu.h M src/soc/intel/cannonlake/include/soc/romstage.h M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/util.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/bootblock/bootblock.c M src/soc/intel/denverton_ns/chip.c M src/soc/intel/denverton_ns/include/soc/romstage.h M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/smm.c M src/soc/intel/denverton_ns/tsc_freq.c M src/soc/intel/denverton_ns/upd_display.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/include/soc/romstage.h M src/soc/intel/fsp_baytrail/placeholders.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_baytrail/smm.c M src/soc/intel/fsp_baytrail/southcluster.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/fsp_broadwell_de/include/soc/romstage.h M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/smmrelocate.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/include/soc/cpu.h M src/soc/intel/icelake/include/soc/romstage.h M src/soc/intel/quark/include/soc/cpu.h M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/include/fsp20/soc/romstage.h M src/soc/intel/skylake/include/soc/cpu.h M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/smmrelocate.c M src/soc/mediatek/mt8173/soc.c M src/soc/nvidia/tegra124/display.c M src/soc/nvidia/tegra210/ramstage.c M src/soc/nvidia/tegra210/soc.c M src/soc/nvidia/tegra210/sor.c M src/soc/rockchip/rk3399/soc.c M src/soc/samsung/exynos5420/smp.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/smi.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/smi.c M src/southbridge/amd/rs780/cmn.c M src/southbridge/amd/sb700/early_setup.c M src/southbridge/amd/sb800/early_setup.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/common/smi.c M src/southbridge/intel/fsp_bd82x6x/lpc.c M src/southbridge/intel/fsp_bd82x6x/smi.c M src/southbridge/intel/fsp_i89xx/lpc.c M src/southbridge/intel/fsp_i89xx/romstage.c M src/southbridge/intel/fsp_i89xx/romstage.h M src/southbridge/intel/fsp_i89xx/smi.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/fsp_rangeley/romstage.h M src/southbridge/intel/i82801dx/smi.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/smi.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/smi.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/smi.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/smi.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smi.c 237 files changed, 77 insertions(+), 199 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/29300/6 -- To view, visit https://review.coreboot.org/29300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Gerrit-Change-Number: 29300 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src: Remove unneeded include "{arch, cpu}/cpu.h"
by Elyes HAOUAS (Code Review) 27 Oct '18

27 Oct '18

Elyes HAOUAS has posted comments on this change. ( https://review.coreboot.org/29300 ) Change subject: src: Remove unneeded include "{arch,cpu}/cpu.h" ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/29300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Gerrit-Change-Number: 29300 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 27 Oct 2018 12:55:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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