coreboot-gerrit September 2017

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Change in coreboot[master]: soc/intel/common/block: Update LPC lib
by Ravishankar Sarawadi (Code Review) 19 Sep '17

19 Sep '17

Hello Bora Guvendik, Lijian Zhao, I'd like you to reexamine a change. Please visit https://review.coreboot.org/21605 to look at the new patch set (#2). Change subject: soc/intel/common/block: Update LPC lib ...................................................................... soc/intel/common/block: Update LPC lib Add functions to support SoC specific functionality: 1. Setup PCH LPC interrupt routing. 2. Get SoC's generic IO decoder configuration settings. 3. Enable CLKRUN_EN for power gating LPC. Change-Id: Ib9359765f7293210044b411db49163df0418070a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc_lib.c 2 files changed, 69 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/21605/2 -- To view, visit https://review.coreboot.org/21605 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib9359765f7293210044b411db49163df0418070a Gerrit-Change-Number: 21605 Gerrit-PatchSet: 2 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: soc/intel/common/block: Update LPC lib
by Ravishankar Sarawadi (Code Review) 19 Sep '17

19 Sep '17

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/21605 Change subject: soc/intel/common/block: Update LPC lib ...................................................................... soc/intel/common/block: Update LPC lib Add wrapper functions to support SoC specific functionality: 1. Setup PCH LPC interrupt routing. 2. Get SoC's generic IO decoder configuration settings. Change-Id: Ib9359765f7293210044b411db49163df0418070a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc_lib.c 2 files changed, 69 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/21605/1 diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index 596c2b5..455f6c2 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -38,6 +38,14 @@ #define LPC_IOE_COMB_EN (1 << 1) #define LPC_IOE_COMA_EN (1 << 0) +#define PCR_DMI_LPCLGIR1 0x2730 +#define PCR_DMI_LPCLGIR2 0x2734 +#define PCR_DMI_LPCLGIR3 0x2738 +#define PCR_DMI_LPCLGIR4 0x273c + +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 + /* Serial IRQ control. SERIRQ_QUIET is the default (0). */ enum serirq_mode { SERIRQ_QUIET, @@ -75,6 +83,8 @@ void lpc_set_eiss(void); /* Set LPC Serial IRQ mode. */ void lpc_set_serirq_mode(enum serirq_mode mode); +/* Enable CLKRUN_EN for power gating LPC. */ +void lpc_enable_pci_clk_cntl(void); /* * Setup I/O Decode Range Register for LPC * ComA Range 3F8h-3FFh [2:0] @@ -82,5 +92,13 @@ * Enable ComA and ComB Port */ void lpc_io_setup_comm_a_b(void); +/* Enable PCH LPC by setting up generic decode range registers. */ +void pch_enable_lpc(void); +/* Setup PCH LPC interrupt routing. */ +void pch_lpc_interrupt_init(void); +/* Retrieve and setup SoC speicific PCH LPC interrupt routing. */ +void soc_pch_pirq_init(const struct device *dev); +/* Get SoC's generic IO decoder configuration settings. */ +void soc_get_gen_io_dec_config(const struct device *dev, uint32_t *gen_io_dec); #endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */ diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 6b5f29a..6d695ee 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -18,12 +18,16 @@ #define __SIMPLE_DEVICE__ #include <assert.h> +#include <chip.h> #include <console/console.h> #include <device/pci.h> +#include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> #include <lib.h> #include "lpc_def.h" #include <soc/pci_devs.h> +#include <soc/pcr_ids.h> void lpc_enable_fixed_io_ranges(uint16_t io_enables) { @@ -235,3 +239,50 @@ /* Enable ComA and ComB Port */ lpc_enable_fixed_io_ranges(LPC_IOE_COMA_EN | LPC_IOE_COMB_EN); } + +void pch_enable_lpc(void) +{ + /* Lookup device tree in romstage */ + const struct device *dev; + uint32_t gen_io_dec[4]; + + dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); + if (!dev || !dev->chip_info) + return; + + soc_get_gen_io_dec_config(dev, gen_io_dec); + + /* Set in PCI generic decode range registers */ + pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(0), + gen_io_dec[0]); + pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(1), + gen_io_dec[1]); + pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(2), + gen_io_dec[2]); + pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(3), + gen_io_dec[3]); + + /* Mirror these same settings in DMI PCR */ + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); +} + +void pch_lpc_interrupt_init(void) +{ + const struct device *dev; + + dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); + if (!dev || !dev->chip_info) + return; + + soc_pch_pirq_init(dev); +} + +void lpc_enable_pci_clk_cntl(void) +{ + device_t dev = PCH_DEV_LPC; + + pci_write_config8(dev, LPC_PCCTL, LPC_PCCTL_CLKRUN_EN); +} -- To view, visit https://review.coreboot.org/21605 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib9359765f7293210044b411db49163df0418070a Gerrit-Change-Number: 21605 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>

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Change in coreboot[master]: util/cbfstool: Add "expand" command to make CBFS span an fmap region
by build bot (Jenkins) (Code Review) 19 Sep '17

19 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21598 ) Change subject: util/cbfstool: Add "expand" command to make CBFS span an fmap region ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60745/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/15945/ : SUCCESS -- To view, visit https://review.coreboot.org/21598 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I160c8529ce4bfcc28685166b6d9035ade4f6f1d1 Gerrit-Change-Number: 21598 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Sep 2017 20:53:09 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: src/lib/ubsan: Indent macros to improve readability
by Ryan Salsamendi (Code Review) 19 Sep '17

19 Sep '17

Ryan Salsamendi has posted comments on this change. ( https://review.coreboot.org/21600 ) Change subject: src/lib/ubsan: Indent macros to improve readability ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/21600 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ide4e58e584a1a2bbc1b861e2c4dd943a1aeb35ab Gerrit-Change-Number: 21600 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Ryan Salsamendi <rsalsamendi(a)hotmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Sep 2017 20:46:29 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/gardenia: Fix number of memory channels
by build bot (Jenkins) (Code Review) 19 Sep '17

19 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21602 ) Change subject: amd/gardenia: Fix number of memory channels ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60744/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/15944/ : SUCCESS -- To view, visit https://review.coreboot.org/21602 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If49b6a9f37b2687ea2f64105fb9e476a89aa87ed Gerrit-Change-Number: 21602 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Sep 2017 20:28:37 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: util/cbfstool: Add "expand" command to make CBFS span an fmap region
by build bot (Jenkins) (Code Review) 19 Sep '17

19 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21598 ) Change subject: util/cbfstool: Add "expand" command to make CBFS span an fmap region ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60743/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/15943/ : SUCCESS -- To view, visit https://review.coreboot.org/21598 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I160c8529ce4bfcc28685166b6d9035ade4f6f1d1 Gerrit-Change-Number: 21598 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Sep 2017 20:26:59 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/gardenia: Fix number of memory channels
by Marshall Dawson (Code Review) 19 Sep '17

19 Sep '17

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/21602 ) Change subject: amd/gardenia: Fix number of memory channels ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/21602 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If49b6a9f37b2687ea2f64105fb9e476a89aa87ed Gerrit-Change-Number: 21602 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Tue, 19 Sep 2017 20:21:15 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/gardenia: Fix number of memory channels
by Marc Jones (Code Review) 19 Sep '17

19 Sep '17

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/21602 Change subject: amd/gardenia: Fix number of memory channels ...................................................................... amd/gardenia: Fix number of memory channels Gardenia (with Stoney Processor) has a single memory channel, not two. This corrects DMI type 17 reporting and the memory clear functions. Change-Id: If49b6a9f37b2687ea2f64105fb9e476a89aa87ed Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/mainboard/amd/gardenia/OemCustomize.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/21602/1 diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c index 3893e5d..6ca84b4 100644 --- a/src/mainboard/amd/gardenia/OemCustomize.c +++ b/src/mainboard/amd/gardenia/OemCustomize.c @@ -21,7 +21,7 @@ static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), MOTHER_BOARD_LAYERS(LAYERS_6), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), -- To view, visit https://review.coreboot.org/21602 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If49b6a9f37b2687ea2f64105fb9e476a89aa87ed Gerrit-Change-Number: 21602 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: google/kahlee: Prevent AGESA memory clear
by build bot (Jenkins) (Code Review) 19 Sep '17

19 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21596 ) Change subject: google/kahlee: Prevent AGESA memory clear ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60742/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/15942/ : SUCCESS -- To view, visit https://review.coreboot.org/21596 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9b8286ade718fa80bf3badd478ab9a7df643ab98 Gerrit-Change-Number: 21596 Gerrit-PatchSet: 2 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Sep 2017 20:18:28 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: util/cbfstool: Add "expand" command to make CBFS span an fmap region
by Patrick Georgi (Code Review) 19 Sep '17

19 Sep '17

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/21598 ) Change subject: util/cbfstool: Add "expand" command to make CBFS span an fmap region ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/21598/1/util/cbfstool/cbfstool.c File util/cbfstool/cbfstool.c: https://review.coreboot.org/#/c/21598/1/util/cbfstool/cbfstool.c@1114 PS1, Line 1114: /* Obtain the source region. */ > nit: Shouldn't this default to COREBOOT like the other commands? (Or, if it You're right. I originally used source_region which needs this guard. Fixed. -- To view, visit https://review.coreboot.org/21598 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I160c8529ce4bfcc28685166b6d9035ade4f6f1d1 Gerrit-Change-Number: 21598 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Sep 2017 20:17:43 +0000 Gerrit-HasComments: Yes

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coreboot-gerrit September 2017