coreboot-gerrit September 2017

coreboot-gerrit@coreboot.org

1 participants
1960 discussions

Change in coreboot[master]: soc/intel/braswell: Add I2C clock config options
by build bot (Jenkins) (Code Review) 04 Sep '17

04 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21370 ) Change subject: soc/intel/braswell: Add I2C clock config options ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15062/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59793/ : SUCCESS -- To view, visit https://review.coreboot.org/21370 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifae3ba4262cb3cc6416ce5054614ed7765e22c25 Gerrit-Change-Number: 21370 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Sep 2017 02:14:23 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/braswell: add USB2 PHY PERPORTRXISET UPD
by Matt DeVillier (Code Review) 04 Sep '17

04 Sep '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21373 Change subject: soc/intel/braswell: add USB2 PHY PERPORTRXISET UPD ...................................................................... soc/intel/braswell: add USB2 PHY PERPORTRXISET UPD Adapted from Chromium commits 59938a0, 5a4ea6e, 88999de. Add UPD to config USB2 PERPORTRXISET for D-stepping BSW SoC. Ensure PerPortRXISet UPD offsets align with FSP. Ensure UPD values not defined in devicetree.cb are referred from *.dsc. Original-Change-Id: Ib0cdee47692e492a78c34e2dd192447b92253e35 Original-Change-Id: If0d8419d4c70864bd385b5699e0e6d1ec515d26a Original-Change-Id: I3a1d688282303e8c367620ac8bb3e2cba7ab3dcf Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Keith Tzeng <keith.tzeng(a)quantatw.com> Change-Id: I87eda6ea6688931f1a1b069c38ffc515398ad396 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/braswell/chip.c M src/soc/intel/braswell/chip.h 2 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/21373/1 diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index afa90c3..1f68e84 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -130,22 +130,37 @@ params->Usb2Port0PerPortTxiSet = config->Usb2Port0PerPortTxiSet; params->Usb2Port0IUsbTxEmphasisEn = config->Usb2Port0IUsbTxEmphasisEn; params->Usb2Port0PerPortTxPeHalf = config->Usb2Port0PerPortTxPeHalf; + if (config->D0Usb2Port0PerPortRXISet != 0) + params->D0Usb2Port0PerPortRXISet = config->D0Usb2Port0PerPortRXISet; + params->Usb2Port1PerPortPeTxiSet = config->Usb2Port1PerPortPeTxiSet; params->Usb2Port1PerPortTxiSet = config->Usb2Port1PerPortTxiSet; params->Usb2Port1IUsbTxEmphasisEn = config->Usb2Port1IUsbTxEmphasisEn; params->Usb2Port1PerPortTxPeHalf = config->Usb2Port1PerPortTxPeHalf; + if (config->D0Usb2Port1PerPortRXISet != 0) + params->D0Usb2Port1PerPortRXISet = config->D0Usb2Port1PerPortRXISet; + params->Usb2Port2PerPortPeTxiSet = config->Usb2Port2PerPortPeTxiSet; params->Usb2Port2PerPortTxiSet = config->Usb2Port2PerPortTxiSet; params->Usb2Port2IUsbTxEmphasisEn = config->Usb2Port2IUsbTxEmphasisEn; params->Usb2Port2PerPortTxPeHalf = config->Usb2Port2PerPortTxPeHalf; + if (config->D0Usb2Port2PerPortRXISet != 0) + params->D0Usb2Port2PerPortRXISet = config->D0Usb2Port2PerPortRXISet; + params->Usb2Port3PerPortPeTxiSet = config->Usb2Port3PerPortPeTxiSet; params->Usb2Port3PerPortTxiSet = config->Usb2Port3PerPortTxiSet; params->Usb2Port3IUsbTxEmphasisEn = config->Usb2Port3IUsbTxEmphasisEn; params->Usb2Port3PerPortTxPeHalf = config->Usb2Port3PerPortTxPeHalf; + if (config->D0Usb2Port3PerPortRXISet != 0) + params->D0Usb2Port3PerPortRXISet = config->D0Usb2Port3PerPortRXISet; + params->Usb2Port4PerPortPeTxiSet = config->Usb2Port4PerPortPeTxiSet; params->Usb2Port4PerPortTxiSet = config->Usb2Port4PerPortTxiSet; params->Usb2Port4IUsbTxEmphasisEn = config->Usb2Port4IUsbTxEmphasisEn; params->Usb2Port4PerPortTxPeHalf = config->Usb2Port4PerPortTxPeHalf; + if (config->D0Usb2Port4PerPortRXISet != 0) + params->D0Usb2Port4PerPortRXISet = config->D0Usb2Port4PerPortRXISet; + params->Usb3Lane0Ow2tapgen2deemph3p5 = config->Usb3Lane0Ow2tapgen2deemph3p5; params->Usb3Lane1Ow2tapgen2deemph3p5 = @@ -252,6 +267,9 @@ fsp_display_upd_value("Usb2Port0PerPortTxPeHalf", 1, old->Usb2Port0PerPortTxPeHalf, new->Usb2Port0PerPortTxPeHalf); + fsp_display_upd_value("D0Usb2Port0PerPortRXISet", 1, + old->D0Usb2Port0PerPortRXISet, + new->D0Usb2Port0PerPortRXISet); fsp_display_upd_value("Usb2Port1PerPortPeTxiSet", 1, old->Usb2Port1PerPortPeTxiSet, new->Usb2Port1PerPortPeTxiSet); @@ -264,6 +282,9 @@ fsp_display_upd_value("Usb2Port1PerPortTxPeHalf", 1, old->Usb2Port1PerPortTxPeHalf, new->Usb2Port1PerPortTxPeHalf); + fsp_display_upd_value("D0Usb2Port1PerPortRXISet", 1, + old->D0Usb2Port1PerPortRXISet, + new->D0Usb2Port1PerPortRXISet); fsp_display_upd_value("Usb2Port2PerPortPeTxiSet", 1, old->Usb2Port2PerPortPeTxiSet, new->Usb2Port2PerPortPeTxiSet); @@ -276,6 +297,9 @@ fsp_display_upd_value("Usb2Port2PerPortTxPeHalf", 1, old->Usb2Port2PerPortTxPeHalf, new->Usb2Port2PerPortTxPeHalf); + fsp_display_upd_value("D0Usb2Port2PerPortRXISet", 1, + old->D0Usb2Port2PerPortRXISet, + new->D0Usb2Port2PerPortRXISet); fsp_display_upd_value("Usb2Port3PerPortPeTxiSet", 1, old->Usb2Port3PerPortPeTxiSet, new->Usb2Port3PerPortPeTxiSet); @@ -288,6 +312,9 @@ fsp_display_upd_value("Usb2Port3PerPortTxPeHalf", 1, old->Usb2Port3PerPortTxPeHalf, new->Usb2Port3PerPortTxPeHalf); + fsp_display_upd_value("D0Usb2Port3PerPortRXISet", 1, + old->D0Usb2Port3PerPortRXISet, + new->D0Usb2Port3PerPortRXISet); fsp_display_upd_value("Usb2Port4PerPortPeTxiSet", 1, old->Usb2Port4PerPortPeTxiSet, new->Usb2Port4PerPortPeTxiSet); @@ -300,6 +327,9 @@ fsp_display_upd_value("Usb2Port4PerPortTxPeHalf", 1, old->Usb2Port4PerPortTxPeHalf, new->Usb2Port4PerPortTxPeHalf); + fsp_display_upd_value("D0Usb2Port4PerPortRXISet", 1, + old->D0Usb2Port4PerPortRXISet, + new->D0Usb2Port4PerPortRXISet); fsp_display_upd_value("Usb3Lane0Ow2tapgen2deemph3p5", 1, old->Usb3Lane0Ow2tapgen2deemph3p5, new->Usb3Lane0Ow2tapgen2deemph3p5); diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index c661bb4..9fde4d1 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -168,6 +168,11 @@ UINT8 I2C4Frequency; UINT8 I2C5Frequency; UINT8 I2C6Frequency; + UINT8 D0Usb2Port0PerPortRXISet; /*setting for D0 stepping SOC*/ + UINT8 D0Usb2Port1PerPortRXISet; /*setting for D0 stepping SOC*/ + UINT8 D0Usb2Port2PerPortRXISet; /*setting for D0 stepping SOC*/ + UINT8 D0Usb2Port3PerPortRXISet; /*setting for D0 stepping SOC*/ + UINT8 D0Usb2Port4PerPortRXISet; /*setting for D0 stepping SOC*/ }; extern struct chip_operations soc_intel_braswell_ops; -- To view, visit https://review.coreboot.org/21373 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I87eda6ea6688931f1a1b069c38ffc515398ad396 Gerrit-Change-Number: 21373 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com>

1 0

Change in coreboot[master]: soc/intel/braswell: Add USB2 phy setting override
by Matt DeVillier (Code Review) 04 Sep '17

04 Sep '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21372 Change subject: soc/intel/braswell: Add USB2 phy setting override ...................................................................... soc/intel/braswell: Add USB2 phy setting override Adapted from Chromium commit 9756af8. Create hook function to override USB2 phy setting from board level. Original-Change-Id: Ic736dd945f01cf9f24af4ce3bd3f2757abfdeb2e Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Keith Tzeng <keith.tzeng(a)quantatw.com> Change-Id: If2ac687f6fc44e4c022a72eea7f08cb6385f0380 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/braswell/chip.c M src/soc/intel/braswell/include/soc/ramstage.h 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/21372/1 diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index e0c1a51..afa90c3 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -81,6 +81,10 @@ } } +__attribute__((weak)) void board_silicon_USB2_override(SILICON_INIT_UPD *params) +{ +} + void soc_silicon_init_params(SILICON_INIT_UPD *params) { device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); @@ -170,6 +174,7 @@ params->I2C5Frequency = config->I2C5Frequency; params->I2C6Frequency = config->I2C6Frequency; + board_silicon_USB2_override(params); } void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, diff --git a/src/soc/intel/braswell/include/soc/ramstage.h b/src/soc/intel/braswell/include/soc/ramstage.h index 8f5f9a5..c566201 100644 --- a/src/soc/intel/braswell/include/soc/ramstage.h +++ b/src/soc/intel/braswell/include/soc/ramstage.h @@ -101,6 +101,7 @@ void southcluster_enable_dev(device_t dev); void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); int SocStepping(void); +void board_silicon_USB2_override(SILICON_INIT_UPD *params); extern struct pci_operations soc_pci_ops; -- To view, visit https://review.coreboot.org/21372 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If2ac687f6fc44e4c022a72eea7f08cb6385f0380 Gerrit-Change-Number: 21372 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: soc/intel/braswell: Add SoC stepping identify helper
by Matt DeVillier (Code Review) 04 Sep '17

04 Sep '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21371 Change subject: soc/intel/braswell: Add SoC stepping identify helper ...................................................................... soc/intel/braswell: Add SoC stepping identify helper Adapted from Chromium commit 9756af8. Add SOC helper to identify BSW SoC stepping. Will be used to override USB2 phy setting based on stepping in subsequent commit. Original-Change-Id: Ic736dd945f01cf9f24af4ce3bd3f2757abfdeb2e Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Keith Tzeng <keith.tzeng(a)quantatw.com> Change-Id: Ib2371f85ea84df4b417e25ec8840d317cd918d5f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/braswell/chip.c M src/soc/intel/braswell/include/soc/ramstage.h 2 files changed, 152 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/21371/1 diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 91cb384..e0c1a51 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -169,6 +169,7 @@ params->I2C4Frequency = config->I2C4Frequency; params->I2C5Frequency = config->I2C5Frequency; params->I2C6Frequency = config->I2C6Frequency; + } void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, @@ -363,3 +364,83 @@ struct pci_operations soc_pci_ops = { .set_subsystem = &pci_set_subsystem, }; + +/** + Return SoC stepping type + + @retval SOC_STEPPING SoC stepping type +**/ +int SocStepping(void) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + u8 revid = pci_read_config8(dev, 0x8); + + switch (revid & B_PCH_LPC_RID_STEPPING_MASK) { + case V_PCH_LPC_RID_A0: + return SocA0; + case V_PCH_LPC_RID_A1: + return SocA1; + case V_PCH_LPC_RID_A2: + return SocA2; + case V_PCH_LPC_RID_A3: + return SocA3; + case V_PCH_LPC_RID_A4: + return SocA4; + case V_PCH_LPC_RID_A5: + return SocA5; + case V_PCH_LPC_RID_A6: + return SocA6; + case V_PCH_LPC_RID_A7: + return SocA7; + case V_PCH_LPC_RID_B0: + return SocB0; + case V_PCH_LPC_RID_B1: + return SocB1; + case V_PCH_LPC_RID_B2: + return SocB2; + case V_PCH_LPC_RID_B3: + return SocB3; + case V_PCH_LPC_RID_B4: + return SocB4; + case V_PCH_LPC_RID_B5: + return SocB5; + case V_PCH_LPC_RID_B6: + return SocB6; + case V_PCH_LPC_RID_B7: + return SocB7; + case V_PCH_LPC_RID_C0: + return SocC0; + case V_PCH_LPC_RID_C1: + return SocC1; + case V_PCH_LPC_RID_C2: + return SocC2; + case V_PCH_LPC_RID_C3: + return SocC3; + case V_PCH_LPC_RID_C4: + return SocC4; + case V_PCH_LPC_RID_C5: + return SocC5; + case V_PCH_LPC_RID_C6: + return SocC6; + case V_PCH_LPC_RID_C7: + return SocC7; + case V_PCH_LPC_RID_D0: + return SocD0; + case V_PCH_LPC_RID_D1: + return SocD1; + case V_PCH_LPC_RID_D2: + return SocD2; + case V_PCH_LPC_RID_D3: + return SocD3; + case V_PCH_LPC_RID_D4: + return SocD4; + case V_PCH_LPC_RID_D5: + return SocD5; + case V_PCH_LPC_RID_D6: + return SocD6; + case V_PCH_LPC_RID_D7: + return SocD7; + default: + return SocSteppingMax; + } +} diff --git a/src/soc/intel/braswell/include/soc/ramstage.h b/src/soc/intel/braswell/include/soc/ramstage.h index 07b6633..8f5f9a5 100644 --- a/src/soc/intel/braswell/include/soc/ramstage.h +++ b/src/soc/intel/braswell/include/soc/ramstage.h @@ -21,6 +21,76 @@ #include <device/device.h> #include <fsp/ramstage.h> +#define V_PCH_LPC_RID_A0 0x00 // A0 Stepping +#define V_PCH_LPC_RID_A1 0x04 // A1 Stepping +#define V_PCH_LPC_RID_A2 0x08 // A2 Stepping +#define V_PCH_LPC_RID_A3 0x0C // A3 Stepping +#define V_PCH_LPC_RID_A4 0x80 // A4 Stepping +#define V_PCH_LPC_RID_A5 0x84 // A5 Stepping +#define V_PCH_LPC_RID_A6 0x88 // A6 Stepping +#define V_PCH_LPC_RID_A7 0x8C // A7 Stepping +#define V_PCH_LPC_RID_B0 0x10 // B0 Stepping +#define V_PCH_LPC_RID_B1 0x14 // B1 Stepping +#define V_PCH_LPC_RID_B2 0x18 // B2 Stepping +#define V_PCH_LPC_RID_B3 0x1C // B3 Stepping +#define V_PCH_LPC_RID_B4 0x90 // B4 Stepping +#define V_PCH_LPC_RID_B5 0x94 // B5 Stepping +#define V_PCH_LPC_RID_B6 0x98 // B6 Stepping +#define V_PCH_LPC_RID_B7 0x9C // B7 Stepping +#define V_PCH_LPC_RID_C0 0x20 // C0 Stepping +#define V_PCH_LPC_RID_C1 0x24 // C1 Stepping +#define V_PCH_LPC_RID_C2 0x28 // C2 Stepping +#define V_PCH_LPC_RID_C3 0x2C // C3 Stepping +#define V_PCH_LPC_RID_C4 0xA0 // C4 Stepping +#define V_PCH_LPC_RID_C5 0xA4 // C5 Stepping +#define V_PCH_LPC_RID_C6 0xA8 // C6 Stepping +#define V_PCH_LPC_RID_C7 0xAC // C7 Stepping +#define V_PCH_LPC_RID_D0 0x30 // D0 Stepping +#define V_PCH_LPC_RID_D1 0x34 // D1 Stepping +#define V_PCH_LPC_RID_D2 0x38 // D2 Stepping +#define V_PCH_LPC_RID_D3 0x3C // D3 Stepping +#define V_PCH_LPC_RID_D4 0xB0 // D4 Stepping +#define V_PCH_LPC_RID_D5 0xB4 // D5 Stepping +#define V_PCH_LPC_RID_D6 0xB8 // D6 Stepping +#define V_PCH_LPC_RID_D7 0xBC // D7 Stepping +#define B_PCH_LPC_RID_STEPPING_MASK 0xFC // SoC Stepping Mask (Ignoring Package Type) + +enum { + SocA0 = 0, + SocA1 = 1, + SocA2 = 2, + SocA3 = 3, + SocA4 = 4, + SocA5 = 5, + SocA6 = 6, + SocA7 = 7, + SocB0 = 8, + SocB1 = 9, + SocB2 = 10, + SocB3 = 11, + SocB4 = 12, + SocB5 = 13, + SocB6 = 14, + SocB7 = 15, + SocC0 = 16, + SocC1 = 17, + SocC2 = 18, + SocC3 = 19, + SocC4 = 20, + SocC5 = 21, + SocC6 = 22, + SocC7 = 23, + SocD0 = 24, + SocD1 = 25, + SocD2 = 26, + SocD3 = 27, + SocD4 = 28, + SocD5 = 29, + SocD6 = 30, + SocD7 = 31, + SocSteppingMax +}; + /* * The soc_init_pre_device() function is called prior to device * initialization, but it's after console and cbmem has been reinitialized. @@ -30,6 +100,7 @@ void set_max_freq(void); void southcluster_enable_dev(device_t dev); void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); +int SocStepping(void); extern struct pci_operations soc_pci_ops; -- To view, visit https://review.coreboot.org/21371 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib2371f85ea84df4b417e25ec8840d317cd918d5f Gerrit-Change-Number: 21371 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: soc/intel/braswell: Add I2C clock config options
by Matt DeVillier (Code Review) 04 Sep '17

04 Sep '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21370 Change subject: soc/intel/braswell: Add I2C clock config options ...................................................................... soc/intel/braswell: Add I2C clock config options Cherry-pick from Chromium commit e3c1ec2. This change includes - FSP config parameters to configure I2C clock speed. - Options are 0 - 100Khz, 1 - 400Khz, 2 - 1Mhz and default is 400Khz. Original-Change-Id: Iab2bf3997102908583078f5f1d185d6c66561390 Original-Signed-off-by: Divagar Mohandass <divagar.mohandass(a)intel.com> Original-Tested-by: Kenji Chen <kenji.chen(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Ifae3ba4262cb3cc6416ce5054614ed7765e22c25 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/braswell/chip.c M src/soc/intel/braswell/chip.h 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/21370/1 diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 4d7b906..91cb384 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -162,6 +162,13 @@ params->ISPEnable = config->ISPEnable; params->ISPPciDevConfig = config->ISPPciDevConfig; params->PcdSdDetectChk = config->PcdSdDetectChk; + params->I2C0Frequency = config->I2C0Frequency; + params->I2C1Frequency = config->I2C1Frequency; + params->I2C2Frequency = config->I2C2Frequency; + params->I2C3Frequency = config->I2C3Frequency; + params->I2C4Frequency = config->I2C4Frequency; + params->I2C5Frequency = config->I2C5Frequency; + params->I2C6Frequency = config->I2C6Frequency; } void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 8c3f143..c661bb4 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -161,6 +161,13 @@ UINT8 ISPEnable; UINT8 ISPPciDevConfig; UINT8 PcdSdDetectChk; /*Enable\Disable SD Card Detect Simulation*/ + UINT8 I2C0Frequency; /* 0 - 100Khz, 1 - 400Khz, 2 - 1Mhz */ + UINT8 I2C1Frequency; + UINT8 I2C2Frequency; + UINT8 I2C3Frequency; + UINT8 I2C4Frequency; + UINT8 I2C5Frequency; + UINT8 I2C6Frequency; }; extern struct chip_operations soc_intel_braswell_ops; -- To view, visit https://review.coreboot.org/21370 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifae3ba4262cb3cc6416ce5054614ed7765e22c25 Gerrit-Change-Number: 21370 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: drivers/intel/fsp1_1: don't fail on revision mismatch
by Matt DeVillier (Code Review) 04 Sep '17

04 Sep '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21369 Change subject: drivers/intel/fsp1_1: don't fail on revision mismatch ...................................................................... drivers/intel/fsp1_1: don't fail on revision mismatch Braswell ChromeOS devices ship with FSP blobs which have various FSP Header Revisions, but are all compatible with the latest header file. Therefore, warn of the mismatch rather than silent failing and falling into a reboot loop. Move the revision check/warning from prior to tempraminit to after, as console output is not available prior to tempraminit. TEST: build/boot google/cyan and edgar boards, observe no adverse effects from using updated/mismatched FSP header. Change-Id: I8934675a2deed260886a83fa34512904c40af8e1 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/drivers/intel/fsp1_1/bootblock.c M src/drivers/intel/fsp1_1/fsp_util.c 2 files changed, 9 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/21369/1 diff --git a/src/drivers/intel/fsp1_1/bootblock.c b/src/drivers/intel/fsp1_1/bootblock.c index cf9e134..9554d2d 100644 --- a/src/drivers/intel/fsp1_1/bootblock.c +++ b/src/drivers/intel/fsp1_1/bootblock.c @@ -36,7 +36,7 @@ fih = find_fsp(CONFIG_FSP_LOC); /* Check the FSP header */ if (((uintptr_t)fih >= ERROR_NO_FV_SIG) && - ((uintptr_t)fih <= ERROR_FSP_REV_MISMATCH)) { + ((uintptr_t)fih <= ERROR_FSP_SIG_MISMATCH)) { printk(BIOS_ERR, "FSP header error %p, ", fih); fih = NULL; } diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 34d6e48..5517695 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -78,10 +78,6 @@ if (*image_id != FSP_IMAGE_ID) return (FSP_INFO_HEADER *)ERROR_FSP_SIG_MISMATCH; - /* Verify the FSP Revision */ - if (fsp_ptr.fih->ImageRevision != FSP_IMAGE_REV) - return (FSP_INFO_HEADER *)ERROR_FSP_REV_MISMATCH; - return fsp_ptr.fih; } @@ -103,6 +99,14 @@ (u8)((fsp_header->ImageRevision >> 16) & 0xff), (u8)((fsp_header->ImageRevision >> 8) & 0xff), (u8)(fsp_header->ImageRevision & 0xff)); + /* Verify the FSP Revision */ + if (fsp_header->ImageRevision != FSP_IMAGE_REV) { + printk(BIOS_WARNING, "Warning: Expected FSP Revision: %d.%d.%d.%d\n", + (u8)((FSP_IMAGE_REV >> 24) & 0xff), + (u8)((FSP_IMAGE_REV >> 16) & 0xff), + (u8)((FSP_IMAGE_REV >> 8) & 0xff), + (u8)(FSP_IMAGE_REV & 0xff)); + } #if IS_ENABLED(CONFIG_DISPLAY_FSP_ENTRY_POINTS) printk(BIOS_SPEW, "FSP Entry Points:\n"); printk(BIOS_SPEW, " 0x%p: Image Base\n", fsp_base); -- To view, visit https://review.coreboot.org/21369 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8934675a2deed260886a83fa34512904c40af8e1 Gerrit-Change-Number: 21369 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: vc/intel/fsp/fsp1_1/braswell: Update FspUpdVpd.h to v 1.1.7.0
by Matt DeVillier (Code Review) 04 Sep '17

04 Sep '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21368 Change subject: vc/intel/fsp/fsp1_1/braswell: Update FspUpdVpd.h to v 1.1.7.0 ...................................................................... vc/intel/fsp/fsp1_1/braswell: Update FspUpdVpd.h to v 1.1.7.0 Cherry-pick from Chromium 414024e. Update the FSP 1.1 header to version 1.1.7.0, required for susequent Chromium cherry-picks and to-be-merged Braswell CrOS devices. As this header update doesn't shift offsets, only adds new fields in previously unused/reserved space, it should not negatively impact existing boards built against the older header version. Original-Change-Id: Ic378b3c10769c10d8e47c8c76b8e397ddb9ce020 Original-Signed-off-by: Martin Roth <martinroth(a)google.com> Original-Reviewed-by: Hannah Williams <hannah.williams(a)intel.com> Original-Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Original-Tested-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Id33d41dee998cfa033264a98dfee40e2d8feead8 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h 1 file changed, 81 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/21368/1 diff --git a/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h index 61673c6..1ae1d03 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h +++ b/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2015, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -193,8 +193,43 @@ **/ UINT8 PcdCaMirrorEn; /** Offset 0x0043 + DDR3 Auto Self Refresh + Enable/Disable DDR3 Auto Self Refresh **/ - UINT8 ReservedMemoryInitUpd[189]; + UINT8 PcdDdr3AutoSelfRefreshEnable; +/** Offset 0x0044 + Disable Auto Detect Dram for LPDDR3 memory + To Enable/Disable AutoDetectDram +**/ + UINT8 PcdDisableAutoDetectDram; +/** Offset 0x0045 + Dram Width + Select Dram Width +**/ + UINT8 PcdDramWidth; +/** Offset 0x0046 + Dual Rank Enable + To Enable/Disable DualRankDram +**/ + UINT8 PcdDualRankDram; +/** Offset 0x0047 + Dram Density + Select Dram Density +**/ + UINT8 PcdDramDensity; +/** Offset 0x0048 + Channel 0 RX ODT Limit For Rx Power Training + Select RX ODT Limit for Channel 0 +**/ + UINT8 PcdRxOdtLimitChannel0; +/** Offset 0x0049 + Channel 1 RX ODT Limit For Rx Power Training + Select RX ODT Limit for Channel 1 +**/ + UINT8 PcdRxOdtLimitChannel1; +/** Offset 0x004A +**/ + UINT8 ReservedMemoryInitUpd[182]; } MEMORY_INIT_UPD; typedef struct { @@ -441,8 +476,8 @@ **/ UINT8 PcdTurboMode; /** Offset 0x0161 - Pnp-Power & Performance - select Pnp type + Pnp Setting Type + Select Pnp type **/ UINT8 PcdPnpSettings; /** Offset 0x0162 @@ -452,7 +487,46 @@ UINT8 PcdSdDetectChk; /** Offset 0x0163 **/ - UINT8 ReservedSiliconInitUpd[411]; + UINT8 I2C0Frequency; +/** Offset 0x0164 +**/ + UINT8 I2C1Frequency; +/** Offset 0x0165 +**/ + UINT8 I2C2Frequency; +/** Offset 0x0166 +**/ + UINT8 I2C3Frequency; +/** Offset 0x0167 +**/ + UINT8 I2C4Frequency; +/** Offset 0x0168 +**/ + UINT8 I2C5Frequency; +/** Offset 0x0169 +**/ + UINT8 I2C6Frequency; +/** Offset 0x016A +**/ + UINT8 D0Usb2Port0PerPortRXISet; +/** Offset 0x016B +**/ + UINT8 D0Usb2Port1PerPortRXISet; +/** Offset 0x016C +**/ + UINT8 D0Usb2Port2PerPortRXISet; +/** Offset 0x016D +**/ + UINT8 D0Usb2Port3PerPortRXISet; +/** Offset 0x016E +**/ + UINT8 D0Usb2Port4PerPortRXISet; +/** Offset 0x016F +**/ + UINT8 D0VnnBump100mV; +/** Offset 0x170 +**/ + UINT8 ReservedSiliconInitUpd[398]; } SILICON_INIT_UPD; #define FSP_UPD_SIGNATURE 0x2444505557534224 /* '$BSWUPD$' */ @@ -484,13 +558,13 @@ /** Offset 0x0100 **/ SILICON_INIT_UPD SiliconInitUpd; -/** Offset 0x02FE +/** Offset 0x0305 **/ UINT16 PcdRegionTerminator; } UPD_DATA_REGION; #define FSP_IMAGE_ID 0x2450534657534224 /* '$BSWFSP$' */ -#define FSP_IMAGE_REV 0x01010100 +#define FSP_IMAGE_REV 0x01010700 typedef struct _VPD_DATA_REGION { /** Offset 0x0000 -- To view, visit https://review.coreboot.org/21368 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id33d41dee998cfa033264a98dfee40e2d8feead8 Gerrit-Change-Number: 21368 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: rmodtool: Increase limit on number of symbols
by Philippe Mathieu-Daudé (Code Review) 04 Sep '17

04 Sep '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/21360 ) Change subject: rmodtool: Increase limit on number of symbols ...................................................................... Patch Set 1: Code-Review-1 (2 comments) add a new variable https://review.coreboot.org/#/c/21360/1/util/cbfstool/elfheaders.c File util/cbfstool/elfheaders.c: https://review.coreboot.org/#/c/21360/1/util/cbfstool/elfheaders.c@a438 PS1, Line 438: name this shnum (same type, Elf64_Half) https://review.coreboot.org/#/c/21360/1/util/cbfstool/elfheaders.c@438 PS1, Line 438: Elf64_Word use Elf64_Xword for i (new var) -- To view, visit https://review.coreboot.org/21360 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9ad2f64c452cef2e7bf957f766600891cb5ae798 Gerrit-Change-Number: 21360 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Sep 2017 00:17:55 +0000 Gerrit-HasComments: Yes

1 0

Change in coreboot[master]: armv7/Makefile.inc: Make cflags compiler agnostic
by Philippe Mathieu-Daudé (Code Review) 04 Sep '17

04 Sep '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/21357 ) Change subject: armv7/Makefile.inc: Make cflags compiler agnostic ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/21357 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I00b7ab5ad25349382bef3cc5001f3a3297f11ca0 Gerrit-Change-Number: 21357 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Sep 2017 00:10:32 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: agesa/f15tn: Put parentheses around logic op
by Philippe Mathieu-Daudé (Code Review) 04 Sep '17

04 Sep '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/21361 ) Change subject: agesa/f15tn: Put parentheses around logic op ...................................................................... Patch Set 1: Code-Review-1 simply use: if ( LocalCfgPtr->Gec.PtrDynamicGecRomAddress != 0 ) { or if ( LocalCfgPtr->Gec.PtrDynamicGecRomAddress ) { -- To view, visit https://review.coreboot.org/21361 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4d7dfaa5fcf0e95acd650e4c129e0899b5d68f09 Gerrit-Change-Number: 21361 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Sep 2017 00:07:53 +0000 Gerrit-HasComments: No

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2017