coreboot-gerrit September 2017

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Change in coreboot[master]: soc/intel/cannonlake: Add serialio device config
by Lijian Zhao (Code Review) 08 Sep '17

08 Sep '17

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/21411 Change subject: soc/intel/cannonlake: Add serialio device config ...................................................................... soc/intel/cannonlake: Add serialio device config Add SerialIO device mode configuration, device mode definition mirrored from FSP. Change-Id: I7009120d69646cf60cb5a622e438ae1eeb6498cf Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/chip.h A src/soc/intel/cannonlake/include/soc/serialio.h 3 files changed, 154 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/21411/6 diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index bee2517..3c6451d 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -24,6 +24,55 @@ #include <soc/ramstage.h> #include <string.h> +static void parse_devicetree(FSP_S_CONFIG *params) +{ + struct device *dev = SA_DEV_ROOT; + const config_t *config = dev->chip_info; + + int SerialIoDev[PchSerialIoIndexMAX] = { + PCH_DEVFN_I2C0, + PCH_DEVFN_I2C1, + PCH_DEVFN_I2C2, + PCH_DEVFN_I2C3, + PCH_DEVFN_I2C4, + PCH_DEVFN_I2C5, + PCH_DEVFN_GSPI0, + PCH_DEVFN_GSPI1, + PCH_DEVFN_GSPI2, + PCH_DEVFN_UART0, + PCH_DEVFN_UART1, + PCH_DEVFN_UART2 + }; + + if (!dev) { + printk(BIOS_ERR, "Could not find root device\n"); + return; + } + /* Only disable bus 0 devices. */ + for (dev = dev->bus->children; dev; dev = dev->sibling) { + for (int i = 0; i < PchSerialIoIndexMAX; i++) { + if ((dev->path.pci.devfn) == SerialIoDev[i]) { + if (!dev->enabled) { + params->SerialIoDevMode[i] = + PchSerialIoDisabled; + break; + } else { + params->SerialIoDevMode[i] = + PchSerialIoPci; + if (config->SerialIoDevMode[i] == + PchSerialIoAcpi + || config->SerialIoDevMode[i] == + PchSerialIoHidden) + params->SerialIoDevMode[i] = + config->SerialIoDevMode[i]; + break; + } + + } + } + } +} + void soc_init_pre_device(void *chip_info) { /* Perform silicon specific init. */ @@ -36,17 +85,17 @@ } static struct device_operations pci_domain_ops = { - .read_resources = &pci_domain_read_resources, - .set_resources = &pci_domain_set_resources, - .scan_bus = &pci_domain_scan_bus, - .ops_pci_bus = &pci_bus_default_ops, + .read_resources = &pci_domain_read_resources, + .set_resources = &pci_domain_set_resources, + .scan_bus = &pci_domain_scan_bus, + .ops_pci_bus = &pci_bus_default_ops, }; static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .init = DEVICE_NOOP, + .init = DEVICE_NOOP, }; static void soc_enable(device_t dev) @@ -60,8 +109,8 @@ struct chip_operations soc_intel_cannonlake_ops = { CHIP_NAME("Intel Cannonlake") - .enable_dev = &soc_enable, - .init = &soc_init_pre_device, + .enable_dev = &soc_enable, + .init = &soc_init_pre_device, }; /* UPD parameters to be initialized before SiliconInit */ @@ -71,6 +120,9 @@ FSP_S_CONFIG *params = &supd->FspsConfig; const struct device *dev = SA_DEV_ROOT; const config_t *config = dev->chip_info; + + /* Parse device tree and disable unused device */ + parse_devicetree(params); /* Set USB OC pin to 0 first */ for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) { @@ -88,9 +140,9 @@ params->SataMode = config->SataMode; params->SataSalpSupport = config->SataSalpSupport; memcpy(params->SataPortsEnable, config->SataPortsEnable, - sizeof(params->SataPortsEnable)); + sizeof(params->SataPortsEnable)); memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, - sizeof(params->SataPortsDevSlp)); + sizeof(params->SataPortsDevSlp)); /* Lan */ params->PchLanEnable = config->PchLanEnable; @@ -101,18 +153,13 @@ /* USB */ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { - params->PortUsb20Enable[i] = - config->usb2_ports[i].enable; - params->Usb2OverCurrentPin[i] = - config->usb2_ports[i].ocpin; - params->Usb2AfePetxiset[i] = - config->usb2_ports[i].pre_emp_bias; - params->Usb2AfeTxiset[i] = - config->usb2_ports[i].tx_bias; + params->PortUsb20Enable[i] = config->usb2_ports[i].enable; + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias; + params->Usb2AfeTxiset[i] = config->usb2_ports[i].tx_bias; params->Usb2AfePredeemp[i] = - config->usb2_ports[i].tx_emp_enable; - params->Usb2AfePehalfbit[i] = - config->usb2_ports[i].pre_emp_bit; + config->usb2_ports[i].tx_emp_enable; + params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit; } for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { @@ -121,12 +168,12 @@ if (config->usb3_ports[i].tx_de_emp) { params->Usb3HsioTxDeEmphEnable[i] = 1; params->Usb3HsioTxDeEmph[i] = - config->usb3_ports[i].tx_de_emp; + config->usb3_ports[i].tx_de_emp; } if (config->usb3_ports[i].tx_downscale_amp) { params->Usb3HsioTxDownscaleAmpEnable[i] = 1; params->Usb3HsioTxDownscaleAmp[i] = - config->usb3_ports[i].tx_downscale_amp; + config->usb3_ports[i].tx_downscale_amp; } } @@ -150,7 +197,8 @@ } /* Mainboard GPIO Configuration */ -__attribute__((weak)) void mainboard_silicon_init_params(FSP_S_CONFIG *params) +__attribute__ ((weak)) +void mainboard_silicon_init_params(FSP_S_CONFIG *params) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 0ed41fc..a48b7fa 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -20,6 +20,8 @@ #include <intelblocks/gspi.h> #include <stdint.h> +#include <soc/pci_devs.h> +#include <soc/serialio.h> #include <soc/usb.h> #include <soc/vr_config.h> @@ -39,16 +41,16 @@ uint8_t pirqh_routing; /* GPE configuration */ - uint32_t gpe0_en_1; /* GPE0_EN_31_0 */ - uint32_t gpe0_en_2; /* GPE0_EN_63_32 */ - uint32_t gpe0_en_3; /* GPE0_EN_95_64 */ - uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */ + uint32_t gpe0_en_1; /* GPE0_EN_31_0 */ + uint32_t gpe0_en_2; /* GPE0_EN_63_32 */ + uint32_t gpe0_en_3; /* GPE0_EN_95_64 */ + uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */ /* Gpio group routed to each dword of the GPE0 block. Values are * of the form GPP_[A:G] or GPD. */ - uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ - uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ - uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ + uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ + uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ + uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ /* Generic IO decode ranges */ uint32_t gen1_dec; @@ -161,8 +163,10 @@ uint8_t TcoIrqEnable; enum { - CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */ - CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */ + /* FSP handles locking per UPDs */ + CHIPSET_LOCKDOWN_FSP = 0, + /* coreboot handles locking */ + CHIPSET_LOCKDOWN_COREBOOT, } chipset_lockdown; uint8_t FspSkipMpInit; @@ -194,6 +198,31 @@ * 0x02000000 - 32MiB and beyond */ uint32_t PrmrrSize; + + /* + * SerialIO device mode selection: + * + * Device index: + * PchSerialIoIndexI2C0 + * PchSerialIoIndexI2C1 + * PchSerialIoIndexI2C2 + * PchSerialIoIndexI2C3 + * PchSerialIoIndexI2C4 + * PchSerialIoIndexI2C5 + * PchSerialIoIndexSPI0 + * PchSerialIoIndexSPI1 + * PchSerialIoIndexSPI2 + * PchSerialIoIndexUART0 + * PchSerialIoIndexUART1 + * PchSerialIoIndexUART2 + * + * Mode select: + * PchSerialIoDisabled + * PchSerialIoPci + * PchSerialIoAcpi + * PchSerialIoHidden + */ + uint8_t SerialIoDevMode[PchSerialIoIndexMAX]; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/include/soc/serialio.h b/src/soc/intel/cannonlake/include/soc/serialio.h new file mode 100644 index 0000000..e152770 --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/serialio.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SERIALIO_H_ +#define _SERIALIO_H_ + +typedef enum { + PchSerialIoDisabled, + PchSerialIoPci, + PchSerialIoAcpi, + PchSerialIoHidden, +} PCH_SERIAL_IO_MODE; + +typedef enum { + PchSerialIoIndexI2C0, + PchSerialIoIndexI2C1, + PchSerialIoIndexI2C2, + PchSerialIoIndexI2C3, + PchSerialIoIndexI2C4, + PchSerialIoIndexI2C5, + PchSerialIoIndexSPI0, + PchSerialIoIndexSPI1, + PchSerialIoIndexSPI2, + PchSerialIoIndexUART0, + PchSerialIoIndexUART1, + PchSerialIoIndexUART2, + PchSerialIoIndexMAX +} PCH_SERIAL_IO_CONTROLLER; + +#endif -- To view, visit https://review.coreboot.org/21411 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7009120d69646cf60cb5a622e438ae1eeb6498cf Gerrit-Change-Number: 21411 Gerrit-PatchSet: 6 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vaibhav Shankar <vaibhav.shankar(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Add common ACPI support for CNL
by build bot (Jenkins) (Code Review) 08 Sep '17

08 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21076 ) Change subject: soc/intel/cannonlake: Add common ACPI support for CNL ...................................................................... Patch Set 33: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15303/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60057/ : SUCCESS -- To view, visit https://review.coreboot.org/21076 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibc16d2afdd3cb9bad2ecb85cf320c88504409707 Gerrit-Change-Number: 21076 Gerrit-PatchSet: 33 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Sep 2017 00:38:59 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add common ACPI support for CNL
by build bot (Jenkins) (Code Review) 08 Sep '17

08 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21076 ) Change subject: soc/intel/cannonlake: Add common ACPI support for CNL ...................................................................... Patch Set 32: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/60056/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/15302/ : SUCCESS -- To view, visit https://review.coreboot.org/21076 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibc16d2afdd3cb9bad2ecb85cf320c88504409707 Gerrit-Change-Number: 21076 Gerrit-PatchSet: 32 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Sep 2017 00:24:59 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add common ACPI support for CNL
by build bot (Jenkins) (Code Review) 08 Sep '17

08 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21076 ) Change subject: soc/intel/cannonlake: Add common ACPI support for CNL ...................................................................... Patch Set 31: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/60055/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/15301/ : SUCCESS -- To view, visit https://review.coreboot.org/21076 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibc16d2afdd3cb9bad2ecb85cf320c88504409707 Gerrit-Change-Number: 21076 Gerrit-PatchSet: 31 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Sep 2017 00:09:42 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amdfw: Clean up makefiles a bit more
by build bot (Jenkins) (Code Review) 07 Sep '17

07 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21451 ) Change subject: amdfw: Clean up makefiles a bit more ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15300/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60054/ : SUCCESS -- To view, visit https://review.coreboot.org/21451 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I194b4c790b3e35353d480d34b60507a00f10ef11 Gerrit-Change-Number: 21451 Gerrit-PatchSet: 4 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Sep 2017 22:47:32 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amdfw: Clean up makefiles a bit more
by build bot (Jenkins) (Code Review) 07 Sep '17

07 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21451 ) Change subject: amdfw: Clean up makefiles a bit more ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/60053/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/15299/ : SUCCESS -- To view, visit https://review.coreboot.org/21451 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I194b4c790b3e35353d480d34b60507a00f10ef11 Gerrit-Change-Number: 21451 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Sep 2017 22:39:39 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amdfw: Clean up makefiles a bit more
by build bot (Jenkins) (Code Review) 07 Sep '17

07 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21451 ) Change subject: amdfw: Clean up makefiles a bit more ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/15298/ : ABORTED https://qa.coreboot.org/job/coreboot-gerrit/60052/ : ABORTED -- To view, visit https://review.coreboot.org/21451 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I194b4c790b3e35353d480d34b60507a00f10ef11 Gerrit-Change-Number: 21451 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Sep 2017 22:34:49 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: drivers/intel/gma/vbt.c: Add GENERAL DEFINITIONS block to fake vbt
by build bot (Jenkins) (Code Review) 07 Sep '17

07 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21448 ) Change subject: drivers/intel/gma/vbt.c: Add GENERAL DEFINITIONS block to fake vbt ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15297/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60051/ : SUCCESS -- To view, visit https://review.coreboot.org/21448 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5bce00d2e37d77c27cf0022c7dab3444c3699dcf Gerrit-Change-Number: 21448 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Sep 2017 21:48:16 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: drivers/intel/gma/vbt.c: Add GENERAL DEFINITIONS block to fake vbt
by Arthur Heymans (Code Review) 07 Sep '17

07 Sep '17

Hello Patrick Rudolph, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/21448 to look at the new patch set (#2). Change subject: drivers/intel/gma/vbt.c: Add GENERAL DEFINITIONS block to fake vbt ...................................................................... drivers/intel/gma/vbt.c: Add GENERAL DEFINITIONS block to fake vbt This is needed for Linux (at least 4.12) to know on which DDC gmbus to probe for VGA edid. TESTED on dg43gt: Use NGI with a payload like grub that doesn't override VBT (seavgabios) with a DVI-I to VGA adapter and observe that Linux can properly modeset the display. Change-Id: I5bce00d2e37d77c27cf0022c7dab3444c3699dcf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/gma/vbt.c 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/21448/2 -- To view, visit https://review.coreboot.org/21448 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I5bce00d2e37d77c27cf0022c7dab3444c3699dcf Gerrit-Change-Number: 21448 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: drivers/intel/gma/vbt.c: Add GENERAL DEFINITIONS block to fake vbt
by Arthur Heymans (Code Review) 07 Sep '17

07 Sep '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/21448 ) Change subject: drivers/intel/gma/vbt.c: Add GENERAL DEFINITIONS block to fake vbt ...................................................................... Patch Set 1: > Maybe don't add the general definitions block at all if VGADDC? > Other- > wise somebody should check if the incomplete general definitions > block > has any unwanted side effects (e.g. does LVDS still work? DP dual > mode? > etc.). good idea. I was thinking that this change be hard to test on all platform using it but restricting to only when needed seems to be a good solution here to avoid potential regressions. -- To view, visit https://review.coreboot.org/21448 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5bce00d2e37d77c27cf0022c7dab3444c3699dcf Gerrit-Change-Number: 21448 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Sep 2017 21:34:32 +0000 Gerrit-HasComments: No

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coreboot-gerrit September 2017