coreboot-gerrit September 2017

coreboot-gerrit@coreboot.org

1 participants
1960 discussions

Change in coreboot[master]: amd/stoneyridge: Convert MP init to mp_init_with_smm
by build bot (Jenkins) (Code Review) 11 Sep '17

11 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21498 ) Change subject: amd/stoneyridge: Convert MP init to mp_init_with_smm ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15489/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60264/ : SUCCESS -- To view, visit https://review.coreboot.org/21498 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie54295cb00c6835947456e8818a289b7eb260914 Gerrit-Change-Number: 21498 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Sep 2017 23:03:44 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: amd/stoneyridge: Remove EXT_CONF_SUPPORT check
by build bot (Jenkins) (Code Review) 11 Sep '17

11 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21497 ) Change subject: amd/stoneyridge: Remove EXT_CONF_SUPPORT check ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15488/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60263/ : SUCCESS -- To view, visit https://review.coreboot.org/21497 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic58c47fc5f568d17f5027c96d4152b0e5b3e1d14 Gerrit-Change-Number: 21497 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Sep 2017 23:00:18 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/cannonlake: Add common ACPI support for CNL
by build bot (Jenkins) (Code Review) 11 Sep '17

11 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21076 ) Change subject: soc/intel/cannonlake: Add common ACPI support for CNL ...................................................................... Patch Set 37: No Builds Executed -- To view, visit https://review.coreboot.org/21076 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibc16d2afdd3cb9bad2ecb85cf320c88504409707 Gerrit-Change-Number: 21076 Gerrit-PatchSet: 37 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Sep 2017 22:58:54 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: cpu/intel/car: Add postcar frame support
by build bot (Jenkins) (Code Review) 11 Sep '17

11 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21329 ) Change subject: cpu/intel/car: Add postcar frame support ...................................................................... Patch Set 6: No Builds Executed -- To view, visit https://review.coreboot.org/21329 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9ab996e46e4f96320143022938477a5fd2046ed7 Gerrit-Change-Number: 21329 Gerrit-PatchSet: 6 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Sep 2017 22:58:24 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: amd/stoneyridge: Simplify memory hole calculation
by build bot (Jenkins) (Code Review) 11 Sep '17

11 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21496 ) Change subject: amd/stoneyridge: Simplify memory hole calculation ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15487/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60262/ : SUCCESS -- To view, visit https://review.coreboot.org/21496 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id15a88897e29bff28ab7c498dc4d3818834f08b2 Gerrit-Change-Number: 21496 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Sep 2017 22:54:56 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: amd/stoneyridge: Remove PSP BAR init from cpu init
by build bot (Jenkins) (Code Review) 11 Sep '17

11 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21492 ) Change subject: amd/stoneyridge: Remove PSP BAR init from cpu init ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15483/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60259/ : SUCCESS -- To view, visit https://review.coreboot.org/21492 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e77fad3abdcb6482f1b9d849e5922a426dff5f5 Gerrit-Change-Number: 21492 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Sep 2017 22:54:38 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: cpu/intel/car/cache_as_ram.inc: Fix long standing issues
by Keith Hui (Code Review) 11 Sep '17

11 Sep '17

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/21503 Change subject: cpu/intel/car/cache_as_ram.inc: Fix long standing issues ...................................................................... cpu/intel/car/cache_as_ram.inc: Fix long standing issues Do not set %ebp before and switch directly to stack returned by romstage_main(). Remove an unneeded 4-byte gap in CAR stack. The caching strategy for flash XIP area should be WRPROT. Clarify the various comments in the file on the logic. Together they lay the groundwork for bringing EARLY_CBMEM_INIT to intel/slot_1 boards. Change-Id: Ibb6cf6a2adbe3a1f28bf2903d852ddc19e09b484 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/cpu/intel/car/cache_as_ram.inc 1 file changed, 23 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/21503/1 diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 7cf55b3..d208cee 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -22,9 +22,6 @@ #include <cpu/x86/lapic_def.h> #include <cpu/x86/post_code.h> -#define CacheSize CONFIG_DCACHE_RAM_SIZE -#define CacheBase (0xd0000 - CacheSize) - /* Save the BIST result. */ movl %eax, %ebp @@ -128,32 +125,29 @@ */ .endm -#if CacheSize > 0x10000 +#if CONFIG_DCACHE_RAM_SIZE > 0x10000 #error Invalid CAR size, must be at most 64k. #endif -#if CacheSize < 0x1000 +#if CONFIG_DCACHE_RAM_SIZE < 0x1000 #error Invalid CAR size, must be at least 4k. This is a processor limitation. #endif -#if (CacheSize & (0x1000 - 1)) +#if (CONFIG_DCACHE_RAM_SIZE & (0x1000 - 1)) #error Invalid CAR size, is not a multiple of 4k. This is a processor limitation. #endif -#if CacheSize > 0x8000 +#if CONFIG_DCACHE_RAM_SIZE > 0x8000 /* Enable caching for 32K-64K using fixed MTRR. */ movl $MTRR_FIX_4K_C0000, %ecx - simplemask CacheSize, 0x8000 + simplemask CONFIG_DCACHE_RAM_SIZE, 0x8000 wrmsr #endif /* Enable caching for 0-32K using fixed MTRR. */ movl $MTRR_FIX_4K_C8000, %ecx - simplemask CacheSize, 0 + simplemask CONFIG_DCACHE_RAM_SIZE, 0 wrmsr - /* - * Enable write base caching so we can do execute in place (XIP) - * on the flash ROM. - */ + /* Enable cache for our code in Flash because we do XIP here. */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx /* @@ -162,7 +156,7 @@ */ movl $copy_and_run, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax - orl $MTRR_TYPE_WRBACK, %eax + orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx @@ -175,33 +169,31 @@ andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 - /* Read the range with lodsl. */ - movl $CacheBase, %esi + /* Read the CAR region. This will also fill up the cache. + * IMPORTANT: This step is mandatory. + */ + movl $CONFIG_DCACHE_RAM_BASE, %esi cld - movl $(CacheSize >> 2), %ecx + movl $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx rep lodsl - /* Clear the range. */ - movl $CacheBase, %edi - movl $(CacheSize >> 2), %ecx + /* Clear the CAR region. */ + movl $CONFIG_DCACHE_RAM_BASE, %edi + movl $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx xorl %eax, %eax rep stosl - movl $(CacheBase + CacheSize - 4), %eax + movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax movl %eax, %esp lout: /* Restore the BIST result. */ movl %ebp, %eax - /* We need to set EBP? No need. */ - movl %esp, %ebp pushl %eax /* BIST */ call romstage_main - /* Save return value from romstage_main. It contains the stack to use - * after cache-as-ram is torn down. - */ - movl %eax, %ebx + /* Setup stack as indicated by return value from romstage_main(). */ + movl %eax, %esp /* We don't need CAR from now on. */ @@ -210,7 +202,7 @@ orl $CR0_CacheDisable, %eax movl %eax, %cr0 - /* Clear sth. */ + /* Clear the fixed MTRR we used. */ movl $MTRR_FIX_4K_C8000, %ecx xorl %edx, %edx xorl %eax, %eax @@ -222,12 +214,12 @@ #endif /* - * Set the default memory type and disable fixed - * and enable variable MTRRs. + * Enable variable and disable fixed MTRRs. + * Default memory type will be UC. */ movl $MTRR_DEF_TYPE_MSR, %ecx xorl %edx, %edx - movl $MTRR_DEF_TYPE_EN, %eax /* Enable variable and disable fixed MTRRs. */ + movl $MTRR_DEF_TYPE_EN, %eax wrmsr /* Enable cache. */ @@ -238,10 +230,6 @@ __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - - /* Setup stack as indicated by return value from romstage_main(). */ - movl %ebx, %esp - movl %esp, %ebp call copy_and_run .Lhlt: -- To view, visit https://review.coreboot.org/21503 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibb6cf6a2adbe3a1f28bf2903d852ddc19e09b484 Gerrit-Change-Number: 21503 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

1 0

Change in coreboot[master]: cpu/intel/car/cache_as_ram.inc: Remove unused code
by Keith Hui (Code Review) 11 Sep '17

11 Sep '17

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/21502 Change subject: cpu/intel/car/cache_as_ram.inc: Remove unused code ...................................................................... cpu/intel/car/cache_as_ram.inc: Remove unused code Remove CAR testing code currently blocked out by #if. Newer CAR code don't even do it anymore. Change-Id: I2d53b4e7a244824c7aa2c0f597ed91e17f6cc668 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/cpu/intel/car/cache_as_ram.inc 1 file changed, 0 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/21502/1 diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index baa10c0..7cf55b3 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -187,50 +187,6 @@ xorl %eax, %eax rep stosl -#if 0 - /* Check the cache as ram. */ - movl $CacheBase, %esi - movl $(CacheSize >> 2), %ecx -.xin1: - movl %esi, %eax - movl %eax, (%esi) - decl %ecx - je .xout1 - add $4, %esi - jmp .xin1 -.xout1: - - movl $CacheBase, %esi - // movl $(CacheSize >> 2), %ecx - movl $4, %ecx -.xin1x: - movl %esi, %eax - - movl $0x4000, %edx - movb %ah, %al -.testx1: - outb %al, $0x80 - decl %edx - jnz .testx1 - - movl (%esi), %eax - cmpb 0xff, %al - je .xin2 /* Don't show. */ - - movl $0x4000, %edx -.testx2: - outb %al, $0x80 - decl %edx - jnz .testx2 - -.xin2: - decl %ecx - je .xout1x - add $4, %esi - jmp .xin1x -.xout1x: -#endif - movl $(CacheBase + CacheSize - 4), %eax movl %eax, %esp lout: -- To view, visit https://review.coreboot.org/21502 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2d53b4e7a244824c7aa2c0f597ed91e17f6cc668 Gerrit-Change-Number: 21502 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

1 0

Change in coreboot[master]: amd/stoneyridge: Simplify SB link routing
by build bot (Jenkins) (Code Review) 11 Sep '17

11 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21494 ) Change subject: amd/stoneyridge: Simplify SB link routing ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15485/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60261/ : SUCCESS -- To view, visit https://review.coreboot.org/21494 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie4ce6b5aa847a184534224db302437ff8d37c14b Gerrit-Change-Number: 21494 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Sep 2017 22:52:48 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: amd/stoneyridge: Remove multi-node support
by build bot (Jenkins) (Code Review) 11 Sep '17

11 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21495 ) Change subject: amd/stoneyridge: Remove multi-node support ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/60260/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/15486/ : SUCCESS -- To view, visit https://review.coreboot.org/21495 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Gerrit-Change-Number: 21495 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Sep 2017 22:45:37 +0000 Gerrit-HasComments: No

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2017