coreboot-gerrit August 2017

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Change in coreboot[master]: mainboard/intel/cannonlake-u: populate PCI devices
by build bot (Jenkins) (Code Review) 16 Aug '17

16 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21054 ) Change subject: mainboard/intel/cannonlake-u: populate PCI devices ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58665/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14047/ : SUCCESS -- To view, visit https://review.coreboot.org/21054 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id04f5efe77a04c180b5dd392da777195bd9fb7a3 Gerrit-Change-Number: 21054 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Aug 2017 19:43:43 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/intel/cannonlake-y: populate PCI devices
by build bot (Jenkins) (Code Review) 16 Aug '17

16 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21055 ) Change subject: mainboard/intel/cannonlake-y: populate PCI devices ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58666/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14048/ : SUCCESS -- To view, visit https://review.coreboot.org/21055 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I311437798274dd48b0898f0832bf03d86fd9d3a6 Gerrit-Change-Number: 21055 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Aug 2017 19:27:56 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/intel/cannonlake-y: populate PCI devices
by Pratikkumar V Prajapati (Code Review) 16 Aug '17

16 Aug '17

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21055 Change subject: mainboard/intel/cannonlake-y: populate PCI devices ...................................................................... mainboard/intel/cannonlake-y: populate PCI devices Define and populate PCI devices in devicetree for CNL-Y RVP Change-Id: I311437798274dd48b0898f0832bf03d86fd9d3a6 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb 1 file changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/21055/1 diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index c7001a4..e71f15b 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -5,5 +5,57 @@ end device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.5 on end # SDCard + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 on end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 on end # eMMC + device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 + device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE end end -- To view, visit https://review.coreboot.org/21055 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I311437798274dd48b0898f0832bf03d86fd9d3a6 Gerrit-Change-Number: 21055 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: intel/cannonlake/chip: Add initial PCI enum support
by build bot (Jenkins) (Code Review) 16 Aug '17

16 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21053 ) Change subject: intel/cannonlake/chip: Add initial PCI enum support ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58664/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14046/ : SUCCESS -- To view, visit https://review.coreboot.org/21053 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia8a51973aa2b805d62590114bfc49968244b1668 Gerrit-Change-Number: 21053 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Aug 2017 19:07:50 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/intel/cannonlake-u: populate PCI devices
by Pratikkumar V Prajapati (Code Review) 16 Aug '17

16 Aug '17

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21054 Change subject: mainboard/intel/cannonlake-u: populate PCI devices ...................................................................... mainboard/intel/cannonlake-u: populate PCI devices Define and populate PCI devices in devicetree for CNL-U RVP Change-Id: Id04f5efe77a04c180b5dd392da777195bd9fb7a3 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb 1 file changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/21054/1 diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index c7001a4..e71f15b 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -5,5 +5,57 @@ end device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.5 on end # SDCard + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 on end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 on end # eMMC + device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 + device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE end end -- To view, visit https://review.coreboot.org/21054 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id04f5efe77a04c180b5dd392da777195bd9fb7a3 Gerrit-Change-Number: 21054 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: intel/cannonlake/chip: Add initial PCI enum support
by Pratikkumar V Prajapati (Code Review) 16 Aug '17

16 Aug '17

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21053 Change subject: intel/cannonlake/chip: Add initial PCI enum support ...................................................................... intel/cannonlake/chip: Add initial PCI enum support Add callbacks for initial PCI devices enumeration. Change-Id: Ia8a51973aa2b805d62590114bfc49968244b1668 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/cannonlake/chip.c 1 file changed, 30 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/21053/1 diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 2f893e3..62181a3 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -15,8 +15,8 @@ #include <chip.h> #include <console/console.h> +#include <device/device.h> #include <device/pci.h> -#include <fsp/api.h> #include <fsp/api.h> #include <fsp/util.h> #include <romstage_handoff.h> @@ -29,8 +29,37 @@ fsp_silicon_init(romstage_handoff_is_resume()); } +static void pci_domain_set_resources(device_t dev) +{ + assign_resources(dev->link_list); +} + +static struct device_operations pci_domain_ops = { + .read_resources = &pci_domain_read_resources, + .set_resources = &pci_domain_set_resources, + .scan_bus = &pci_domain_scan_bus, + .ops_pci_bus = &pci_bus_default_ops, +}; + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = DEVICE_NOOP, +}; + +static void soc_enable(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) + dev->ops = &pci_domain_ops; + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) + dev->ops = &cpu_bus_ops; +} + struct chip_operations soc_intel_cannonlake_ops = { CHIP_NAME("Intel Cannonlake") + .enable_dev = &soc_enable, .init = &soc_init_pre_device, }; -- To view, visit https://review.coreboot.org/21053 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia8a51973aa2b805d62590114bfc49968244b1668 Gerrit-Change-Number: 21053 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: mainboard/lenovo: add Lenovo Z61m laptop
by build bot (Jenkins) (Code Review) 16 Aug '17

16 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21019 ) Change subject: mainboard/lenovo: add Lenovo Z61m laptop ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58663/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14045/ : SUCCESS -- To view, visit https://review.coreboot.org/21019 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I84c89cc47d3db126d827f92d50270954bc42f224 Gerrit-Change-Number: 21019 Gerrit-PatchSet: 4 Gerrit-Owner: Andrey Korolyov <andrey(a)xdel.ru> Gerrit-Reviewer: Andrey Korolyov <andrey(a)xdel.ru> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Aug 2017 18:55:01 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: lint: update signed-off-by check
by build bot (Jenkins) (Code Review) 16 Aug '17

16 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20920 ) Change subject: lint: update signed-off-by check ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58662/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14044/ : SUCCESS -- To view, visit https://review.coreboot.org/20920 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8be8aef25730d988c7cf1586ae66ecb839d5f756 Gerrit-Change-Number: 20920 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Chris Ching <chingcodes(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Aug 2017 18:27:15 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: util/kbc1126: [cosmetic] change Makefile casing
by Idwer Vollering (Code Review) 16 Aug '17

16 Aug '17

Idwer Vollering has submitted this change and it was merged. ( https://review.coreboot.org/21050 ) Change subject: util/kbc1126: [cosmetic] change Makefile casing ...................................................................... util/kbc1126: [cosmetic] change Makefile casing Change-Id: Iac616fdb3de79f4f58c30a2eb674ed5152b6a6e4 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> Reviewed-on: https://review.coreboot.org/21050 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- R util/kbc1126/Makefile 1 file changed, 0 insertions(+), 0 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/kbc1126/makefile b/util/kbc1126/Makefile similarity index 100% rename from util/kbc1126/makefile rename to util/kbc1126/Makefile -- To view, visit https://review.coreboot.org/21050 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Iac616fdb3de79f4f58c30a2eb674ed5152b6a6e4 Gerrit-Change-Number: 21050 Gerrit-PatchSet: 2 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/common/block: Add functions to common CPU library code
by build bot (Jenkins) (Code Review) 16 Aug '17

16 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21051 ) Change subject: soc/intel/common/block: Add functions to common CPU library code ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58660/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14043/ : SUCCESS -- To view, visit https://review.coreboot.org/21051 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id34eb7e03069656238ca0cbdf6ce33f116e0e413 Gerrit-Change-Number: 21051 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Aug 2017 17:05:24 +0000 Gerrit-HasComments: No

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coreboot-gerrit August 2017