coreboot-gerrit August 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/skylake: Move LPC lock down config after PCI enumeration
by build bot (Jenkins) (Code Review) 17 Aug '17

17 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21000 ) Change subject: soc/intel/skylake: Move LPC lock down config after PCI enumeration ...................................................................... Patch Set 5: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58735/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/14110/ : SUCCESS -- To view, visit https://review.coreboot.org/21000 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee Gerrit-Change-Number: 21000 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Thu, 17 Aug 2017 11:34:12 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Move DMI lock down config after PCI enumeration
by build bot (Jenkins) (Code Review) 17 Aug '17

17 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21030 ) Change subject: soc/intel/skylake: Move DMI lock down config after PCI enumeration ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58736/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/14111/ : SUCCESS -- To view, visit https://review.coreboot.org/21030 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie66701d5bd8c8f389e23fb30c8595dd83cf6b1ae Gerrit-Change-Number: 21030 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Aug 2017 11:33:59 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Move PMC lock down config after PCI enumeration
by build bot (Jenkins) (Code Review) 17 Aug '17

17 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21029 ) Change subject: soc/intel/skylake: Move PMC lock down config after PCI enumeration ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58737/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/14112/ : SUCCESS -- To view, visit https://review.coreboot.org/21029 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibd86a38fa78752ce007da63a9ccdd991ca21ab92 Gerrit-Change-Number: 21029 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Thu, 17 Aug 2017 11:33:42 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboards: Enable LPC and SPI lock down
by Subrata Banik (Code Review) 17 Aug '17

17 Aug '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21069 Change subject: mainboards: Enable LPC and SPI lock down ...................................................................... mainboards: Enable LPC and SPI lock down This patch is to enable LPC and SPI lock down configuration from coreboot. Change-Id: I42bd02c261501ac35f081afb01ecf067aa90d8e2 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/google/chell/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/lars/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/purism/librem13v2/devicetree.cb 11 files changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/21069/1 diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index 4d4d0af..172dabd 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -190,6 +190,10 @@ # Send an extra VR mailbox command for the supported MPS IMVP8 model register "SendVrMbxCmd" = "1" + # Lock Down + register "lpc_lockdown" = "1" + register "spi_lockdown" = "1" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index b6cb848..d97b6ea 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -218,6 +218,10 @@ register "tdp_pl2_override" = "15" register "tcc_offset" = "10" + # Lock Down + register "lpc_lockdown" = "1" + register "spi_lockdown" = "1" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index bf9f0c9..a40519b 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -216,6 +216,10 @@ # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_A7" + # Lock Down + register "lpc_lockdown" = "1" + register "spi_lockdown" = "1" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index d4155ea..bff0503 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -188,6 +188,10 @@ # Send an extra VR mailbox command for the supported MPS IMVP8 model register "SendVrMbxCmd" = "1" + # Lock Down + register "lpc_lockdown" = "1" + register "spi_lockdown" = "1" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index ed1de93..d9e18fb 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -184,6 +184,10 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" + # Lock Down + register "lpc_lockdown" = "1" + register "spi_lockdown" = "1" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index f10db59..995e2c3 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -199,6 +199,10 @@ # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_E15" + # Lock Down + register "lpc_lockdown" = "1" + register "spi_lockdown" = "1" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index b874093..a0e72fb 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -208,6 +208,10 @@ # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_E15" + # Lock Down + register "lpc_lockdown" = "1" + register "spi_lockdown" = "1" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb index c1974ad..50d6c77 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb @@ -205,6 +205,10 @@ # Enable/Disable VMX feature register "VmxEnable" = "0" + # Lock Down + register "lpc_lockdown" = "1" + register "spi_lockdown" = "1" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb index a56345c..0ae6f35 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb @@ -200,6 +200,10 @@ # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_G5" + # Lock Down + register "lpc_lockdown" = "1" + register "spi_lockdown" = "1" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 17e8e27..8e94597 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -194,6 +194,10 @@ # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_A7" + # Lock Down + register "lpc_lockdown" = "1" + register "spi_lockdown" = "1" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb index e113b3f..957beee 100644 --- a/src/mainboard/purism/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem13v2/devicetree.cb @@ -171,6 +171,10 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" + # Lock Down + register "lpc_lockdown" = "1" + register "spi_lockdown" = "1" + device cpu_cluster 0 on device lapic 0 on end end -- To view, visit https://review.coreboot.org/21069 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I42bd02c261501ac35f081afb01ecf067aa90d8e2 Gerrit-Change-Number: 21069 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Add LPC and SPI lock down config option
by Subrata Banik (Code Review) 17 Aug '17

17 Aug '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21068 Change subject: soc/intel/skylake: Add LPC and SPI lock down config option ...................................................................... soc/intel/skylake: Add LPC and SPI lock down config option This patch to provide new config options to perform LPC and SPI lock down. Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/chip.h 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/21068/1 diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index efd3566..67ccec8 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -501,6 +501,16 @@ * end of POST for security concerns. */ u8 SpiFlashCfgLockDown; + /* LPC Lock Down + * 1b - Coreboot to handle lockdown + * 0b - FSP to handle lockdown + */ + u8 lpc_lockdown; + /* SPI Lock Down + * 1b - Coreboot to handle lockdown + * 0b - FSP to handle lockdown + */ + u8 spi_lockdown; }; typedef struct soc_intel_skylake_config config_t; -- To view, visit https://review.coreboot.org/21068 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc Gerrit-Change-Number: 21068 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: google/snappy: Add MELFAS touch screen support
by build bot (Jenkins) (Code Review) 17 Aug '17

17 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21067 ) Change subject: google/snappy: Add MELFAS touch screen support ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58734/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14109/ : SUCCESS -- To view, visit https://review.coreboot.org/21067 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If2bc910d641e0cf2b120ed883c5788542959f568 Gerrit-Change-Number: 21067 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Keith Tzeng <keith.tzeng(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Aug 2017 10:58:56 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/snappy: Add MELFAS touch screen support
by build bot (Jenkins) (Code Review) 17 Aug '17

17 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21067 ) Change subject: google/snappy: Add MELFAS touch screen support ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58733/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/14108/ : SUCCESS -- To view, visit https://review.coreboot.org/21067 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If2bc910d641e0cf2b120ed883c5788542959f568 Gerrit-Change-Number: 21067 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Keith Tzeng <keith.tzeng(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Aug 2017 10:51:58 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/snappy: Add MELFAS touch screen support
by Kevin Chiu (Code Review) 17 Aug '17

17 Aug '17

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/21067 Change subject: google/snappy: Add MELFAS touch screen support ...................................................................... google/snappy: Add MELFAS touch screen support Current fw does not create ACPI device for OS to recognize MELFAS touchscreen. List the touch screen in the devicetree so that the correct ACPI device are created. BUG=b:64779224 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: If2bc910d641e0cf2b120ed883c5788542959f568 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/reef/variants/snappy/devicetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/21067/1 diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index d888896..e0182dd 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -193,6 +193,13 @@ register "has_power_resource" = "1" device i2c 10 on end end + chip drivers/i2c/generic + register "hid" = ""MLFS0000"" + register "desc" = ""Melfas Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "probed" = "1" + device i2c 34 on end + end chip drivers/i2c/hid register "generic.hid" = ""WDHT0002"" register "generic.desc" = ""WDT Touchscreen"" -- To view, visit https://review.coreboot.org/21067 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If2bc910d641e0cf2b120ed883c5788542959f568 Gerrit-Change-Number: 21067 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com>

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Change in coreboot[master]: soc/intel/skylake: Move SPI lock down config after PCI enumeration
by Subrata Banik (Code Review) 17 Aug '17

17 Aug '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/21064 ) Change subject: soc/intel/skylake: Move SPI lock down config after PCI enumeration ...................................................................... Patch Set 1: (3 comments) https://review.coreboot.org/#/c/21064/1/src/soc/intel/skylake/finalize.c File src/soc/intel/skylake/finalize.c: https://review.coreboot.org/#/c/21064/1/src/soc/intel/skylake/finalize.c@128 PS1, Line 128: const struct device *dev1 = dev_find_slot(0, PCH_DEVFN_LPC); remove this and use "dev" itself now. dev = PCH_DEV_PMC const struct soc_intel_skylake_config *config = dev->chip_info; https://review.coreboot.org/#/c/21064/1/src/soc/intel/skylake/finalize.c@133 PS1, Line 133: dev = PCH_DEV_PMC; remove this https://review.coreboot.org/#/c/21064/1/src/soc/intel/skylake/lockdown.c File src/soc/intel/skylake/lockdown.c: https://review.coreboot.org/#/c/21064/1/src/soc/intel/skylake/lockdown.c@104 PS1, Line 104: /* Bios Interface Lock */ : if (config->LockDownConfigBiosInterface == 0) : fast_spi_set_bios_interface_lock_down(); : : /* Bios Lock */ : if (config->LockDownConfigBiosLock == 0) : fast_spi_set_lock_enable(); : : /* SPIEiss */ : if (config->LockDownConfigSpiEiss == 0) : fast_spi_set_eiss(); i'm going to use new name config like spilockdown and lpclockdown to make all lockdown under a single -- To view, visit https://review.coreboot.org/21064 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8f5a952656e51d3bf365917b90d3056b46f899c5 Gerrit-Change-Number: 21064 Gerrit-PatchSet: 1 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Aug 2017 09:24:07 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/skylake: Add support for all UART port index
by build bot (Jenkins) (Code Review) 17 Aug '17

17 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20997 ) Change subject: soc/intel/skylake: Add support for all UART port index ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58730/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14105/ : SUCCESS -- To view, visit https://review.coreboot.org/20997 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I306d3d299f8d6a890ae519c74008f9d0d9dd1a76 Gerrit-Change-Number: 20997 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Thu, 17 Aug 2017 09:15:35 +0000 Gerrit-HasComments: No

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coreboot-gerrit August 2017