coreboot-gerrit August 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/skylake: Remove TCO lock down programming
by build bot (Jenkins) (Code Review) 17 Aug '17

17 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21031 ) Change subject: soc/intel/skylake: Remove TCO lock down programming ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58725/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14100/ : SUCCESS -- To view, visit https://review.coreboot.org/21031 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iec9e3075df01862f8558b303a458126c68202bff Gerrit-Change-Number: 21031 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Aug 2017 06:44:43 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Move DMI lock down config after PCI enumeration
by build bot (Jenkins) (Code Review) 17 Aug '17

17 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21030 ) Change subject: soc/intel/skylake: Move DMI lock down config after PCI enumeration ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58723/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14098/ : SUCCESS -- To view, visit https://review.coreboot.org/21030 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie66701d5bd8c8f389e23fb30c8595dd83cf6b1ae Gerrit-Change-Number: 21030 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Aug 2017 06:42:43 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Move LPC lock down config after PCI enumeration
by build bot (Jenkins) (Code Review) 17 Aug '17

17 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21000 ) Change subject: soc/intel/skylake: Move LPC lock down config after PCI enumeration ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58721/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14096/ : SUCCESS -- To view, visit https://review.coreboot.org/21000 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee Gerrit-Change-Number: 21000 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Thu, 17 Aug 2017 06:42:02 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Move PMC lock down config after PCI enumeration
by build bot (Jenkins) (Code Review) 17 Aug '17

17 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21029 ) Change subject: soc/intel/skylake: Move PMC lock down config after PCI enumeration ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58722/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14097/ : SUCCESS -- To view, visit https://review.coreboot.org/21029 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibd86a38fa78752ce007da63a9ccdd991ca21ab92 Gerrit-Change-Number: 21029 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Thu, 17 Aug 2017 06:41:26 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/common/mrc_cache: Move update_mrc_cache after BS_DEV_RESOURCES
by build bot (Jenkins) (Code Review) 17 Aug '17

17 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21028 ) Change subject: intel/common/mrc_cache: Move update_mrc_cache after BS_DEV_RESOURCES ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58720/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14095/ : SUCCESS -- To view, visit https://review.coreboot.org/21028 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8ee26b5cc70433438cf4e45e707b8a54f89cf9b0 Gerrit-Change-Number: 21028 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Thu, 17 Aug 2017 06:40:09 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: common/block/fast_spi: Add function to DLOCK PR registers
by build bot (Jenkins) (Code Review) 17 Aug '17

17 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21063 ) Change subject: common/block/fast_spi: Add function to DLOCK PR registers ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58724/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14099/ : SUCCESS -- To view, visit https://review.coreboot.org/21063 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I46e1948315ea9489932efdf7d60d6d78ab3948a6 Gerrit-Change-Number: 21063 Gerrit-PatchSet: 1 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Aug 2017 06:39:27 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Move SPI lock down config after PCI enumeration
by Barnali Sarkar (Code Review) 17 Aug '17

17 Aug '17

Barnali Sarkar has uploaded this change for review. ( https://review.coreboot.org/21064 Change subject: soc/intel/skylake: Move SPI lock down config after PCI enumeration ...................................................................... soc/intel/skylake: Move SPI lock down config after PCI enumeration This patch to ensures that coreboot is meeting Intel Silicon recommendation to performing register lockdown. TEST=Ensure SPIBAR+HSFSTS(0x04) register FLOCKDN bit and WRSDIS bit is set. Also, Bits 8-12 of SPIBAR+DLOCK(0x0C) register is set. Change-Id: I8f5a952656e51d3bf365917b90d3056b46f899c5 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/lockdown.c 2 files changed, 38 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/21064/1 diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index aed7e87..42d67ec 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -21,7 +21,6 @@ #include <console/post_codes.h> #include <cpu/x86/smm.h> #include <device/pci.h> -#include <intelblocks/fast_spi.h> #include <intelblocks/pcr.h> #include <reg_script.h> #include <spi-generic.h> @@ -90,12 +89,6 @@ config_t *config; u8 reg8; - /* Set FAST_SPI opcode menu */ - fast_spi_set_opcode_menu(); - - /* Lock FAST_SPIBAR */ - fast_spi_lock_bar(); - /* Display me status before we hide it */ intel_me_status(); @@ -142,18 +135,6 @@ reg8 |= SMI_LOCK; pci_write_config8(dev, GEN_PMCON_A, reg8); } - - /* Bios Interface Lock */ - if (config->LockDownConfigBiosInterface == 0) - fast_spi_set_bios_interface_lock_down(); - - /* Bios Lock */ - if (config->LockDownConfigBiosLock == 0) - fast_spi_set_lock_enable(); - - /* SPIEiss */ - if (config->LockDownConfigSpiEiss == 0) - fast_spi_set_eiss(); } static void soc_finalize(void *unused) diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c index e31cf09..cddb87b 100644 --- a/src/soc/intel/skylake/lockdown.c +++ b/src/soc/intel/skylake/lockdown.c @@ -17,6 +17,7 @@ #include <bootstate.h> #include <chip.h> #include <console/console.h> +#include <intelblocks/fast_spi.h> #include <intelblocks/pcr.h> #include <soc/lpc.h> #include <soc/pci_devs.h> @@ -79,6 +80,40 @@ pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); } +static void spi_lockdown_config(void) +{ + static struct soc_intel_skylake_config *config; + struct device *dev; + + /* Set FAST_SPI opcode menu */ + fast_spi_set_opcode_menu(); + + /* Discrete Lock Flash PR registers */ + fast_spi_pr_dlock(); + + /* Lock FAST_SPIBAR */ + fast_spi_lock_bar(); + + dev = PCH_DEV_SPI; + /* Check if SPI is enabled, else return */ + if (dev == NULL || dev->chip_info == NULL) + return; + + config = dev->chip_info; + + /* Bios Interface Lock */ + if (config->LockDownConfigBiosInterface == 0) + fast_spi_set_bios_interface_lock_down(); + + /* Bios Lock */ + if (config->LockDownConfigBiosLock == 0) + fast_spi_set_lock_enable(); + + /* SPIEiss */ + if (config->LockDownConfigSpiEiss == 0) + fast_spi_set_eiss(); +} + static void platform_lockdown_config(void *unused) { /* LPC lock down configuration */ @@ -89,6 +124,9 @@ /* DMI lock down configuration */ dmi_lockdown_config(); + + /* SPI lock down configuration */ + spi_lockdown_config(); } BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config, -- To view, visit https://review.coreboot.org/21064 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8f5a952656e51d3bf365917b90d3056b46f899c5 Gerrit-Change-Number: 21064 Gerrit-PatchSet: 1 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com>

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Change in coreboot[master]: common/block/fast_spi: Add function to DLOCK PR registers
by Barnali Sarkar (Code Review) 17 Aug '17

17 Aug '17

Barnali Sarkar has uploaded this change for review. ( https://review.coreboot.org/21063 Change subject: common/block/fast_spi: Add function to DLOCK PR registers ...................................................................... common/block/fast_spi: Add function to DLOCK PR registers Add a function in FAST_SPI library to discrete lock the PR registers 0 to 4. BUG=none BRANCH=none TEST=Build and boot poppy Change-Id: I46e1948315ea9489932efdf7d60d6d78ab3948a6 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/include/intelblocks/fast_spi.h 3 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/21063/1 diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index fe0217a..dbb25d7 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -149,6 +149,23 @@ write16(spibar + SPIBAR_HSFSTS_CTL, hsfs); } +/*. + * Set FAST_SPIBAR + DLOCK (0x0C) register bits to discrete lock the + * FAST_SPI Protected Range (PR) registers. + */ +void fast_spi_pr_dlock(void) +{ + void *spibar = fast_spi_get_bar(); + uint32_t dlock; + + dlock = read32(spibar + SPIBAR_DLOCK); + dlock |= (SPIBAR_DLOCK_PR0LOCKDN | SPIBAR_DLOCK_PR1LOCKDN + | SPIBAR_DLOCK_PR2LOCKDN | SPIBAR_DLOCK_PR3LOCKDN + | SPIBAR_DLOCK_PR4LOCKDN); + + write32(spibar + SPIBAR_DLOCK, dlock); +} + /* * Set FAST_SPIBAR Soft Reset Data Register value. */ diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index 8e06df2..5b83265 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -34,6 +34,7 @@ #define SPIBAR_BFPREG 0x00 #define SPIBAR_HSFSTS_CTL 0x04 #define SPIBAR_FADDR 0x08 +#define SPIBAR_DLOCK 0x0c #define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4) #define SPIBAR_FPR_BASE 0x84 #define SPIBAR_FPR(n) 0x84 + (4 * n)) @@ -87,6 +88,13 @@ /* Bit definitions for FADDR (0x08) register */ #define SPIBAR_FADDR_MASK 0x7FFFFFF +/* Bit definitions for DLOCK (0x0C) register */ +#define SPIBAR_DLOCK_PR0LOCKDN (1 << 8) +#define SPIBAR_DLOCK_PR1LOCKDN (1 << 9) +#define SPIBAR_DLOCK_PR2LOCKDN (1 << 10) +#define SPIBAR_DLOCK_PR3LOCKDN (1 << 11) +#define SPIBAR_DLOCK_PR4LOCKDN (1 << 12) + /* Maximum bytes of data that can fit in FDATAn (0x10) registers */ #define SPIBAR_FDATA_FIFO_SIZE 0x40 diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index b399e4d..e93c546 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -48,6 +48,11 @@ * Lock FAST_SPIBAR. */ void fast_spi_lock_bar(void); +/*. + * Set FAST_SPIBAR + DLOCK (0x0C) register bits to discrete lock the + * FAST_SPI Protected Range (PR) registers. + */ +void fast_spi_pr_dlock(void); /* * Set FAST_SPIBAR Soft Reset Data Register value. */ -- To view, visit https://review.coreboot.org/21063 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I46e1948315ea9489932efdf7d60d6d78ab3948a6 Gerrit-Change-Number: 21063 Gerrit-PatchSet: 1 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Add SPI flash controller driver
by build bot (Jenkins) (Code Review) 17 Aug '17

17 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21052 ) Change subject: soc/intel/cannonlake: Add SPI flash controller driver ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58717/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14094/ : SUCCESS -- To view, visit https://review.coreboot.org/21052 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie45146721f39d3cec20ff5136adf8925c75da1cd Gerrit-Change-Number: 21052 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Aug 2017 03:54:22 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add SPI flash controller driver
by Lijian Zhao (Code Review) 17 Aug '17

17 Aug '17

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/21052 Change subject: soc/intel/cannonlake: Add SPI flash controller driver ...................................................................... soc/intel/cannonlake: Add SPI flash controller driver Add SPI driver code for the SPI flash controller, including both fast_spi and generic_spi. Change-Id: Ie45146721f39d3cec20ff5136adf8925c75da1cd Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/chip.h A src/soc/intel/cannonlake/gspi.c M src/soc/intel/cannonlake/include/soc/pci_devs.h A src/soc/intel/cannonlake/spi.c 6 files changed, 163 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/21052/4 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 311cfb8..1b6759c 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -11,6 +11,8 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH + select BOOT_DEVICE_SUPPORTS_WRITES select C_ENVIRONMENT_BOOTBLOCK select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select HAVE_HARD_RESET @@ -29,6 +31,7 @@ select SOC_INTEL_COMMON_BLOCK_CSE select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO + select SOC_INTEL_COMMON_BLOCK_GSPI select SOC_INTEL_COMMON_BLOCK_LPSS select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_RTC @@ -38,6 +41,7 @@ select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_UART + select SOC_INTEL_COMMON_SPI_FLASH_PROTECT select SOC_INTEL_COMMON_RESET select SUPPORT_CPU_UCODE_IN_CBFS select TSC_CONSTANT_RATE @@ -78,6 +82,11 @@ int default 100 + +config SOC_INTEL_COMMON_BLOCK_GSPI_MAX + int + default 3 + # Clock divider parameters for 115200 baud rate config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 297d34f..8a83eb0 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -11,20 +11,27 @@ bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += gpio.c +bootblock-y += gspi.c bootblock-y += memmap.c +bootblock-y += spi.c bootblock-$(CONFIG_UART_DEBUG) += uart.c +romstage-y += gspi.c romstage-y += memmap.c romstage-y += reset.c +romstage-y += spi.c romstage-$(CONFIG_UART_DEBUG) += uart.c ramstage-y += chip.c +ramstage-y += gspi.c ramstage-y += memmap.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c +ramstage-y += spi.c ramstage-y += systemagent.c ramstage-$(CONFIG_UART_DEBUG) += uart.c postcar-y += memmap.c +postcar-y += spi.c postcar-$(CONFIG_UART_DEBUG) += uart.c CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index bbc5880..67be85d 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -18,9 +18,12 @@ #ifndef _SOC_CHIP_H_ #define _SOC_CHIP_H_ +#include <intelblocks/gspi.h> #include <stdint.h> struct soc_intel_cannonlake_config { + /* GSPI */ + struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/gspi.c b/src/soc/intel/cannonlake/gspi.c new file mode 100644 index 0000000..a1ebfba --- /dev/null +++ b/src/soc/intel/cannonlake/gspi.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <device/device.h> +#include <intelblocks/gspi.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include "chip.h" + +const struct gspi_cfg *gspi_get_soc_cfg(void) +{ + DEVTREE_CONST struct soc_intel_cannonlake_config *config; + int devfn = SA_DEVFN_ROOT; + DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn); + + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", + __func__); + return NULL; + } + + config = dev->chip_info; + + return &config->gspi[0]; +} + +uintptr_t gspi_get_soc_early_base(void) +{ + return EARLY_GSPI_BASE_ADDRESS; +} + +/* + * SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust + * the bus # accordingly when referring to SPI / GSPI bus numbers. + */ +#define GSPI_TO_SPI_BUS(x) ((x) + 1) +#define SPI_TO_GSPI_BUS(x) ((x) - 1) + +int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus) +{ + if (spi_bus == 0) + return -1; + + *gspi_bus = SPI_TO_GSPI_BUS(spi_bus); + if (*gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX) + return -1; + + return 0; +} + +int gspi_soc_bus_to_devfn(unsigned int gspi_bus) +{ + if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX) + return -1; + + return spi_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus)); +} diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index f00ea1f..ed6b670 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -173,6 +173,7 @@ case PCH_DEVFN_SPI: return 0; case PCH_DEVFN_GSPI0: return 1; case PCH_DEVFN_GSPI1: return 2; + case PCH_DEVFN_GSPI2: return 3; } return -1; } @@ -183,6 +184,7 @@ case 0: return PCH_DEVFN_SPI; case 1: return PCH_DEVFN_GSPI0; case 2: return PCH_DEVFN_GSPI1; + case 3: return PCH_DEVFN_GSPI2; } return -1; } diff --git a/src/soc/intel/cannonlake/spi.c b/src/soc/intel/cannonlake/spi.c new file mode 100644 index 0000000..1d65dee --- /dev/null +++ b/src/soc/intel/cannonlake/spi.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/spi.h> +#include <intelblocks/fast_spi.h> +#include <intelblocks/gspi.h> +#include <soc/ramstage.h> +#include <soc/pci_devs.h> +#include <spi-generic.h> + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 }, +#if !ENV_SMM + { .ctrlr = &gspi_ctrlr, .bus_start = 1, + .bus_end = 1 + (CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX - 1)}, +#endif +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); + +#if ENV_RAMSTAGE + +static int spi_dev_to_bus(struct device *dev) +{ + return spi_devfn_to_bus(dev->path.pci.devfn); +} + +static struct spi_bus_operations spi_bus_ops = { + .dev_to_bus = &spi_dev_to_bus, +}; + +static struct device_operations spi_dev_ops = { + .read_resources = &pci_dev_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .scan_bus = &scan_generic_bus, + .ops_spi_bus = &spi_bus_ops, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI, + PCI_DEVICE_ID_INTEL_CNL_SPI0, + PCI_DEVICE_ID_INTEL_CNL_SPI1, + PCI_DEVICE_ID_INTEL_CNL_SPI2, + 0 +}; + +static const struct pci_driver pch_spi __pci_driver = { + .ops = &spi_dev_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; +#endif -- To view, visit https://review.coreboot.org/21052 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie45146721f39d3cec20ff5136adf8925c75da1cd Gerrit-Change-Number: 21052 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit August 2017