coreboot-gerrit July 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: google/fizz: Override PL2 and SysPL2 values
by build bot (Jenkins) (Code Review) 11 Jul '17

11 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20420 ) Change subject: google/fizz: Override PL2 and SysPL2 values ...................................................................... Patch Set 4: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/56864/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/12411/ : SUCCESS -- To view, visit https://review.coreboot.org/20420 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5c46667fdae9d8eed5346a481753bb69f98a071b Gerrit-Change-Number: 20420 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Jul 2017 21:15:22 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: libpayload: Support unaligned pointer for memcpy, memmove an...
by build bot (Jenkins) (Code Review) 11 Jul '17

11 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20535 ) Change subject: libpayload: Support unaligned pointer for memcpy, memmove and memcmp ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56862/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12409/ : SUCCESS -- To view, visit https://review.coreboot.org/20535 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0b668739b7b58d47266f10f2dff2dc9cbf38577e Gerrit-Change-Number: 20535 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Jul 2017 21:11:28 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: libpayload: Support unaligned pointer for memcpy, memmove an...
by Jérémy Compostella (Code Review) 11 Jul '17

11 Jul '17

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/20535 Change subject: libpayload: Support unaligned pointer for memcpy, memmove and memcmp ...................................................................... libpayload: Support unaligned pointer for memcpy, memmove and memcmp The memcpy(), memmove() and memcmp() functions use word by word operations regardless of the pointer alignment. Depending on the platform, this could lead to a crash. This patch makes the memcpy(), memmove() or memcmp() operate byte per byte if they are supplied with unaligned pointers. Change-Id: I0b668739b7b58d47266f10f2dff2dc9cbf38577e Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M payloads/libpayload/libc/memory.c 1 file changed, 20 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/20535/1 diff --git a/payloads/libpayload/libc/memory.c b/payloads/libpayload/libc/memory.c index 1adfb32..78418ba 100644 --- a/payloads/libpayload/libc/memory.c +++ b/payloads/libpayload/libc/memory.c @@ -66,13 +66,19 @@ size_t i; void *ret = dst; + if (!IS_ALIGNED((uintptr_t)dst, sizeof(unsigned long)) || + !IS_ALIGNED((uintptr_t)src, sizeof(unsigned long))) + goto copy_bytes; + for(i = 0; i < n / sizeof(unsigned long); i++) ((unsigned long *)dst)[i] = ((unsigned long *)src)[i]; src += i * sizeof(unsigned long); dst += i * sizeof(unsigned long); + n -= i * sizeof(unsigned long); - for(i = 0; i < n % sizeof(unsigned long); i++) +copy_bytes: + for(i = 0; i < n ; i++) ((u8 *)dst)[i] = ((u8 *)src)[i]; return ret; @@ -88,6 +94,13 @@ if (src > dst) return memcpy(dst, src, n); + + if (!IS_ALIGNED((uintptr_t)dst, sizeof(unsigned long)) || + !IS_ALIGNED((uintptr_t)src, sizeof(unsigned long))) { + for (i = n - 1; i >= 0; i--) + ((u8 *)dst)[i] = ((u8 *)src)[i]; + return dst; + } offs = n - (n % sizeof(unsigned long)); @@ -116,12 +129,17 @@ static int default_memcmp(const void *s1, const void *s2, size_t n) { - size_t i; + size_t i = 0; + + if (!IS_ALIGNED((uintptr_t)s1, sizeof(unsigned long)) || + !IS_ALIGNED((uintptr_t)s2, sizeof(unsigned long))) + goto compare_bytes; for (i = 0; i < n / sizeof(unsigned long); i++) if (((unsigned long *)s1)[i] != ((unsigned long *)s2)[i]) break; /* fall through to find differing byte */ +compare_bytes: for (i *= sizeof(unsigned long); i < n; i++) if (((u8 *)s1)[i] != ((u8 *)s2)[i]) return ((u8 *)s1)[i] - ((u8 *)s2)[i]; -- To view, visit https://review.coreboot.org/20535 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0b668739b7b58d47266f10f2dff2dc9cbf38577e Gerrit-Change-Number: 20535 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)gmail.com>

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Change in coreboot[master]: soc/intel/cannonlake: Add postcar stage support
by build bot (Jenkins) (Code Review) 11 Jul '17

11 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20534 ) Change subject: soc/intel/cannonlake: Add postcar stage support ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/56860/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/12407/ : SUCCESS -- To view, visit https://review.coreboot.org/20534 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079 Gerrit-Change-Number: 20534 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Jul 2017 19:57:44 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add postcar stage support
by Lijian Zhao (Code Review) 11 Jul '17

11 Jul '17

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/20534 Change subject: soc/intel/cannonlake: Add postcar stage support ...................................................................... soc/intel/cannonlake: Add postcar stage support Initilize postcar frame once finish FSP memoryinit Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/drivers/intel/fsp2_0/Makefile.inc M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/romstage/romstage.c 4 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/20534/1 diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index cdf6146..d5709ad 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -43,6 +43,7 @@ postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c postcar-$(CONFIG_FSP_CAR) += util.c postcar-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c +postcar-y += hand_off_block.c CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 2c60309..54abba0 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -23,6 +23,8 @@ select HAVE_INTEL_FIRMWARE select INTEL_CAR_NEM_ENHANCED select PLATFORM_USES_FSP2_0 + select POSTCAR_CONSOLE + select POSTCAR_STAGE select SOC_INTEL_COMMON select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index b0fe57f..a5cb463 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -20,6 +20,9 @@ ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c +postcar-y += memmap.c +postcar-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c + CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20 CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cannonlake diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 5a860a2..8144b3a 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -14,6 +14,10 @@ */ #include <arch/io.h> +#include <arch/symbols.h> +#include <assert.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> #include <cbmem.h> #include <console/console.h> #include <fsp/util.h> @@ -22,9 +26,17 @@ #include <soc/romstage.h> #include <timestamp.h> +/* + * Romstage needs some stack for decompressing ramstage images, since the lzma + * lib keeps its state on the stack during romstage. + */ +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 + asmlinkage void car_stage_entry(void) { bool s3wake; + struct postcar_frame pcf; + uintptr_t top_of_ram; struct chipset_power_state *ps; console_init(); @@ -36,8 +48,29 @@ timestamp_add_now(TS_START_ROMSTAGE); s3wake = ps->prev_sleep_state == ACPI_S3; fsp_memory_init(s3wake); + if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + die("Unable to initialize postcar frame.\n"); + + /* + * We need to make sure ramstage will be run cached. At this + * point exact location of ramstage in cbmem is not known. + * Instruct postcar to cache 16 megs under cbmem top which is + * a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t) cbmem_top(); + printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); + top_of_ram -= 16*MiB; + postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1, + CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + + run_postcar_phase(&pcf); } + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { + mainboard_memory_init_params(mupd); } -- To view, visit https://review.coreboot.org/20534 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079 Gerrit-Change-Number: 20534 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Add memory map support
by build bot (Jenkins) (Code Review) 11 Jul '17

11 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20533 ) Change subject: soc/intel/cannonlake: Add memory map support ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/56859/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/12406/ : SUCCESS -- To view, visit https://review.coreboot.org/20533 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0dcc8f737c5811c9010cc4a20ea0126ab3f90f14 Gerrit-Change-Number: 20533 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Jul 2017 19:50:43 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add memory map support
by Lijian Zhao (Code Review) 11 Jul '17

11 Jul '17

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/20533 Change subject: soc/intel/cannonlake: Add memory map support ...................................................................... soc/intel/cannonlake: Add memory map support Calculate the top of ram from output of Fsp reserved memory range. Change-Id: I0dcc8f737c5811c9010cc4a20ea0126ab3f90f14 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc A src/soc/intel/cannonlake/memmap.c 2 files changed, 144 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/20533/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 480e047..b0fe57f 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -12,11 +12,11 @@ bootblock-y += bootblock/report_platform.c bootblock-y += gpio.c -romstage-y += cbmem.c +romstage-y += memmap.c romstage-y += reset.c romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c -ramstage-y += cbmem.c +ramstage-y += memmap.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c new file mode 100644 index 0000000..fb9d5f8 --- /dev/null +++ b/src/soc/intel/cannonlake/memmap.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <device/device.h> +#include <device/pci.h> +#include <fsp/util.h> +#include <soc/msr.h> +#include <soc/systemagent.h> +#include <soc/pci_devs.h> +#include <stdlib.h> + +#ifdef __x86_64__ +#define CRx_IN "q" +#define CRx_RET "=q" +#else +#define CRx_IN "r" +#define CRx_RET "=r" +#endif +#define COMPILER_BARRIER "memory" + +static alwaysinline uint32_t read_xmm0(void) +{ + uint32_t value; + __asm__ __volatile__ ( + "movd %%xmm0, %0" + : CRx_RET(value) + : + : COMPILER_BARRIER + ); + return value; +} + +static alwaysinline void write_xmm0(uint32_t data) +{ + __asm__ __volatile__ ( + "movd %0, %%xmm0" + : + : CRx_IN(data) + : COMPILER_BARRIER + ); +} + +/* + * Host Memory Map: + * + * +--------------------------+ TOUUD + * | | + * +--------------------------+ 4GiB + * | PCI Address Space | + * +--------------------------+ TOLUD (also maps into MC address space) + * | iGD | + * +--------------------------+ BDSM + * | GTT | + * +--------------------------+ BGSM + * | TSEG | + * +--------------------------+ TSEGMB + * | DMA Protected Region | + * +--------------------------+ DPR + * | PRM (C6DRAM/SGX) | + * +--------------------------+ PRMRR + * | Trace Memory | + * +--------------------------+ top_of_ram + * | Reserved - FSP/CBMEM | + * +--------------------------+ TOLUM + * | Usage DRAM | + * +--------------------------+ 0 + * + * Some of the base registers above can be equal making the size of those + * regions 0. The reason is because the memory controller internally subtracts + * the base registers from each other to determine sizes of the regions. In + * other words, the memory map is in a fixed order no matter what. + */ + +u32 top_of_32bit_ram(void) +{ + u32 top_of_ram = 0; + struct range_entry fsp_mem; + u32 fsp_reserve_base; + int status; + + /* + * Check if Tseg has been initialized, we will use this as a flag + * to check if the MRC is done, and only then continue to read the + * FSP Reserve Memory HOB. + */ + status = fsp_find_reserved_memory(&fsp_mem); + if (status == 0) { + fsp_reserve_base = (u32)range_entry_base(&fsp_mem); + top_of_ram = ALIGN_UP((uintptr_t)fsp_reserve_base, 16*MiB); + write_xmm0(top_of_ram); + } else + top_of_ram = read_xmm0(); + + return top_of_ram; +} + +void *cbmem_top(void) +{ + /* + * +-------------------------+ Top of RAM (aligned) + * | System Management Mode | + * | code and data | Length: CONFIG_TSEG_SIZE + * | (TSEG) | + * +-------------------------+ SMM base (aligned) + * | | + * | Chipset Reserved Memory | + * | | + * +-------------------------+ top_of_ram (aligned) + * | | + * | CBMEM Root | + * | | + * +-------------------------+ + * | | + * | FSP Reserved Memory | + * | | + * +-------------------------+ + * | | + * | Various CBMEM Entries | + * | | + * +-------------------------+ top_of_stack (8 byte aligned) + * | | + * | stack (CBMEM Entry) | + * | | + * +-------------------------+ + */ + return (void *)top_of_32bit_ram(); +} -- To view, visit https://review.coreboot.org/20533 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0dcc8f737c5811c9010cc4a20ea0126ab3f90f14 Gerrit-Change-Number: 20533 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: mainboard/intel/cannonlake_rvp: Initial board files
by build bot (Jenkins) (Code Review) 11 Jul '17

11 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20075 ) Change subject: mainboard/intel/cannonlake_rvp: Initial board files ...................................................................... Patch Set 12: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/56858/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/12405/ : SUCCESS -- To view, visit https://review.coreboot.org/20075 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I82bd5c785e451f02b827765c54d432517afd7de0 Gerrit-Change-Number: 20075 Gerrit-PatchSet: 12 Gerrit-Owner: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Jul 2017 19:20:06 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/intel/cannonlake_rvp: Initial board files
by build bot (Jenkins) (Code Review) 11 Jul '17

11 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20075 ) Change subject: mainboard/intel/cannonlake_rvp: Initial board files ...................................................................... Patch Set 11: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/56857/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/12404/ : SUCCESS -- To view, visit https://review.coreboot.org/20075 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I82bd5c785e451f02b827765c54d432517afd7de0 Gerrit-Change-Number: 20075 Gerrit-PatchSet: 11 Gerrit-Owner: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Jul 2017 19:11:34 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add minimal changes to call FSP Memory...
by build bot (Jenkins) (Code Review) 11 Jul '17

11 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20497 ) Change subject: soc/intel/cannonlake: Add minimal changes to call FSP Memoryinit ...................................................................... Patch Set 3: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/56856/ : UNSTABLE -- To view, visit https://review.coreboot.org/20497 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iab96b27d4220acf4089b901bca28018eaba940a1 Gerrit-Change-Number: 20497 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Jul 2017 18:46:50 +0000 Gerrit-HasComments: No

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coreboot-gerrit July 2017