coreboot-gerrit July 2017

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Change in coreboot[master]: mainboard/hp: Add HP Elitebook 2570p
by build bot (Jenkins) (Code Review) 11 Jul '17

11 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20489 ) Change subject: mainboard/hp: Add HP Elitebook 2570p ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56892/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12434/ : SUCCESS -- To view, visit https://review.coreboot.org/20489 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9f3cd124fc676d49add59e9f0a07f70a6bb0fff0 Gerrit-Change-Number: 20489 Gerrit-PatchSet: 5 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 12 Jul 2017 04:41:04 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboards/hp: Add HP Elitebook 2760p
by build bot (Jenkins) (Code Review) 11 Jul '17

11 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18241 ) Change subject: mainboards/hp: Add HP Elitebook 2760p ...................................................................... Patch Set 26: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56890/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12432/ : SUCCESS -- To view, visit https://review.coreboot.org/18241 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3ffdb9f9c71f6c9a84e896abc3c424c8dd4bed0e Gerrit-Change-Number: 18241 Gerrit-PatchSet: 26 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Swift Geek <swiftgeek(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 12 Jul 2017 04:31:25 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: ec: add support for KBC1126 in HP laptops
by build bot (Jenkins) (Code Review) 11 Jul '17

11 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19072 ) Change subject: ec: add support for KBC1126 in HP laptops ...................................................................... Patch Set 11: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56889/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12431/ : SUCCESS -- To view, visit https://review.coreboot.org/19072 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6b16eb7e26303eda740f52d667dedb7cc04b4ef0 Gerrit-Change-Number: 19072 Gerrit-PatchSet: 11 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 12 Jul 2017 04:28:04 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboards/hp: Add HP Elitebook 8470p
by build bot (Jenkins) (Code Review) 11 Jul '17

11 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18985 ) Change subject: mainboards/hp: Add HP Elitebook 8470p ...................................................................... Patch Set 11: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56891/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12433/ : SUCCESS -- To view, visit https://review.coreboot.org/18985 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icbc051e2272b8ea73627940db15a56901d737472 Gerrit-Change-Number: 18985 Gerrit-PatchSet: 11 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 12 Jul 2017 04:25:13 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboards/hp: Add HP Elitebook 2760p
by build bot (Jenkins) (Code Review) 11 Jul '17

11 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18241 ) Change subject: mainboards/hp: Add HP Elitebook 2760p ...................................................................... Patch Set 26: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56886/ : SUCCESS -- To view, visit https://review.coreboot.org/18241 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3ffdb9f9c71f6c9a84e896abc3c424c8dd4bed0e Gerrit-Change-Number: 18241 Gerrit-PatchSet: 26 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Swift Geek <swiftgeek(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 12 Jul 2017 04:24:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: ec: add support for KBC1126 in HP laptops
by build bot (Jenkins) (Code Review) 11 Jul '17

11 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19072 ) Change subject: ec: add support for KBC1126 in HP laptops ...................................................................... Patch Set 11: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56885/ : SUCCESS -- To view, visit https://review.coreboot.org/19072 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6b16eb7e26303eda740f52d667dedb7cc04b4ef0 Gerrit-Change-Number: 19072 Gerrit-PatchSet: 11 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 12 Jul 2017 04:18:37 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: driver/intel/wifi: Update wifi wake source in elog
by build bot (Jenkins) (Code Review) 11 Jul '17

11 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20455 ) Change subject: driver/intel/wifi: Update wifi wake source in elog ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56888/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12430/ : SUCCESS -- To view, visit https://review.coreboot.org/20455 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7d42c5c81e0a3f7a3f94c3f6b7d2ebdf029d1aff Gerrit-Change-Number: 20455 Gerrit-PatchSet: 4 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 12 Jul 2017 04:18:03 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboards/hp: Add HP Elitebook 8470p
by build bot (Jenkins) (Code Review) 11 Jul '17

11 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18985 ) Change subject: mainboards/hp: Add HP Elitebook 8470p ...................................................................... Patch Set 11: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56887/ : SUCCESS -- To view, visit https://review.coreboot.org/18985 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icbc051e2272b8ea73627940db15a56901d737472 Gerrit-Change-Number: 18985 Gerrit-PatchSet: 11 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 12 Jul 2017 04:17:11 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/hp: Add HP Elitebook 2570p
by Iru Cai (Code Review) 11 Jul '17

11 Jul '17

Iru Cai has uploaded this change for review. ( https://review.coreboot.org/20489 Change subject: mainboard/hp: Add HP Elitebook 2570p ...................................................................... mainboard/hp: Add HP Elitebook 2570p The EHCI debug port is the upper USB port beside the battery. Tested and working: - CPU and memory: i7-3720QM, 4G+4G - Linux Mint with Linux 4.4 (SeaBIOS payload) - All USB ports - ExpressCard - WLAN - AC and battery status - S3 - Other devices detected: DVD drive, smartcard reader, fingerprint, bluetooth Not tested: - VGA and DP - Ethernet and modem - Dock Change-Id: I9f3cd124fc676d49add59e9f0a07f70a6bb0fff0 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A src/mainboard/hp/2570p/Kconfig A src/mainboard/hp/2570p/Kconfig.name A src/mainboard/hp/2570p/Makefile.inc A src/mainboard/hp/2570p/acpi/ec.asl A src/mainboard/hp/2570p/acpi/platform.asl A src/mainboard/hp/2570p/acpi/superio.asl A src/mainboard/hp/2570p/acpi_tables.c A src/mainboard/hp/2570p/board_info.txt A src/mainboard/hp/2570p/devicetree.cb A src/mainboard/hp/2570p/dsdt.asl A src/mainboard/hp/2570p/gma-mainboard.ads A src/mainboard/hp/2570p/gpio.c A src/mainboard/hp/2570p/hda_verb.c A src/mainboard/hp/2570p/mainboard.c A src/mainboard/hp/2570p/romstage.c 15 files changed, 765 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/20489/5 diff --git a/src/mainboard/hp/2570p/Kconfig b/src/mainboard/hp/2570p/Kconfig new file mode 100644 index 0000000..e6a5d4c --- /dev/null +++ b/src/mainboard/hp/2570p/Kconfig @@ -0,0 +1,68 @@ +if BOARD_HP_2570P + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select CPU_INTEL_SOCKET_RPGA989 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SANDYBRIDGE_IVYBRIDGE_LVDS + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + select EC_HP_KBC1126 + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_INTERNAL_IS_LVDS + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default hp/2570p + +config MAINBOARD_PART_NUMBER + string + default "HP EliteBook 2570p" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x17df + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x103c + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 +endif diff --git a/src/mainboard/hp/2570p/Kconfig.name b/src/mainboard/hp/2570p/Kconfig.name new file mode 100644 index 0000000..cac032d --- /dev/null +++ b/src/mainboard/hp/2570p/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_2570P + bool "HP EliteBook 2570p" diff --git a/src/mainboard/hp/2570p/Makefile.inc b/src/mainboard/hp/2570p/Makefile.inc new file mode 100644 index 0000000..ea035d3 --- /dev/null +++ b/src/mainboard/hp/2570p/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/2570p/acpi/ec.asl b/src/mainboard/hp/2570p/acpi/ec.asl new file mode 100644 index 0000000..830c819 --- /dev/null +++ b/src/mainboard/hp/2570p/acpi/ec.asl @@ -0,0 +1 @@ +#include <ec/hp/kbc1126/acpi/ec.asl> diff --git a/src/mainboard/hp/2570p/acpi/platform.asl b/src/mainboard/hp/2570p/acpi/platform.asl new file mode 100644 index 0000000..79eddcb --- /dev/null +++ b/src/mainboard/hp/2570p/acpi/platform.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/hp/2570p/acpi/superio.asl b/src/mainboard/hp/2570p/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/hp/2570p/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/hp/2570p/acpi_tables.c b/src/mainboard/hp/2570p/acpi_tables.c new file mode 100644 index 0000000..6b731cc --- /dev/null +++ b/src/mainboard/hp/2570p/acpi_tables.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/hp/2570p/board_info.txt b/src/mainboard/hp/2570p/board_info.txt new file mode 100644 index 0000000..51ecd98 --- /dev/null +++ b/src/mainboard/hp/2570p/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/HP-EliteBook-2570p-Notebook-PC/5259393 +ROM protocol: SPI +ROM package: SOIC-16 +ROM socketed: n +Flashrom support: n +Release year: 2012 diff --git a/src/mainboard/hp/2570p/devicetree.cb b/src/mainboard/hp/2570p/devicetree.cb new file mode 100644 index 0000000..f539861 --- /dev/null +++ b/src/mainboard/hp/2570p/devicetree.cb @@ -0,0 +1,142 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x00000437" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "2300" + register "gpu_panel_power_backlight_on_delay" = "2000" + register "gpu_panel_power_cycle_delay" = "5" + register "gpu_panel_power_down_delay" = "230" + register "gpu_panel_power_up_delay" = "300" + register "gpu_pch_backlight" = "0x0d9c0d9c" + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x000402e9" + register "gpi6_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x103c 0x17df + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x103c 0x17df + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x103c 0x17df + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x103c 0x17df + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x103c 0x17df + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x103c 0x17df + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x103c 0x17df + end + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x103c 0x17df + end + device pci 1c.3 on # PCIe Port #4 + subsystemid 0x103c 0x17df + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x103c 0x17df + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x103c 0x17df + chip ec/hp/kbc1126 + register "ec_data_port" = "0x62" + register "ec_cmd_port" = "0x66" + register "ec_ctrl_reg" = "0x81" + device pnp ff.1 off end + end # kbc1126 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x103c 0x17df + end + device pci 1f.3 off # SMBus + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x103c 0x17df + end + device pci 01.0 off # PCIe Bridge for discrete graphics + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x103c 0x17df + end + end +end diff --git a/src/mainboard/hp/2570p/dsdt.asl b/src/mainboard/hp/2570p/dsdt.asl new file mode 100644 index 0000000..3b7fb7e --- /dev/null +++ b/src/mainboard/hp/2570p/dsdt.asl @@ -0,0 +1,30 @@ +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> + } + } +} diff --git a/src/mainboard/hp/2570p/gma-mainboard.ads b/src/mainboard/hp/2570p/gma-mainboard.ads new file mode 100644 index 0000000..9877397 --- /dev/null +++ b/src/mainboard/hp/2570p/gma-mainboard.ads @@ -0,0 +1,18 @@ +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + HDMI1, + HDMI2, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/2570p/gpio.c b/src/mainboard/hp/2570p/gpio.c new file mode 100644 index 0000000..b07fb5b --- /dev/null +++ b/src/mainboard/hp/2570p/gpio.c @@ -0,0 +1,246 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +const static struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +const static struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +const static struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +const static struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +const static struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +const static struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +const static struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +const static struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +const static struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio46 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_LOW, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_LOW, +}; + +const static struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +const static struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +const static struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +const static struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +const static struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/2570p/hda_verb.c b/src/mainboard/hp/2570p/hda_verb.c new file mode 100644 index 0000000..3c4c734 --- /dev/null +++ b/src/mainboard/hp/2570p/hda_verb.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d7605, /* Codec Vendor / Device ID: IDT */ + 0x103c17df, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x103c17df), + + /* NID 0x0a. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x21011030), + + /* NID 0x0b. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x0421101f), + + /* NID 0x0c. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x04a11020), + + /* NID 0x0d. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110), + + /* NID 0x0e. */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x40f000f0), + + /* NID 0x0f. */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x2181102e), + + /* NID 0x10. */ + AZALIA_PIN_CFG(0x0, 0x10, 0x40f000f0), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x0, 0x11, 0xd5a30140), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x40f000f0), + + /* NID 0x20. */ + AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0), + 0x11c11040, /* Codec Vendor / Device ID: LSI */ + 0x103c3066, /* Subsystem ID */ + + 0x00000001, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x1, 0x103c3066), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x58560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/2570p/mainboard.c b/src/mainboard/hp/2570p/mainboard.c new file mode 100644 index 0000000..d84bff9 --- /dev/null +++ b/src/mainboard/hp/2570p/mainboard.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(device_t dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/hp/2570p/romstage.c b/src/mainboard/hp/2570p/romstage.c new file mode 100644 index 0000000..9bcc892 --- /dev/null +++ b/src/mainboard/hp/2570p/romstage.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/hp/kbc1126/ec.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0201); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0101); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00fcfe01); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000402e9); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x02010000); +} + +void rcba_config(void) +{ + /* Disable devices. */ + RCBA32(0x3414) = 0x00000000; + RCBA32(0x3418) = 0x17f01feb; + +} +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 0, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 0, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 4 }, + { 1, 1, 4 }, + { 1, 0, 5 }, + { 0, 0, 5 }, + { 1, 0, 6 }, + { 0, 0, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ + kbc1126_enter_conf(); + kbc1126_mailbox_init(); + kbc1126_kbc_init(); + kbc1126_ec_init(); + kbc1126_pm1_init(); + kbc1126_exit_conf(); + kbc1126_disable4e(); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} -- To view, visit https://review.coreboot.org/20489 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9f3cd124fc676d49add59e9f0a07f70a6bb0fff0 Gerrit-Change-Number: 20489 Gerrit-PatchSet: 5 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com>

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Change in coreboot[master]: mainboards/hp: Add HP Elitebook 8470p
by Iru Cai (Code Review) 11 Jul '17

11 Jul '17

Iru Cai has uploaded a new patch set (#11). ( https://review.coreboot.org/18985 ) Change subject: mainboards/hp: Add HP Elitebook 8470p ...................................................................... mainboards/hp: Add HP Elitebook 8470p The code is based on the code generated by autoport. The EHCI debug port is between the DP port and eSATA port. The serial port on dock can also be used for debugging. The model with discrete graphics is not tested. Tested and work: - memory: 0+4G, 4G+0, 4G+4G - Linux (Arch Linux with kernel 4.10.6) boot from SeaBIOS payload with native graphics init - WLAN - keyboard, trackpoint and touchpad - USB - serial port on dock - fan control - AC and battery status (EC) blobs: This laptop uses SMSC KBC1126 EC, and there are two blobs needed by it. You can use the tools in util/kbc1126/ to extract them and insert them to the coreboot image using the following configuration: -> Chipset -> Add firmware images for KBC1126 firmware Change-Id: Icbc051e2272b8ea73627940db15a56901d737472 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A src/mainboard/hp/8470p/Kconfig A src/mainboard/hp/8470p/Kconfig.name A src/mainboard/hp/8470p/Makefile.inc A src/mainboard/hp/8470p/acpi/ec.asl A src/mainboard/hp/8470p/acpi/platform.asl A src/mainboard/hp/8470p/acpi/superio.asl A src/mainboard/hp/8470p/acpi_tables.c A src/mainboard/hp/8470p/board_info.txt A src/mainboard/hp/8470p/devicetree.cb A src/mainboard/hp/8470p/dsdt.asl A src/mainboard/hp/8470p/gma-mainboard.ads A src/mainboard/hp/8470p/gpio.c A src/mainboard/hp/8470p/hda_verb.c A src/mainboard/hp/8470p/mainboard.c A src/mainboard/hp/8470p/romstage.c 15 files changed, 767 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/18985/11 -- To view, visit https://review.coreboot.org/18985 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Icbc051e2272b8ea73627940db15a56901d737472 Gerrit-Change-Number: 18985 Gerrit-PatchSet: 11 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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