coreboot-gerrit June 2017

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Change in coreboot[master]: mainboard/[m-w]: add IS_ENABLED() around Kconfig symbol refe...
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20344 Change subject: mainboard/[m-w]: add IS_ENABLED() around Kconfig symbol references ...................................................................... mainboard/[m-w]: add IS_ENABLED() around Kconfig symbol references Change-Id: Ifba3257b0328d0b6ad1bee9bf885683998df5851 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/msi/ms7135/romstage.c M src/mainboard/msi/ms7260/romstage.c M src/mainboard/msi/ms7721/buildOpts.c M src/mainboard/msi/ms9185/mptable.c M src/mainboard/msi/ms9185/romstage.c M src/mainboard/msi/ms9282/romstage.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/nvidia/l1_2pvv/romstage.c M src/mainboard/samsung/lumpy/acpi_tables.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/romstage.c M src/mainboard/siemens/mc_bdx1/mainboard.c M src/mainboard/siemens/mc_tcu3/mainboard.c M src/mainboard/siemens/sitemp_g1p1/acpi_tables.c M src/mainboard/siemens/sitemp_g1p1/mainboard.c M src/mainboard/siemens/sitemp_g1p1/romstage.c M src/mainboard/sunw/ultra40/romstage.c M src/mainboard/sunw/ultra40m2/romstage.c M src/mainboard/supermicro/h8dme/romstage.c M src/mainboard/supermicro/h8dmr/romstage.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qgi/buildOpts.c M src/mainboard/supermicro/h8qgi/rd890_cfg.h M src/mainboard/supermicro/h8qgi/sb700_cfg.h M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/supermicro/h8scm/rd890_cfg.h M src/mainboard/supermicro/h8scm/sb700_cfg.h M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/technexion/tim5690/mainboard.c M src/mainboard/technexion/tim5690/romstage.c M src/mainboard/technexion/tim8690/romstage.c M src/mainboard/thomson/ip1000/spd_table.h M src/mainboard/tyan/s2912/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c M src/mainboard/tyan/s8226/buildOpts.c M src/mainboard/tyan/s8226/rd890_cfg.h M src/mainboard/tyan/s8226/sb700_cfg.h M src/mainboard/via/epia-m850/mainboard.c M src/mainboard/via/epia-m850/romstage.c M src/mainboard/winent/mb6047/romstage.c 40 files changed, 81 insertions(+), 81 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/20344/1 diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 08fbdc7..c595006 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -41,7 +41,7 @@ #include <spd.h> #include <northbridge/amd/amdk8/pre_f.h> -#if CONFIG_HAVE_OPTION_TABLE +#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE) #include "option_table.h" #endif @@ -132,7 +132,7 @@ needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); @@ -156,7 +156,7 @@ ms7135_set_nf4_voltage(); ms7135_set_ram_voltage(); -#if CONFIG_DEBUG_SMBUS +#if IS_ENABLED(CONFIG_DEBUG_SMBUS) dump_spd_registers(&ctrl[0]); dump_smbus_registers(); #endif diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 6feddcf..5287258a 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -144,7 +144,7 @@ setup_coherent_ht_domain(); /* Routing table and start other core0. */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched * becase optimize_link_coherent_ht is moved out from * setup_coherent_ht_domain, so here need to make sure last core0 is @@ -158,7 +158,7 @@ /* Set up chains and store link pair for optimization later. */ ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) { msr_t msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index ecb168c..5191574 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -168,7 +168,7 @@ #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c index 38cc72b..e93602b 100644 --- a/src/mainboard/msi/ms9185/mptable.c +++ b/src/mainboard/msi/ms9185/mptable.c @@ -26,7 +26,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdk8_sysconf.h> diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 56eaa6a..5d03179 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -123,7 +123,7 @@ setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, @@ -144,7 +144,7 @@ needs_reset |= optimize_link_incoherent_ht(sysinfo); #endif -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) { msr_t msr; msr = rdmsr(0xc0010042); diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index fd90491..4fa40bf 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -154,7 +154,7 @@ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched start_other_cores(); //wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 4acb240..11e9bc0 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -178,7 +178,7 @@ */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -189,7 +189,7 @@ post_code(0x38); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index b80f4f3..9c04b1c 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -142,7 +142,7 @@ setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, @@ -155,7 +155,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) { msr_t msr; msr = rdmsr(0xc0010042); diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index 828546c..65922f3 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -25,7 +25,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <ec/acpi/ec.h> -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 2a4bb4c..3afb196 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -38,7 +38,7 @@ #include <cpu/x86/msr.h> #include <halt.h> #include "option_table.h" -#if CONFIG_DRIVERS_UART_8250IO +#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) #include <superio/smsc/lpc47n207/lpc47n207.h> #endif @@ -47,7 +47,7 @@ /* Set COM1/COM2 decode range */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); -#if CONFIG_DRIVERS_UART_8250IO +#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) /* Enable SuperIO + EC + KBC + COM1 + lpc47n207 config*/ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index c4df1e7..ec5368d 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -38,12 +38,12 @@ #include <cpu/x86/msr.h> #include <halt.h> #include <tpm.h> -#if CONFIG_DRIVERS_UART_8250IO +#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) #include <superio/smsc/lpc47n207/lpc47n207.h> #endif /* Stumpy USB Reset Disable defined in cmos.layout */ -#if CONFIG_USE_OPTION_TABLE +#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) #include "option_table.h" #define CMOS_USB_RESET_DISABLE (CMOS_VSTART_stumpy_usb_reset_disable >> 3) #else @@ -60,7 +60,7 @@ /* Set COM1/COM2 decode range */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); -#if CONFIG_DRIVERS_UART_8250IO +#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) /* Enable SuperIO + PS/2 Keyboard/Mouse + COM1 + lpc47n207 config*/ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |\ CNF2_LPC_EN | COMA_LPC_EN); diff --git a/src/mainboard/siemens/mc_bdx1/mainboard.c b/src/mainboard/siemens/mc_bdx1/mainboard.c index fe35fe1..f5ea3ab 100644 --- a/src/mainboard/siemens/mc_bdx1/mainboard.c +++ b/src/mainboard/siemens/mc_bdx1/mainboard.c @@ -21,7 +21,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif #include <pc80/mc146818rtc.h> diff --git a/src/mainboard/siemens/mc_tcu3/mainboard.c b/src/mainboard/siemens/mc_tcu3/mainboard.c index a11ff26..df08471 100644 --- a/src/mainboard/siemens/mc_tcu3/mainboard.c +++ b/src/mainboard/siemens/mc_tcu3/mainboard.c @@ -21,7 +21,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif #include <pc80/mc146818rtc.h> diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c index 0582566..30f963e 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c +++ b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c @@ -65,7 +65,7 @@ /* Write SB600 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); -#if !CONFIG_LINT01_CONVERSION +#if !IS_ENABLED(CONFIG_LINT01_CONVERSION) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c index 1f266a7..bc2c75b 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c @@ -30,7 +30,7 @@ #include <southbridge/amd/rs690/chip.h> #include <southbridge/amd/rs690/rs690.h> #include <superio/ite/it8712f/it8712f.h> -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) #include <x86emu/x86emu.h> #endif #include "int15_func.h" @@ -215,7 +215,7 @@ u8 t_range; }; /* ############################################################################################# */ -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) static int int15_handler(void) { #define BOOT_DISPLAY_DEFAULT 0 @@ -779,14 +779,14 @@ static void mainboard_init(device_t dev) { -#if CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) INT15_function_extensions int15_func; #endif printk(BIOS_DEBUG, "%s %s[%x/%x] %s\n", dev_name(dev), dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__); -#if CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) if (get_option(&int15_func.regs.func00_LCD_panel_id, "lcd_panel_id") != CB_SUCCESS) int15_func.regs.func00_LCD_panel_id = PANEL_TABLE_ID_NO; int15_func.regs.func05_TV_standard = TV_MODE_NO; @@ -808,7 +808,7 @@ printk(BIOS_INFO, "%s %s[%x/%x] %s\n", dev_name(dev), dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__); -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); #endif diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 6ac79d1..52d9c23 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -117,7 +117,7 @@ setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index 1345871..405439f 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -124,7 +124,7 @@ needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c index 44bf851..9145ca5 100644 --- a/src/mainboard/sunw/ultra40m2/romstage.c +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -135,7 +135,7 @@ setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, @@ -148,7 +148,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) { msr_t msr; msr = rdmsr(0xc0010042); diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index d0ab05e..f173d1a 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -154,13 +154,13 @@ printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram -#if CONFIG_DEBUG_SMBUS +#if IS_ENABLED(CONFIG_DEBUG_SMBUS) dump_smbus_registers(); #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, @@ -173,7 +173,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) { msr_t msr; msr = rdmsr(0xc0010042); diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index e4ee1c8..3f01c92 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -137,7 +137,7 @@ setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, @@ -150,7 +150,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) { msr_t msr; msr = rdmsr(0xc0010042); diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index d457f1b..e100876 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -173,7 +173,7 @@ */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -183,7 +183,7 @@ post_code(0x38); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c index 4db2c6f..b146afe 100644 --- a/src/mainboard/supermicro/h8qgi/buildOpts.c +++ b/src/mainboard/supermicro/h8qgi/buildOpts.c @@ -426,10 +426,10 @@ */ /* -#if CONFIG_CPU_AMD_AGESA_FAMILY15 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15) #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE #endif -#if CONFIG_CPU_AMD_AGESA_FAMILY10 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10) #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE #endif */ diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.h b/src/mainboard/supermicro/h8qgi/rd890_cfg.h index 35ddfbb..6607094 100644 --- a/src/mainboard/supermicro/h8qgi/rd890_cfg.h +++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.h @@ -27,10 +27,10 @@ * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. */ #ifndef DEFAULT_HT_PATH -#if CONFIG_CPU_AMD_AGESA_FAMILY10 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10) #define DEFAULT_HT_PATH {0x0, 0x3} #endif -#if CONFIG_CPU_AMD_AGESA_FAMILY15 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15) #define DEFAULT_HT_PATH {0x0, 0x1} #endif #endif diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.h b/src/mainboard/supermicro/h8qgi/sb700_cfg.h index a5f371d..62b618f 100644 --- a/src/mainboard/supermicro/h8qgi/sb700_cfg.h +++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.h @@ -36,13 +36,13 @@ * before AGESA module get call. */ #ifndef BIOS_SIZE -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 +#if IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_1024) #define BIOS_SIZE BIOS_SIZE_1M -#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_2048) #define BIOS_SIZE BIOS_SIZE_2M -#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_4096) #define BIOS_SIZE BIOS_SIZE_4M -#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_8192) #define BIOS_SIZE BIOS_SIZE_8M #endif #endif diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 26f3da7..3554a05 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -239,7 +239,7 @@ */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -249,7 +249,7 @@ post_code(0x38); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/supermicro/h8scm/rd890_cfg.h b/src/mainboard/supermicro/h8scm/rd890_cfg.h index 35ddfbb..6607094 100644 --- a/src/mainboard/supermicro/h8scm/rd890_cfg.h +++ b/src/mainboard/supermicro/h8scm/rd890_cfg.h @@ -27,10 +27,10 @@ * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. */ #ifndef DEFAULT_HT_PATH -#if CONFIG_CPU_AMD_AGESA_FAMILY10 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10) #define DEFAULT_HT_PATH {0x0, 0x3} #endif -#if CONFIG_CPU_AMD_AGESA_FAMILY15 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15) #define DEFAULT_HT_PATH {0x0, 0x1} #endif #endif diff --git a/src/mainboard/supermicro/h8scm/sb700_cfg.h b/src/mainboard/supermicro/h8scm/sb700_cfg.h index c067095..62b618f 100644 --- a/src/mainboard/supermicro/h8scm/sb700_cfg.h +++ b/src/mainboard/supermicro/h8scm/sb700_cfg.h @@ -36,13 +36,13 @@ * before AGESA module get call. */ #ifndef BIOS_SIZE -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 +#if IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_1024) #define BIOS_SIZE BIOS_SIZE_1M -#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_2048) #define BIOS_SIZE BIOS_SIZE_2M -#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_4096) #define BIOS_SIZE BIOS_SIZE_4M -#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_8192) #define BIOS_SIZE BIOS_SIZE_8M #endif #endif diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 091514d..60288e0 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -153,7 +153,7 @@ */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -167,7 +167,7 @@ sr5650_early_setup(); sb7xx_51xx_early_setup(); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 8bc1075..edc1170 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -184,7 +184,7 @@ it8712f_exit_conf(); } -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) /* The LCD's panel id seletion. */ static void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id) { @@ -221,7 +221,7 @@ static void mainboard_enable(device_t dev) { u16 gpio_base = IT8712F_SIMPLE_IO_BASE; -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) rs690_vbios_regs vbios_regs; u8 port2; #endif @@ -230,7 +230,7 @@ mb_gpio_init(&gpio_base); -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) /* The LCD's panel id seletion by switch. */ port2 = inb(gpio_base+1); lcd_panel_id(&vbios_regs, ((~port2) & 0xf)); diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 3b4b4fd..744ea67 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -95,7 +95,7 @@ setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 6030864..18e3140 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -91,7 +91,7 @@ setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/thomson/ip1000/spd_table.h b/src/mainboard/thomson/ip1000/spd_table.h index 0ecf1c0..1de05ed 100644 --- a/src/mainboard/thomson/ip1000/spd_table.h +++ b/src/mainboard/thomson/ip1000/spd_table.h @@ -16,11 +16,11 @@ #include <spd.h> -#if CONFIG_ONBOARD_MEMORY_64MB +#if IS_ENABLED(CONFIG_ONBOARD_MEMORY_64MB) #define DENSITY 0x10 -#elif CONFIG_ONBOARD_MEMORY_128MB +#elif IS_ENABLED(CONFIG_ONBOARD_MEMORY_128MB) #define DENSITY 0x20 diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 6a47612..89f3175 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -140,7 +140,7 @@ setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, @@ -153,7 +153,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) { msr_t msr; msr = rdmsr(0xc0010042); diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 4c8c19f..b449f77 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -174,7 +174,7 @@ */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -184,7 +184,7 @@ post_code(0x38); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/tyan/s8226/buildOpts.c b/src/mainboard/tyan/s8226/buildOpts.c index 1312892..e27ec16 100644 --- a/src/mainboard/tyan/s8226/buildOpts.c +++ b/src/mainboard/tyan/s8226/buildOpts.c @@ -426,10 +426,10 @@ */ /* -#if CONFIG_CPU_AMD_AGESA_FAMILY15 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15) #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE #endif -#if CONFIG_CPU_AMD_AGESA_FAMILY10 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10) #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE #endif */ diff --git a/src/mainboard/tyan/s8226/rd890_cfg.h b/src/mainboard/tyan/s8226/rd890_cfg.h index 35ddfbb..6607094 100644 --- a/src/mainboard/tyan/s8226/rd890_cfg.h +++ b/src/mainboard/tyan/s8226/rd890_cfg.h @@ -27,10 +27,10 @@ * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. */ #ifndef DEFAULT_HT_PATH -#if CONFIG_CPU_AMD_AGESA_FAMILY10 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10) #define DEFAULT_HT_PATH {0x0, 0x3} #endif -#if CONFIG_CPU_AMD_AGESA_FAMILY15 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15) #define DEFAULT_HT_PATH {0x0, 0x1} #endif #endif diff --git a/src/mainboard/tyan/s8226/sb700_cfg.h b/src/mainboard/tyan/s8226/sb700_cfg.h index 3f82931..bed9161 100644 --- a/src/mainboard/tyan/s8226/sb700_cfg.h +++ b/src/mainboard/tyan/s8226/sb700_cfg.h @@ -36,13 +36,13 @@ * before AGESA module get call. */ #ifndef BIOS_SIZE -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 +#if IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_1024) #define BIOS_SIZE BIOS_SIZE_1M -#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_2048) #define BIOS_SIZE BIOS_SIZE_2M -#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_4096) #define BIOS_SIZE BIOS_SIZE_4M -#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_8192) #define BIOS_SIZE BIOS_SIZE_8M #endif #endif diff --git a/src/mainboard/via/epia-m850/mainboard.c b/src/mainboard/via/epia-m850/mainboard.c index 335e86b..68c49bc 100644 --- a/src/mainboard/via/epia-m850/mainboard.c +++ b/src/mainboard/via/epia-m850/mainboard.c @@ -19,7 +19,7 @@ #include <device/pci_ops.h> #include <console/console.h> -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <arch/interrupt.h> #include <x86emu/x86emu.h> @@ -96,7 +96,7 @@ { (void)dev; -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) printk(BIOS_DEBUG, "Installing INT15 handler...\n"); mainboard_interrupt_handlers(0x15, &vx900_int15_handler); #endif diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index 450f7d7..a79d419 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -90,7 +90,7 @@ printk(BIOS_DEBUG, "We passed RAM verify\n"); /* We got RAM working, now we can write the timestamps to RAM */ -#if CONFIG_EARLY_CBMEM_INIT +#if IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) cbmem_recovery(0); #endif /* FIXME: See if this is needed or take this out please */ diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index 09de180..ddce5c6 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -37,7 +37,7 @@ #include <southbridge/nvidia/ck804/early_setup_ss.h> #include "southbridge/nvidia/ck804/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) #include "cpu/amd/model_fxx/fidvid.c" #endif #include "northbridge/amd/amdk8/early_ht.c" @@ -100,7 +100,7 @@ start_other_cores(); wait_all_other_cores_started(bsp_apicid); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ if ((cpuid_edx(0x80000007) & 0x6) == 0x6) { -- To view, visit https://review.coreboot.org/20344 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifba3257b0328d0b6ad1bee9bf885683998df5851 Gerrit-Change-Number: 20344 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: mainboard/[g-l]: add IS_ENABLED() around Kconfig symbol refe...
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20343 Change subject: mainboard/[g-l]: add IS_ENABLED() around Kconfig symbol references ...................................................................... mainboard/[g-l]: add IS_ENABLED() around Kconfig symbol references Change-Id: I1f906c8c465108017bc4d08534653233078ef32d Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/gigabyte/ga_2761gxdk/romstage.c M src/mainboard/gigabyte/m57sli/romstage.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/google/auron/smihandler.c M src/mainboard/google/beltino/acpi_tables.c M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/link/acpi_tables.c M src/mainboard/google/link/mainboard.c M src/mainboard/google/link/mainboard_smi.c M src/mainboard/google/nyan_blaze/romstage.c M src/mainboard/google/parrot/acpi_tables.c M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/rambi/mainboard.c M src/mainboard/google/rambi/mainboard_smi.c M src/mainboard/google/slippy/acpi_tables.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/google/storm/mainboard.c M src/mainboard/google/stout/acpi_tables.c M src/mainboard/google/stout/ec.c M src/mainboard/hp/dl145_g1/romstage.c M src/mainboard/hp/dl145_g3/mptable.c M src/mainboard/hp/dl145_g3/romstage.c M src/mainboard/hp/dl165_g6_fam10/mptable.c M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/intel/baskingridge/acpi_tables.c M src/mainboard/intel/bayleybay_fsp/mainboard.c M src/mainboard/intel/camelbackmountain_fsp/mainboard.c M src/mainboard/intel/cougar_canyon2/romstage.c M src/mainboard/intel/eagleheights/fadt.c M src/mainboard/iwill/dk8_htx/mptable.c M src/mainboard/iwill/dk8_htx/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/kontron/kt690/romstage.c M src/mainboard/kontron/ktqm77/mainboard.c M src/mainboard/lenovo/g505s/buildOpts.c M src/mainboard/lenovo/t400/romstage.c M src/mainboard/lenovo/x200/romstage.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/lippert/frontrunner/romstage.c M src/mainboard/lippert/hurricane-lx/mainboard.c M src/mainboard/lippert/hurricane-lx/romstage.c M src/mainboard/lippert/literunner-lx/mainboard.c M src/mainboard/lippert/literunner-lx/romstage.c M src/mainboard/lippert/roadrunner-lx/mainboard.c M src/mainboard/lippert/roadrunner-lx/romstage.c M src/mainboard/lippert/spacerunner-lx/mainboard.c M src/mainboard/lippert/spacerunner-lx/romstage.c 52 files changed, 88 insertions(+), 87 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/20343/1 diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 6a18e98..79debd7 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -137,7 +137,7 @@ setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, @@ -150,7 +150,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) { msr_t msr; msr = rdmsr(0xc0010042); diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index d4b6367..7346657 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -155,7 +155,7 @@ setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, @@ -168,7 +168,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) { msr_t msr; msr = rdmsr(0xc0010042); diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 2e22556..12fe12c 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -137,7 +137,7 @@ */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -151,7 +151,7 @@ rs780_early_setup(); sb7xx_51xx_early_setup(); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index bf51e38..6747a62 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -137,7 +137,7 @@ */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -151,7 +151,7 @@ rs780_early_setup(); sb7xx_51xx_early_setup(); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 1405507..ff9ced2 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -139,7 +139,7 @@ */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -153,7 +153,7 @@ rs780_early_setup(); sb7xx_51xx_early_setup(); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index 03d07b9..247fc2f 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -33,7 +33,7 @@ u8 cmd = google_chromeec_get_event(); u32 pm1_cnt; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) /* Log this event */ if (cmd) elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c index 6eaa5e2..86a25fc 100644 --- a/src/mainboard/google/beltino/acpi_tables.c +++ b/src/mainboard/google/beltino/acpi_tables.c @@ -72,7 +72,7 @@ gnvs->tpmp = 1; -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) // SuperIO is always RO gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; #endif diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 70916d5..1ce25b4 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -34,7 +34,7 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #endif #include <cbfs.h> diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index 3f86c29..bd17c4d 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -68,7 +68,7 @@ int get_recovery_mode_switch(void) { -#if CONFIG_EC_GOOGLE_CHROMEEC +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) uint32_t ec_events; ec_events = google_chromeec_get_events_b(); diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c index 13c358b..28d9922 100644 --- a/src/mainboard/google/link/acpi_tables.c +++ b/src/mainboard/google/link/acpi_tables.c @@ -58,7 +58,7 @@ gnvs->s5u0 = 0; gnvs->s5u1 = 0; -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 53915d2..24062e9 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -21,7 +21,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif #include <pc80/mc146818rtc.h> @@ -52,7 +52,7 @@ */ } -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) static int int15_handler(void) { int res = 0; @@ -201,7 +201,7 @@ dev->ops->init = mainboard_init; dev->ops->get_smbios_data = link_onboard_smbios_data; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); #endif diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c index a0d3803..0babb54 100644 --- a/src/mainboard/google/link/mainboard_smi.c +++ b/src/mainboard/google/link/mainboard_smi.c @@ -33,7 +33,7 @@ u8 cmd = google_chromeec_get_event(); u32 pm1_cnt; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) /* Log this event */ if (cmd) elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index e3d7116..f094e34 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -53,7 +53,7 @@ u32 dram_end_mb = sdram_max_addressable_mb(); u32 dram_size_mb = dram_end_mb - dram_start_mb; -#if !CONFIG_VBOOT +#if !IS_ENABLED(CONFIG_VBOOT) configure_l2_cache(); mmu_init(); /* Device memory below DRAM is uncached. */ @@ -96,7 +96,7 @@ /* Stub to force arm_init_caches to the top, before any stack/memory accesses */ void main(void) { -#if !CONFIG_VBOOT +#if !IS_ENABLED(CONFIG_VBOOT) asm volatile ("bl arm_init_caches" ::: "r0","r1","r2","r3","r4","r5","ip"); #endif diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index 2cda4a2..ae36ba0 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -51,7 +51,7 @@ gnvs->s5u1 = 0; -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) gnvs->chromeos.vbt2 = parrot_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index 351f082..176e33c 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -29,7 +29,7 @@ { u8 src; u32 pm1_cnt; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) static int battery_critical_logged; #endif @@ -39,7 +39,7 @@ switch (src) { case EC_BATTERY_CRITICAL: -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) if (!battery_critical_logged) elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_BATTERY_CRITICAL); @@ -49,7 +49,7 @@ case EC_LID_CLOSE: printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED); #endif /* Go to S5 */ @@ -74,7 +74,7 @@ else if (gpi_sts & (1 << EC_LID_GPI)) { printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED); #endif /* Go to S5 */ diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index acd4ffe..b8dd805 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -21,7 +21,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif #include <pc80/mc146818rtc.h> @@ -40,7 +40,7 @@ { } -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) static int int15_handler(void) { int res = 1; @@ -169,7 +169,7 @@ dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); #endif diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c index bd6f91e..113e7ce 100644 --- a/src/mainboard/google/rambi/mainboard_smi.c +++ b/src/mainboard/google/rambi/mainboard_smi.c @@ -34,7 +34,7 @@ uint16_t pmbase = get_pmbase(); uint32_t pm1_cnt; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) /* Log this event */ if (cmd) elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index bf16858..4036f1b 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -55,7 +55,7 @@ gnvs->tpmp = 1; -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index 24f76f5..3480147 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -41,7 +41,7 @@ u8 cmd = google_chromeec_get_event(); u32 pm1_cnt; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) /* Log this event */ if (cmd) elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index e3e7b68..3c1477d 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -31,7 +31,7 @@ static void setup_usb(void) { -#if !CONFIG_BOARD_VARIANT_AP148 +#if !IS_ENABLED(CONFIG_BOARD_VARIANT_AP148) gpio_tlmm_config_set(USB_ENABLE_GPIO, FUNC_SEL_GPIO, GPIO_PULL_UP, GPIO_10MA, GPIO_ENABLE); gpio_set(USB_ENABLE_GPIO, 1); diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index 7019c81..078cba2 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -53,7 +53,7 @@ gnvs->s5u1 = 0; -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) gnvs->chromeos.vbt2 = get_recovery_mode_switch() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index a7006d9..a459d0c 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -76,7 +76,7 @@ if (ec_reg & 0x8) { printk(BIOS_ERR, " EC Fan Error\n"); critical_shutdown = 1; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) elog_add_event_word(EC_EVENT_BATTERY_CRITICAL, EC_EVENT_FAN_ERROR); #endif } @@ -86,7 +86,7 @@ if (ec_reg & 0x80) { printk(BIOS_ERR, " EC Thermal Device Error\n"); critical_shutdown = 1; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) elog_add_event_word(EC_EVENT_BATTERY_CRITICAL, EC_EVENT_THERMAL); #endif } @@ -98,14 +98,14 @@ if ((ec_reg & 0xCF) == 0xC0) { printk(BIOS_ERR, " EC Critical Battery Error\n"); critical_shutdown = 1; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) elog_add_event_word(ELOG_TYPE_EC_EVENT, EC_EVENT_BATTERY_CRITICAL); #endif } if ((ec_reg & 0x8F) == 0x8F) { printk(BIOS_ERR, " EC Read Battery Error\n"); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) elog_add_event_word(ELOG_TYPE_EC_EVENT, EC_EVENT_BATTERY); #endif } diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 7c54a79..5c94548 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -88,7 +88,7 @@ #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> #include "cpu/amd/model_fxx/init_cpus.c" -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) #include "cpu/amd/model_fxx/fidvid.c" #endif @@ -128,14 +128,14 @@ setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif ht_setup_chains_x(sysinfo); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ struct cpuid_result cpuid1 = cpuid(0x80000007); @@ -191,7 +191,7 @@ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); memreset_setup(); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) init_timer(); // Need to use TMICT to synchronize FID/VID #endif sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c index 3a784e7..86affe8 100644 --- a/src/mainboard/hp/dl145_g3/mptable.c +++ b/src/mainboard/hp/dl145_g3/mptable.c @@ -29,7 +29,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdk8_sysconf.h> diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 0dcc6e5..ef6890d 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -152,7 +152,7 @@ setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, @@ -166,7 +166,7 @@ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn bcm5785_early_setup(); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) { msr_t msr; msr = rdmsr(0xc0010042); diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c index 17e42e4..b1c91c8 100644 --- a/src/mainboard/hp/dl165_g6_fam10/mptable.c +++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c @@ -29,7 +29,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdfam10_sysconf.h> diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index d282e34..96619ed 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -152,7 +152,7 @@ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -160,7 +160,7 @@ wait_all_other_cores_started(bsp_apicid); #endif -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 48258ca..709c81f 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -169,7 +169,7 @@ #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 1731ef4..7417c1a 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -139,7 +139,7 @@ */ wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS + #if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -153,7 +153,7 @@ rs780_early_setup(); sb7xx_51xx_early_setup(); - #if CONFIG_SET_FIDVID + #if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index a532ab0..e3a52fa 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -74,7 +74,7 @@ gnvs->tpmp = 1; -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Emerald Lake has no EC (?) */ gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; #endif diff --git a/src/mainboard/intel/bayleybay_fsp/mainboard.c b/src/mainboard/intel/bayleybay_fsp/mainboard.c index 67bee39..ea57c93 100644 --- a/src/mainboard/intel/bayleybay_fsp/mainboard.c +++ b/src/mainboard/intel/bayleybay_fsp/mainboard.c @@ -21,7 +21,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif #include <pc80/mc146818rtc.h> diff --git a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c index 58da036..393fad8 100644 --- a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c +++ b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c @@ -21,7 +21,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif #include <pc80/mc146818rtc.h> diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index bf5b738..96c22ea 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -213,7 +213,7 @@ pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); post_code(0x46); if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Resume from S3 detected.\n"); boot_mode = 2; /* Clear SLP_TYPE. This will break stage2 but @@ -261,7 +261,7 @@ post_code(0x49); -#if CONFIG_USBDEBUG +#if IS_ENABLED(CONFIG_USBDEBUG) /* FSP reconfigures USB, so reinit it to have debug */ early_usbdebug_init(); #endif diff --git a/src/mainboard/intel/eagleheights/fadt.c b/src/mainboard/intel/eagleheights/fadt.c index 7d0e8a3..eaea7f7 100644 --- a/src/mainboard/intel/eagleheights/fadt.c +++ b/src/mainboard/intel/eagleheights/fadt.c @@ -62,7 +62,7 @@ fadt->dsdt = (unsigned long) dsdt; fadt->preferred_pm_profile = 7; /* Performance Server */ fadt->sci_int = 0x9; -#if CONFIG_HAVE_SMI_HANDLER +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) fadt->smi_cmd = APM_CNT; #else fadt->smi_cmd = 0x00; diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c index b1fcdd1..74770d4 100644 --- a/src/mainboard/iwill/dk8_htx/mptable.c +++ b/src/mainboard/iwill/dk8_htx/mptable.c @@ -4,7 +4,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdk8_sysconf.h> diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 9d29ae2..47d2619 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -99,7 +99,7 @@ setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, @@ -112,7 +112,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) { msr_t msr; msr = rdmsr(0xc0010042); diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index f540a73..23f2892 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -144,7 +144,7 @@ */ wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS + #if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -158,7 +158,7 @@ rs780_early_setup(); sb7xx_51xx_early_setup(); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index 7769647..8470ae1 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -91,7 +91,7 @@ setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index b82102a..5a697f0 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -21,7 +21,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif #include <pc80/mc146818rtc.h> @@ -31,7 +31,7 @@ #include <boot/coreboot_tables.h> #include <southbridge/intel/bd82x6x/pch.h> -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) static int int15_handler(void) { int res = 0; @@ -164,7 +164,8 @@ static void mainboard_enable(device_t dev) { -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) || \ + IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); #endif diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index eda1a4d..80b91ba 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -169,7 +169,7 @@ #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 1a5c17c..2d35650 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -94,7 +94,7 @@ /* Check for S3 resume. */ const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04); if (((pm1_cnt >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Resume from S3 detected.\n"); s3resume = 1; /* Clear SLP_TYPE. This will break stage2 but diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 02f7116..e3f4686 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -89,7 +89,7 @@ /* Check for S3 resume. */ const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04); if (((pm1_cnt >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Resume from S3 detected.\n"); s3resume = 1; /* Clear SLP_TYPE. This will break stage2 but diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 7634de8..e8312d7 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -286,7 +286,7 @@ else quick_ram_check(); -#if CONFIG_LPC_TPM +#if IS_ENABLED(CONFIG_LPC_TPM) init_tpm(s3resume); #endif } diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c index d44cbf3..e7fcbda 100644 --- a/src/mainboard/lippert/frontrunner/romstage.c +++ b/src/mainboard/lippert/frontrunner/romstage.c @@ -50,7 +50,7 @@ if (device != DIMM0) return 0xFF; /* No DIMM1, don't even try. */ -#if CONFIG_DEBUG_SMBUS +#if IS_ENABLED(CONFIG_DEBUG_SMBUS) if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) { printk(BIOS_ERR, "ERROR: spd_read_byte(DIMM0, 0x%02x) " "returns 0xff\n", address); diff --git a/src/mainboard/lippert/hurricane-lx/mainboard.c b/src/mainboard/lippert/hurricane-lx/mainboard.c index 3d32113..0f210cb 100644 --- a/src/mainboard/lippert/hurricane-lx/mainboard.c +++ b/src/mainboard/lippert/hurricane-lx/mainboard.c @@ -25,7 +25,7 @@ #include <device/pci_ids.h> /* Bit1 switches Com1 to RS485, bit2 same for Com2. */ -#if CONFIG_ONBOARD_UARTS_RS485 +#if IS_ENABLED(CONFIG_ONBOARD_UARTS_RS485) #define SIO_GP1X_CONFIG 0x06 #else #define SIO_GP1X_CONFIG 0x00 @@ -54,7 +54,7 @@ outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD# outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM# outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM# -#if !CONFIG_BOARD_OLD_REVISION +#if !IS_ENABLED(CONFIG_BOARD_OLD_REVISION) outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz #endif diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index b76960f..9d7b565 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -48,7 +48,7 @@ return smbus_read_byte(device, address); } -#if !CONFIG_BOARD_OLD_REVISION +#if !IS_ENABLED(CONFIG_BOARD_OLD_REVISION) /* Send config data to System Management Controller via SMB. */ static int smc_send_config(unsigned char config_data) { @@ -79,7 +79,7 @@ 0x042C, // disable ATXPG; VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 enabled 0x1423, // don't delay PoWeROK1/2 0x9072, // watchdog triggers PWROK, counts seconds -#if !CONFIG_USE_WATCHDOG_ON_BOOT +#if !IS_ENABLED(CONFIG_USE_WATCHDOG_ON_BOOT) 0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0 #endif 0xBF25, 0x172A, 0xF326, // select GPIO function for most pins @@ -88,7 +88,7 @@ 0x07C0, // enable Simple-I/O for GP12-10= RS485_EN2,1, WD_ACTIVE 0x06C8, // config GP12,11 as output, GP10 as input 0x2DF5, // map Hw Monitor Thermal Output to GP55 -#if CONFIG_BOARD_OLD_REVISION +#if IS_ENABLED(CONFIG_BOARD_OLD_REVISION) 0x1F2A, 0xC072, // switch GP13 to GPIO, WDT output from PWROK to KRST #endif }; @@ -132,7 +132,7 @@ cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); -#if !CONFIG_BOARD_OLD_REVISION +#if !IS_ENABLED(CONFIG_BOARD_OLD_REVISION) int err; /* bit0 = Spread Spectrum */ if ((err = smc_send_config(SMC_CONFIG))) { diff --git a/src/mainboard/lippert/literunner-lx/mainboard.c b/src/mainboard/lippert/literunner-lx/mainboard.c index e4084b5..11f9e14 100644 --- a/src/mainboard/lippert/literunner-lx/mainboard.c +++ b/src/mainboard/lippert/literunner-lx/mainboard.c @@ -25,7 +25,7 @@ #include <device/pci_ids.h> /* Bit0 turns off the Live LED, bit1 switches Com1 to RS485, bit2 same for Com2. */ -#if CONFIG_ONBOARD_UARTS_RS485 +#if IS_ENABLED(CONFIG_ONBOARD_UARTS_RS485) #define SIO_GP1X_CONFIG 0x07 #else #define SIO_GP1X_CONFIG 0x01 diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index e83924c..1474ecd 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -38,7 +38,7 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) /* Bit0 enables Spread Spectrum, bit1 makes on-board CF slot act as IDE slave. */ -#if CONFIG_ONBOARD_IDE_SLAVE +#if IS_ENABLED(CONFIG_ONBOARD_IDE_SLAVE) #define SMC_CONFIG 0x03 #else #define SMC_CONFIG 0x01 @@ -79,7 +79,7 @@ if (device != DIMM0) return 0xFF; /* No DIMM1, don't even try. */ -#if CONFIG_DEBUG_SMBUS +#if IS_ENABLED(CONFIG_DEBUG_SMBUS) if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) printk(BIOS_ERR, "ERROR: spd_read_byte(DIMM0, 0x%02x) " "returns 0xff\n", address); @@ -118,7 +118,7 @@ 0x072C, // VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal 0x1423, // don't delay PoWeROK1/2 0x9072, // watchdog triggers PWROK, counts seconds -#if !CONFIG_USE_WATCHDOG_ON_BOOT +#if !IS_ENABLED(CONFIG_USE_WATCHDOG_ON_BOOT) 0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0 #endif 0xBF25, 0x172A, 0xF326, // select GPIO function for most pins diff --git a/src/mainboard/lippert/roadrunner-lx/mainboard.c b/src/mainboard/lippert/roadrunner-lx/mainboard.c index 1d35ebe..b922e78 100644 --- a/src/mainboard/lippert/roadrunner-lx/mainboard.c +++ b/src/mainboard/lippert/roadrunner-lx/mainboard.c @@ -25,7 +25,7 @@ #include <device/pci_ids.h> /* Bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off the Live LED. */ -#if CONFIG_ONBOARD_UARTS_RS485 +#if IS_ENABLED(CONFIG_ONBOARD_UARTS_RS485) #define SIO_GP1X_CONFIG 0x26 #else #define SIO_GP1X_CONFIG 0x20 diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 6ba90d7..8341178 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -55,7 +55,7 @@ 0x1E2C, // disable ATXPG; VIN6,FAN4/5,VIN3 enabled, VIN7 internal 0x1423, // don't delay PoWeROK1/2 - triggers 2nd reset 0x9072, // watchdog triggers PWROK, counts seconds -#if !CONFIG_USE_WATCHDOG_ON_BOOT +#if !IS_ENABLED(CONFIG_USE_WATCHDOG_ON_BOOT) 0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0 #endif 0xBF25, 0x372A, 0xF326, // select GPIO function for most pins diff --git a/src/mainboard/lippert/spacerunner-lx/mainboard.c b/src/mainboard/lippert/spacerunner-lx/mainboard.c index b0bc74e..594545d 100644 --- a/src/mainboard/lippert/spacerunner-lx/mainboard.c +++ b/src/mainboard/lippert/spacerunner-lx/mainboard.c @@ -25,7 +25,7 @@ #include <device/pci_ids.h> /* Bit0 turns off the Live LED, bit1 switches Com1 to RS485, bit2 same for Com2. */ -#if CONFIG_ONBOARD_UARTS_RS485 +#if IS_ENABLED(CONFIG_ONBOARD_UARTS_RS485) #define SIO_GP1X_CONFIG 0x07 #else #define SIO_GP1X_CONFIG 0x01 diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index c77d82f..a73276e 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -38,7 +38,7 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) /* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */ -#if CONFIG_ONBOARD_IDE_SLAVE +#if IS_ENABLED(CONFIG_ONBOARD_IDE_SLAVE) #define SMC_CONFIG 0x03 #else #define SMC_CONFIG 0x01 @@ -79,7 +79,7 @@ if (device != DIMM0) return 0xFF; /* No DIMM1, don't even try. */ -#if CONFIG_DEBUG_SMBUS +#if IS_ENABLED(CONFIG_DEBUG_SMBUS) if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) { printk(BIOS_ERR, "ERROR: spd_read_byte(DIMM0, 0x%02x) " "returns 0xff\n", address); @@ -119,7 +119,7 @@ 0x072C, // VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal 0x1423, // don't delay PoWeROK1/2 0x9072, // watchdog triggers PWROK, counts seconds -#if !CONFIG_USE_WATCHDOG_ON_BOOT +#if !IS_ENABLED(CONFIG_USE_WATCHDOG_ON_BOOT) 0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0 #endif 0xBF25, 0x172A, 0xF326, // select GPIO function for most pins -- To view, visit https://review.coreboot.org/20343 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1f906c8c465108017bc4d08534653233078ef32d Gerrit-Change-Number: 20343 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: mainboard/[a-e]: add IS_ENABLED() around Kconfig symbol refe...
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20342 Change subject: mainboard/[a-e]: add IS_ENABLED() around Kconfig symbol references ...................................................................... mainboard/[a-e]: add IS_ENABLED() around Kconfig symbol references Change-Id: Icca8bac5e67f83dfc5a8f5ef1cb87c6432e0a236 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/advansus/a785e-i/get_bus_conf.c M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/bettong/BiosCallOuts.c M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/amd/dbm690t/romstage.c M src/mainboard/amd/dinar/rd890_cfg.h M src/mainboard/amd/dinar/sb700_cfg.h M src/mainboard/amd/gardenia/BiosCallOuts.c M src/mainboard/amd/inagua/broadcom.c M src/mainboard/amd/mahogany/romstage.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/parmer/buildOpts.c M src/mainboard/amd/pistachio/romstage.c M src/mainboard/amd/serengeti_cheetah/mptable.c M src/mainboard/amd/serengeti_cheetah/romstage.c M src/mainboard/amd/serengeti_cheetah_fam10/mptable.c M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c M src/mainboard/amd/thatcher/buildOpts.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/amd/torpedo/Oem.h M src/mainboard/amd/torpedo/platform_cfg.h M src/mainboard/aopen/dxplplusu/romstage.c M src/mainboard/apple/macbook21/gpio.c M src/mainboard/apple/macbook21/hda_verb.c M src/mainboard/asrock/939a785gmh/romstage.c M src/mainboard/asus/a8n_e/romstage.c M src/mainboard/asus/a8v-e_deluxe/romstage.c M src/mainboard/asus/a8v-e_se/romstage.c M src/mainboard/asus/f2a85-m/acpi/routing.asl M src/mainboard/asus/f2a85-m/buildOpts.c M src/mainboard/asus/k8v-x/romstage.c M src/mainboard/asus/kcma-d8/bootblock.c M src/mainboard/asus/kfsn4-dre/bootblock.c M src/mainboard/asus/kfsn4-dre_k8/bootblock.c M src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c M src/mainboard/asus/kgpe-d16/bootblock.c M src/mainboard/asus/m2n-e/romstage.c M src/mainboard/asus/m2v-mx_se/romstage.c M src/mainboard/asus/m2v/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/get_bus_conf.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/avalue/eax-785e/get_bus_conf.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/broadcom/blast/mptable.c M src/mainboard/broadcom/blast/romstage.c M src/mainboard/dmp/vortex86ex/romstage.c M src/mainboard/emulation/qemu-i440fx/northbridge.c 49 files changed, 98 insertions(+), 95 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/20342/1 diff --git a/src/mainboard/advansus/a785e-i/get_bus_conf.c b/src/mainboard/advansus/a785e-i/get_bus_conf.c index 9bd7c25..ed46359 100644 --- a/src/mainboard/advansus/a785e-i/get_bus_conf.c +++ b/src/mainboard/advansus/a785e-i/get_bus_conf.c @@ -21,7 +21,7 @@ #include <stdlib.h> #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam10_sysconf.h> -#if CONFIG_AMD_SB_CIMX +#if IS_ENABLED(CONFIG_AMD_SB_CIMX) #include <sb_cimx.h> #endif @@ -128,7 +128,7 @@ apicid_base = CONFIG_MAX_PHYSICAL_CPUS; apicid_sb800 = apicid_base + 0; -#if CONFIG_AMD_SB_CIMX +#if IS_ENABLED(CONFIG_AMD_SB_CIMX) sb_Late_Post(); #endif } diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index f145c25..7161903 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -144,7 +144,7 @@ */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -158,7 +158,7 @@ rs780_early_setup(); sb800_early_setup(); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); post_code(0x39); diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index e5eed05..7073ec7 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -83,7 +83,7 @@ #endif /* XHCI configuration */ -#if CONFIG_HUDSON_XHCI_ENABLE +#if IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE) FchParams_env->Usb.Xhci0Enable = TRUE; #else FchParams_env->Usb.Xhci0Enable = FALSE; diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index cdb12e3..53cc648 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -136,7 +136,7 @@ */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -150,7 +150,7 @@ rs780_early_setup(); sb800_early_setup(); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index b4a3d12..5c841cb 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -88,7 +88,7 @@ setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/amd/dinar/rd890_cfg.h b/src/mainboard/amd/dinar/rd890_cfg.h index 8645553..ac3c818 100644 --- a/src/mainboard/amd/dinar/rd890_cfg.h +++ b/src/mainboard/amd/dinar/rd890_cfg.h @@ -28,10 +28,10 @@ * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. */ #ifndef DEFAULT_HT_PATH -#if CONFIG_CPU_AMD_AGESA_FAMILY10 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10) #define DEFAULT_HT_PATH {0x0, 0x3} #endif -#if CONFIG_CPU_AMD_AGESA_FAMILY15 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15) #define DEFAULT_HT_PATH {0x0, 0x1} #endif #endif diff --git a/src/mainboard/amd/dinar/sb700_cfg.h b/src/mainboard/amd/dinar/sb700_cfg.h index 02c3934..1896d11 100644 --- a/src/mainboard/amd/dinar/sb700_cfg.h +++ b/src/mainboard/amd/dinar/sb700_cfg.h @@ -36,13 +36,13 @@ * before AGESA module get call. */ #ifndef BIOS_SIZE -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 +#if IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_1024) #define BIOS_SIZE BIOS_SIZE_1M -#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_2048) #define BIOS_SIZE BIOS_SIZE_2M -#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_4096) #define BIOS_SIZE BIOS_SIZE_4M -#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_8192) #define BIOS_SIZE BIOS_SIZE_8M #endif #endif diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c index 23ce0c6..09cac71 100644 --- a/src/mainboard/amd/gardenia/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/BiosCallOuts.c @@ -100,7 +100,7 @@ #endif /* XHCI configuration */ -#if CONFIG_HUDSON_XHCI_ENABLE +#if IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE) FchParams_env->Usb.Xhci0Enable = TRUE; #else FchParams_env->Usb.Xhci0Enable = FALSE; diff --git a/src/mainboard/amd/inagua/broadcom.c b/src/mainboard/amd/inagua/broadcom.c index 9f140a2..f1c49d2 100644 --- a/src/mainboard/amd/inagua/broadcom.c +++ b/src/mainboard/amd/inagua/broadcom.c @@ -37,7 +37,7 @@ #define be(x) cpu_to_be32(x) //this is used a lot! /* C forces us to specify these before defining struct selfboot_patch :-( */ -#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF +#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF) #define INIT1_LENGTH 9 #define INIT2_LENGTH 10 #define INIT3_LENGTH 3 @@ -179,7 +179,7 @@ .powerdown.padding = be16(0x0000), /* Only the lines below may be adapted to your needs ... */ -#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF +#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF) .header.mac_addr = { 0x00, 0x10, 0x18, 0x00, 0x00, 0x00 }, //Broadcom .header.subsys_device = be16(0x1699), //same as pci_device .header.subsys_vendor = be16(0x14E4), //Broadcom @@ -189,7 +189,7 @@ .header.subsys_vendor = be16(0x121D), //LiPPERT #endif .header.pci_device = be16(0x1699), //Broadcom 5785 with GbE PHY -#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF +#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF) .header.patch_version = be16(0x010B), //1.11 (Broadcom's sb5785m1.11) #else .header.patch_version = be16(0x110B), //1.11b, i.e. hacked :-) @@ -208,7 +208,7 @@ * 1 X 0 | 0x330C5180 - - - * 1 X 1 | 0x391C6140 - - - */ -#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF +#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF) .header.basic_config = be16(0x0404), //original for B50610 #else .header.basic_config = be16(0x0604), //bit 9 set so not to mess up PHY regs, kept other bits unchanged @@ -244,7 +244,7 @@ * was added, for reference see Broadcom's changelog. */ .init.hunk1_code = { -#if CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF +#if IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF) be(0x082B8104), //CFR-AF: PHY0B: KSZ9021 select PHY104 be(0x082CF0F0), //CFR-AF: PHY0C: KSZ9021 clk/ctl skew (advised by Micrel) be(0x082B8105), //CFR-AF: PHY0B: KSZ9021 select PHY105 @@ -258,7 +258,7 @@ .init.hunk2_when = 0x30, //after global reset, PHY reset .init.hunk2_code = { -#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF +#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF) be(0x08370F08), //v1.06 : PHY17: B50610 select reg. 08 be(0x08350001), //v1.06 : PHY15: B50610 slow link fix be(0x08370F00), //v1.06 : PHY17: B50610 disable reg. 08 @@ -275,20 +275,20 @@ be(0xC1F03604), be(0xFFE0FFFF), be(0x00110000), //v1.08 : 3604.20-16: 10Mb clock = 12.5MHz }, //-->INIT3_LENGTH! -#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF +#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF) .init.hunk4_when = 0xD8, //original for B50610 #else .init.hunk4_when = 0x80, //run last, after Linux' "ifconfig up" #endif .init.hunk4_code = { -#if CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF +#if IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF) be(0x083F4300), //CFR-AF: PHY1F: IRQ active high be(0x083C0000), //CFR-AF: PHY1C: revert driver writes be(0x08380000), //CFR-AF: PHY18| be(0x083C0000), //CFR-AF: PHY1C| #endif be(0xCB0005A4), be(0xF7F0000C), //v1.01 : if 5A4.0 == 1 -->skip next 12 bytes -#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF +#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF) be(0xC61005A4), be(0x3210C500), //v1.01 : 5A4: PHY LED mode #else be(0xC61005A4), be(0x331C71CE), //CFR-AF: 5A4: fake LED mode @@ -300,7 +300,7 @@ .powerdown.hunk1_when = 0x50, //prior to IDDQ MAC .powerdown.hunk1_code = { -#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF +#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF) be(0x083CB001), //v1.10 : PHY1C: IDDQ B50610 PHY #endif be(0xF7F30116), // IDDQ PHY diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index a8e54d5..86cb9ab 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -91,7 +91,7 @@ setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index efb2885..0393822 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -141,7 +141,7 @@ */ wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS + #if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -155,7 +155,7 @@ rs780_early_setup(); sb7xx_51xx_early_setup(); - #if CONFIG_SET_FIDVID + #if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 8ba3c53..49a9feb 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -154,7 +154,7 @@ #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 2008619..7f04e7f 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -87,7 +87,7 @@ setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c index fc421a9..0210368 100644 --- a/src/mainboard/amd/serengeti_cheetah/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah/mptable.c @@ -17,7 +17,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdk8_sysconf.h> diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 73a1e9f..17ac940 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -104,7 +104,7 @@ struct sys_info *sysinfo = &sysinfo_car; int needs_reset; unsigned bsp_apicid = 0; -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) struct cpuid_result cpuid1; #endif @@ -127,7 +127,7 @@ setup_coherent_ht_domain(); /* routing table and start other core0 */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched */ /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, @@ -140,7 +140,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); /* it will init sblnk and sbbusn, nodes, sbdn */ -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ cpuid1 = cpuid(0x80000007); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c index d800051..048e800 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c @@ -19,7 +19,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdfam10_sysconf.h> diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 831e050..e130ebd 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -242,7 +242,7 @@ */ wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS + #if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -252,7 +252,7 @@ post_code(0x38); - #if CONFIG_SET_FIDVID + #if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index 8ed3bf2..7bc5a77 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -154,7 +154,7 @@ #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 022e91d..92fee45 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -137,7 +137,7 @@ */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -151,7 +151,7 @@ rs780_early_setup(); sb7xx_51xx_early_setup(); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h index 0910ddc..f8f9d80 100644 --- a/src/mainboard/amd/torpedo/Oem.h +++ b/src/mainboard/amd/torpedo/Oem.h @@ -16,7 +16,7 @@ #define BIOS_SIZE 0x04 //04 - 1MB #endif #define LEGACY_FREE 0x00 -#if !CONFIG_ONBOARD_USB30 +#if !IS_ENABLED(CONFIG_ONBOARD_USB30) #define XHCI_SUPPORT 0x01 #endif diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h index 0713e41..72a97d1 100644 --- a/src/mainboard/amd/torpedo/platform_cfg.h +++ b/src/mainboard/amd/torpedo/platform_cfg.h @@ -294,7 +294,7 @@ #define INCHIP_USB_CINFIG 0x7F #define INCHIP_USB_OHCI1_CINFIG 0x01 #define INCHIP_USB_OHCI2_CINFIG 0x01 -#if CONFIG_ONBOARD_USB30 +#if IS_ENABLED(CONFIG_ONBOARD_USB30) #define INCHIP_USB_OHCI3_CINFIG 0x00 #else #define INCHIP_USB_OHCI3_CINFIG 0x01 @@ -962,7 +962,7 @@ * @li <b>0</b> - Disable * @li <b>1</b> - Enable */ -#if CONFIG_ONBOARD_USB30 +#if IS_ENABLED(CONFIG_ONBOARD_USB30) #define SB_XHCI_SWITCH 0 #else #define SB_XHCI_SWITCH 1 diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 3fba1ad..f79d3d3 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -65,8 +65,8 @@ * is lost. Only return addresses from main() and * scrub_ecc() are recovered to stack via xmm0-xmm3. */ -#if CONFIG_HW_SCRUBBER -#if !CONFIG_USBDEBUG_IN_ROMSTAGE +#if IS_ENABLED(CONFIG_HW_SCRUBBER) +#if !IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) unsigned long ret_addr = (unsigned long)((unsigned long*)&bist - 1); e7505_mch_scrub_ecc(ret_addr); #endif diff --git a/src/mainboard/apple/macbook21/gpio.c b/src/mainboard/apple/macbook21/gpio.c index 53c5c96..19296a7 100644 --- a/src/mainboard/apple/macbook21/gpio.c +++ b/src/mainboard/apple/macbook21/gpio.c @@ -56,7 +56,8 @@ }; static const struct pch_gpio_set1 pch_gpio_set1_level = { -#if (CONFIG_BOARD_APPLE_MACBOOK11 || CONFIG_BOARD_APPLE_MACBOOK21) +#if IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK11) || \ + IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK21) .gpio5 = GPIO_LEVEL_LOW, #else /* CONFIG_BOARD_APPLE_IMAC52 */ .gpio5 = GPIO_LEVEL_HIGH, @@ -71,7 +72,8 @@ static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, .gpio7 = GPIO_INVERT, -#if (CONFIG_BOARD_APPLE_MACBOOK11 || CONFIG_BOARD_APPLE_MACBOOK21) +#if IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK11) || \ + IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK21) .gpio13 = GPIO_INVERT, #endif }; @@ -80,7 +82,7 @@ }; static const struct pch_gpio_set2 pch_gpio_set2_mode = { -#if CONFIG_BOARD_APPLE_IMAC52 +#if IS_ENABLED(CONFIG_BOARD_APPLE_IMAC52) .gpio35 = GPIO_MODE_GPIO, #endif .gpio38 = GPIO_MODE_GPIO, @@ -89,7 +91,7 @@ }; static const struct pch_gpio_set2 pch_gpio_set2_direction = { -#if CONFIG_BOARD_APPLE_IMAC52 +#if IS_ENABLED(CONFIG_BOARD_APPLE_IMAC52) .gpio35 = GPIO_DIR_OUTPUT, #endif .gpio38 = GPIO_DIR_OUTPUT, @@ -98,7 +100,7 @@ }; static const struct pch_gpio_set2 pch_gpio_set2_level = { -#if CONFIG_BOARD_APPLE_IMAC52 +#if IS_ENABLED(CONFIG_BOARD_APPLE_IMAC52) .gpio35 = GPIO_LEVEL_LOW, #endif .gpio38 = GPIO_LEVEL_HIGH, diff --git a/src/mainboard/apple/macbook21/hda_verb.c b/src/mainboard/apple/macbook21/hda_verb.c index e0fc92e..9ae5cf8 100644 --- a/src/mainboard/apple/macbook21/hda_verb.c +++ b/src/mainboard/apple/macbook21/hda_verb.c @@ -19,7 +19,8 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x83847680, /* Codec Vendor / Device ID: SigmaTel STAC9221 A1 */ -#if CONFIG_BOARD_APPLE_MACBOOK11 || CONFIG_BOARD_APPLE_MACBOOK21 +#if IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK11) || \ + IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK21) 0x106b2200, /* Subsystem ID */ 0x0000000B, /* Number of 4 dword sets */ diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index bd74fde..c88f027 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -157,7 +157,7 @@ setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index 5a3b1f6..dd76d8e 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -114,7 +114,7 @@ needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched. */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index a19b46a..7b27ed9 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -173,7 +173,7 @@ printk(BIOS_INFO, "now booting... Core0 started\n"); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched. */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 706b859..dbce83e 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -173,7 +173,7 @@ printk(BIOS_INFO, "now booting... Core0 started\n"); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched. */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl index cc36dcd..af8532f 100644 --- a/src/mainboard/asus/f2a85-m/acpi/routing.asl +++ b/src/mainboard/asus/f2a85-m/acpi/routing.asl @@ -46,7 +46,7 @@ /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ -#if CONFIG_BOARD_ASUS_F2A85_M_PRO +#if IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO) Package(){0x000FFFFF, 0, INTA, 0 }, Package(){0x000FFFFF, 1, INTB, 0 }, Package(){0x000FFFFF, 2, INTC, 0 }, diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index e0a1ea4..ab9e151 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -168,7 +168,7 @@ #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 1df033a..8fad0b4 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -128,7 +128,7 @@ printk(BIOS_INFO, "now booting... Core0 started\n"); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched. */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/asus/kcma-d8/bootblock.c b/src/mainboard/asus/kcma-d8/bootblock.c index 6f2c0a1..4e8a790 100644 --- a/src/mainboard/asus/kcma-d8/bootblock.c +++ b/src/mainboard/asus/kcma-d8/bootblock.c @@ -33,7 +33,7 @@ pci_io_write_config8(PCI_DEV(0, 0x14, 0), 0x56, byte); recovery_enabled = (!(pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1)); if (recovery_enabled) { -#if CONFIG_USE_OPTION_TABLE +#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) /* Clear NVRAM checksum */ for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) { cmos_write(0x0, addr); diff --git a/src/mainboard/asus/kfsn4-dre/bootblock.c b/src/mainboard/asus/kfsn4-dre/bootblock.c index b25b34f..454443f 100644 --- a/src/mainboard/asus/kfsn4-dre/bootblock.c +++ b/src/mainboard/asus/kfsn4-dre/bootblock.c @@ -62,7 +62,7 @@ recovery_enabled = bootblock_read_recovery_jumper(GPIO_DEV); if (recovery_enabled) { -#if CONFIG_USE_OPTION_TABLE +#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) /* Clear NVRAM checksum */ for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) { cmos_write(0x0, addr); diff --git a/src/mainboard/asus/kfsn4-dre_k8/bootblock.c b/src/mainboard/asus/kfsn4-dre_k8/bootblock.c index b25b34f..454443f 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/bootblock.c +++ b/src/mainboard/asus/kfsn4-dre_k8/bootblock.c @@ -62,7 +62,7 @@ recovery_enabled = bootblock_read_recovery_jumper(GPIO_DEV); if (recovery_enabled) { -#if CONFIG_USE_OPTION_TABLE +#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) /* Clear NVRAM checksum */ for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) { cmos_write(0x0, addr); diff --git a/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c index 101997a..6548d47 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c +++ b/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c @@ -24,7 +24,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #include <cpu/amd/multicore.h> #endif #include <stdlib.h> diff --git a/src/mainboard/asus/kgpe-d16/bootblock.c b/src/mainboard/asus/kgpe-d16/bootblock.c index 6f2c0a1..4e8a790 100644 --- a/src/mainboard/asus/kgpe-d16/bootblock.c +++ b/src/mainboard/asus/kgpe-d16/bootblock.c @@ -33,7 +33,7 @@ pci_io_write_config8(PCI_DEV(0, 0x14, 0), 0x56, byte); recovery_enabled = (!(pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1)); if (recovery_enabled) { -#if CONFIG_USE_OPTION_TABLE +#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) /* Clear NVRAM checksum */ for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) { cmos_write(0x0, addr); diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 915ca84..7cfdcfb 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -134,7 +134,7 @@ setup_coherent_ht_domain(); /* Routing table and start other core0. */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* * It is said that we should start core1 after all core0 launched * becase optimize_link_coherent_ht is moved out from diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 13113b4..eebf96c 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -139,7 +139,7 @@ printk(BIOS_INFO, "now booting... All core 0 started\n"); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched. */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 61d7488..55d5aca 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -238,7 +238,7 @@ printk(BIOS_INFO, "now booting... All core 0 started\n"); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched. */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 1076bf6..3261fc7 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -141,7 +141,7 @@ */ wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS + #if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -155,7 +155,7 @@ rs780_early_setup(); sb7xx_51xx_early_setup(); - #if CONFIG_SET_FIDVID + #if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 40334d6..a97488e 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -142,7 +142,7 @@ */ wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS + #if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -156,7 +156,7 @@ rs780_early_setup(); sb7xx_51xx_early_setup(); - #if CONFIG_SET_FIDVID + #if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); @@ -244,7 +244,7 @@ */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { -#if !CONFIG_BOARD_ASUS_M4A785TM +#if !IS_ENABLED(CONFIG_BOARD_ASUS_M4A785TM) static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; /* If the BUID was adjusted in early_ht we need to do the manual override */ if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { diff --git a/src/mainboard/asus/m5a88-v/get_bus_conf.c b/src/mainboard/asus/m5a88-v/get_bus_conf.c index 5d32c3a..85daf69 100644 --- a/src/mainboard/asus/m5a88-v/get_bus_conf.c +++ b/src/mainboard/asus/m5a88-v/get_bus_conf.c @@ -21,7 +21,7 @@ #include <stdlib.h> #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam10_sysconf.h> -#if CONFIG_AMD_SB_CIMX +#if IS_ENABLED(CONFIG_AMD_SB_CIMX) #include <sb_cimx.h> #endif @@ -128,7 +128,7 @@ apicid_base = CONFIG_MAX_PHYSICAL_CPUS; apicid_sb800 = apicid_base + 0; -#if CONFIG_AMD_SB_CIMX +#if IS_ENABLED(CONFIG_AMD_SB_CIMX) sb_Late_Post(); #endif } diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index d11f98a..4137e15 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -146,7 +146,7 @@ */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -160,7 +160,7 @@ rs780_early_setup(); sb800_early_setup(); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); post_code(0x39); diff --git a/src/mainboard/avalue/eax-785e/get_bus_conf.c b/src/mainboard/avalue/eax-785e/get_bus_conf.c index 5d32c3a..85daf69 100644 --- a/src/mainboard/avalue/eax-785e/get_bus_conf.c +++ b/src/mainboard/avalue/eax-785e/get_bus_conf.c @@ -21,7 +21,7 @@ #include <stdlib.h> #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam10_sysconf.h> -#if CONFIG_AMD_SB_CIMX +#if IS_ENABLED(CONFIG_AMD_SB_CIMX) #include <sb_cimx.h> #endif @@ -128,7 +128,7 @@ apicid_base = CONFIG_MAX_PHYSICAL_CPUS; apicid_sb800 = apicid_base + 0; -#if CONFIG_AMD_SB_CIMX +#if IS_ENABLED(CONFIG_AMD_SB_CIMX) sb_Late_Post(); #endif } diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 4648310..70dcc40 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -144,7 +144,7 @@ */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -158,7 +158,7 @@ rs780_early_setup(); sb800_early_setup(); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); post_code(0x39); diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c index 81c3049..2417c96 100644 --- a/src/mainboard/broadcom/blast/mptable.c +++ b/src/mainboard/broadcom/blast/mptable.c @@ -4,7 +4,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdk8_sysconf.h> diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index f49f8d3..bb472fb 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -90,7 +90,7 @@ needs_reset = setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c index d2cc146..108cc1d 100644 --- a/src/mainboard/dmp/vortex86ex/romstage.c +++ b/src/mainboard/dmp/vortex86ex/romstage.c @@ -72,25 +72,25 @@ { u32 powerdown_ctrl; powerdown_ctrl = pci_read_config32(SB, 0xbc); -#if CONFIG_TEMP_POWERDOWN +#if IS_ENABLED(CONFIG_TEMP_POWERDOWN) powerdown_ctrl |= (1 << 31); #endif -#if CONFIG_SATA_POWERDOWN +#if IS_ENABLED(CONFIG_SATA_POWERDOWN) powerdown_ctrl |= (1 << 30); #endif -#if CONFIG_ADC_POWERDOWN +#if IS_ENABLED(CONFIG_ADC_POWERDOWN) powerdown_ctrl |= (1 << 28); #endif -#if CONFIG_PCIE0_POWERDOWN +#if IS_ENABLED(CONFIG_PCIE0_POWERDOWN) powerdown_ctrl |= (1 << 13); #endif -#if CONFIG_MAC_POWERDOWN +#if IS_ENABLED(CONFIG_MAC_POWERDOWN) powerdown_ctrl |= (1 << 3); #endif -#if CONFIG_USB1_POWERDOWN +#if IS_ENABLED(CONFIG_USB1_POWERDOWN) powerdown_ctrl |= (1 << 1); #endif -#if CONFIG_IDE_POWERDOWN +#if IS_ENABLED(CONFIG_IDE_POWERDOWN) powerdown_ctrl |= (1 << 0); #endif pci_write_config32(SB, 0xbc, powerdown_ctrl); @@ -169,16 +169,16 @@ static void init_wdt1(void) { -#if CONFIG_WDT1_INITIALIZE -#if CONFIG_WDT1_ENABLE +#if IS_ENABLED(CONFIG_WDT1_INITIALIZE) +#if IS_ENABLED(CONFIG_WDT1_ENABLE) outb(0x1 << 6, 0xa8); #endif u8 wdt1_signal_reg = 0; -#if CONFIG_WDT1_SINGAL_NMI +#if IS_ENABLED(CONFIG_WDT1_SINGAL_NMI) wdt1_signal_reg = 0x0c << 4; -#elif CONFIG_WDT1_SIGNAL_RESET +#elif IS_ENABLED(CONFIG_WDT1_SIGNAL_RESET) wdt1_signal_reg = 0x0d << 4; -#elif CONFIG_WDT1_SIGNAL_SMI +#elif IS_ENABLED(CONFIG_WDT1_SIGNAL_SMI) wdt1_signal_reg = 0x0e << 4; #endif outb(wdt1_signal_reg, 0xa9); diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index d465afe..18dcae3 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -167,7 +167,7 @@ IORESOURCE_ASSIGNED; } -#if CONFIG_GENERATE_SMBIOS_TABLES +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) static int qemu_get_smbios_data16(int handle, unsigned long *current) { struct smbios_type16 *t = (struct smbios_type16 *)*current; @@ -231,7 +231,7 @@ .init = NULL, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, -#if CONFIG_GENERATE_SMBIOS_TABLES +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) .get_smbios_data = qemu_get_smbios_data, #endif }; -- To view, visit https://review.coreboot.org/20342 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icca8bac5e67f83dfc5a8f5ef1cb87c6432e0a236 Gerrit-Change-Number: 20342 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: src/lib: add IS_ENABLED() around Kconfig symbol references
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20341 Change subject: src/lib: add IS_ENABLED() around Kconfig symbol references ...................................................................... src/lib: add IS_ENABLED() around Kconfig symbol references Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: Idcea3f8b1a4246cb6b29999a84a191a3133e5c78 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/lib/cbfs.c M src/lib/coreboot_table.c M src/lib/gcov-glue.c M src/lib/generic_sdram.c M src/lib/hardwaremain.c M src/lib/malloc.c M src/lib/ramtest.c M src/lib/reg_script.c 8 files changed, 39 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/20341/1 diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 11bce2c..596abc5 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -316,7 +316,7 @@ extern const struct cbfs_locator vboot_locator; static const struct cbfs_locator *locators[] = { -#if CONFIG_VBOOT +#if IS_ENABLED(CONFIG_VBOOT) &vboot_locator, #endif &cbfs_master_header_locator, diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index aa6c7a5..eb434cb 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -33,17 +33,17 @@ #include <bootmem.h> #include <spi_flash.h> #include <vboot/vbnv_layout.h> -#if CONFIG_USE_OPTION_TABLE +#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) #include <option_table.h> #endif -#if CONFIG_CHROMEOS -#if CONFIG_HAVE_ACPI_TABLES +#if IS_ENABLED(CONFIG_CHROMEOS) +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) #include <arch/acpi.h> #endif #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif -#if CONFIG_ARCH_X86 +#if IS_ENABLED(CONFIG_ARCH_X86) #include <cpu/x86/mtrr.h> #endif #include <commonlib/helpers.h> @@ -159,7 +159,7 @@ gpios->size += table_size; } -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) static void lb_gpios(struct lb_header *header) { struct lb_gpios *gpios; @@ -200,7 +200,7 @@ static void lb_vdat(struct lb_header *header) { -#if CONFIG_HAVE_ACPI_TABLES +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) struct lb_range *vdat; vdat = (struct lb_range *)lb_new_record(header); @@ -212,7 +212,7 @@ static void lb_vbnv(struct lb_header *header) { -#if CONFIG_PC80_SYSTEM +#if IS_ENABLED(CONFIG_PC80_SYSTEM) struct lb_range *vbnv; vbnv = (struct lb_range *)lb_new_record(header); @@ -223,7 +223,7 @@ #endif } -#if CONFIG_VBOOT +#if IS_ENABLED(CONFIG_VBOOT) static void lb_vboot_handoff(struct lb_header *header) { void *addr; @@ -246,7 +246,7 @@ static void lb_board_id(struct lb_header *header) { -#if CONFIG_BOARD_ID_AUTO || CONFIG_BOARD_ID_MANUAL +#if IS_ENABLED(CONFIG_BOARD_ID_AUTO) || IS_ENABLED(CONFIG_BOARD_ID_MANUAL) struct lb_board_id *bid; bid = (struct lb_board_id *)lb_new_record(header); @@ -359,7 +359,7 @@ return mainboard; } -#if CONFIG_USE_OPTION_TABLE +#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header) { struct lb_record *rec; @@ -475,7 +475,7 @@ head = lb_table_init(rom_table_end); -#if CONFIG_USE_OPTION_TABLE +#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) { struct cmos_option_table *option_table = cbfs_boot_map_with_leak("cmos_layout.bin", @@ -506,10 +506,10 @@ lb_mainboard(head); /* Record the serial ports and consoles */ -#if CONFIG_CONSOLE_SERIAL +#if IS_ENABLED(CONFIG_CONSOLE_SERIAL) uart_fill_lb(head); #endif -#if CONFIG_CONSOLE_USB +#if IS_ENABLED(CONFIG_CONSOLE_USB) lb_add_console(LB_TAG_CONSOLE_EHCI, head); #endif @@ -519,7 +519,7 @@ /* Record our framebuffer */ lb_framebuffer(head); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Record our GPIO settings (ChromeOS specific) */ lb_gpios(head); diff --git a/src/lib/gcov-glue.c b/src/lib/gcov-glue.c index a002ea7..7edc90a 100644 --- a/src/lib/gcov-glue.c +++ b/src/lib/gcov-glue.c @@ -41,7 +41,7 @@ static FILE *fopen(const char *path, const char *mode) { -#if CONFIG_DEBUG_COVERAGE +#if IS_ENABLED(CONFIG_DEBUG_COVERAGE) printk(BIOS_DEBUG, "fopen %s with mode %s\n", path, mode); #endif @@ -74,7 +74,7 @@ static int fclose(FILE *stream) { -#if CONFIG_DEBUG_COVERAGE +#if IS_ENABLED(CONFIG_DEBUG_COVERAGE) printk(BIOS_DEBUG, "fclose %s\n", stream->filename); #endif return 0; @@ -85,7 +85,7 @@ /* fseek should only be called with offset==0 and whence==SEEK_SET * to a freshly opened file. */ gcc_assert(offset == 0 && whence == SEEK_SET); -#if CONFIG_DEBUG_COVERAGE +#if IS_ENABLED(CONFIG_DEBUG_COVERAGE) printk(BIOS_DEBUG, "fseek %s offset=%ld whence=%d\n", stream->filename, offset, whence); #endif @@ -96,7 +96,7 @@ { /* ftell should currently not be called */ gcc_assert(0); -#if CONFIG_DEBUG_COVERAGE +#if IS_ENABLED(CONFIG_DEBUG_COVERAGE) printk(BIOS_DEBUG, "ftell %s\n", stream->filename); #endif return 0; @@ -104,7 +104,7 @@ static size_t fread(void *ptr, size_t size, size_t nmemb, FILE *stream) { -#if CONFIG_DEBUG_COVERAGE +#if IS_ENABLED(CONFIG_DEBUG_COVERAGE) printk(BIOS_DEBUG, "fread: ptr=%p size=%zd nmemb=%zd FILE*=%p\n", ptr, size, nmemb, stream); #endif @@ -113,7 +113,7 @@ static size_t fwrite(const void *ptr, size_t size, size_t nmemb, FILE *stream) { -#if CONFIG_DEBUG_COVERAGE +#if IS_ENABLED(CONFIG_DEBUG_COVERAGE) printk(BIOS_DEBUG, "fwrite: %zd * %zd bytes to file %s\n", nmemb, size, stream->filename); #endif @@ -145,7 +145,7 @@ void __gcov_flush(void); static void coverage_exit(void *unused) { -#if CONFIG_DEBUG_COVERAGE +#if IS_ENABLED(CONFIG_DEBUG_COVERAGE) printk(BIOS_DEBUG, "Syncing coverage data.\n"); #endif __gcov_flush(); diff --git a/src/lib/generic_sdram.c b/src/lib/generic_sdram.c index 801ae61..6aa8d29 100644 --- a/src/lib/generic_sdram.c +++ b/src/lib/generic_sdram.c @@ -1,7 +1,7 @@ #include <lib.h> /* Prototypes */ /* Setup SDRAM */ -#if CONFIG_RAMINIT_SYSINFO +#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO) void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo) #else @@ -13,7 +13,7 @@ for (i = 0; i < controllers; i++) { printk(BIOS_DEBUG, "Ram1.%02x\n", i); - #if CONFIG_RAMINIT_SYSINFO + #if IS_ENABLED(CONFIG_RAMINIT_SYSINFO) sdram_set_registers(ctrl + i, sysinfo); #else sdram_set_registers(ctrl + i); @@ -24,7 +24,7 @@ for (i = 0; i < controllers; i++) { printk(BIOS_DEBUG, "Ram2.%02x\n", i); - #if CONFIG_RAMINIT_SYSINFO + #if IS_ENABLED(CONFIG_RAMINIT_SYSINFO) sdram_set_spd_registers(ctrl + i, sysinfo); #else sdram_set_spd_registers(ctrl + i); @@ -38,7 +38,7 @@ */ printk(BIOS_DEBUG, "Ram3\n"); - #if CONFIG_RAMINIT_SYSINFO + #if IS_ENABLED(CONFIG_RAMINIT_SYSINFO) sdram_enable(controllers, ctrl, sysinfo); #else sdram_enable(controllers, ctrl); diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index a56d68e..0deab4b 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -33,7 +33,7 @@ #include <boot/tables.h> #include <program_loading.h> #include <lib.h> -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) #include <arch/acpi.h> #endif #include <timer.h> @@ -82,7 +82,7 @@ boot_state_t (*run_state)(void *arg); void *arg; int complete : 1; -#if CONFIG_HAVE_MONOTONIC_TIMER +#if IS_ENABLED(CONFIG_HAVE_MONOTONIC_TIMER) struct boot_state_times times; #endif }; @@ -180,7 +180,7 @@ static boot_state_t bs_os_resume_check(void *arg) { -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) void *wake_vector; wake_vector = acpi_find_wakeup_vector(); @@ -199,7 +199,7 @@ static boot_state_t bs_os_resume(void *wake_vector) { -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) arch_bootstate_coreboot_exit(); acpi_resume(wake_vector); #endif @@ -239,7 +239,7 @@ return BS_PAYLOAD_BOOT; } -#if CONFIG_HAVE_MONOTONIC_TIMER +#if IS_ENABLED(CONFIG_HAVE_MONOTONIC_TIMER) static void bs_sample_time(struct boot_state *state) { struct mono_time *mt; @@ -268,7 +268,7 @@ static inline void bs_report_time(struct boot_state *state) {} #endif -#if CONFIG_TIMER_QUEUE +#if IS_ENABLED(CONFIG_TIMER_QUEUE) static void bs_run_timers(int drain) { /* Drain all timer callbacks until none are left, if directed. @@ -473,7 +473,7 @@ post_code(POST_ENTRY_RAMSTAGE); /* Handoff sleep type from romstage. */ -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) acpi_is_wakeup(); #endif diff --git a/src/lib/malloc.c b/src/lib/malloc.c index 9974b2c..b881ed2 100644 --- a/src/lib/malloc.c +++ b/src/lib/malloc.c @@ -2,7 +2,7 @@ #include <console/console.h> #include <cpu/x86/smm.h> -#if CONFIG_DEBUG_MALLOC +#if IS_ENABLED(CONFIG_DEBUG_MALLOC) #define MALLOCDBG(x...) printk(BIOS_SPEW, x) #else #define MALLOCDBG(x...) diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index 419d0eb..2b2c344 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -6,7 +6,7 @@ { // Assembler in lib/ is very ugly. But we properly guarded // it so let's obey this one for now -#if CONFIG_SSE2 +#if IS_ENABLED(CONFIG_SSE2) asm volatile( "movnti %1, (%0)" : /* outputs */ @@ -31,7 +31,7 @@ static void phys_memory_barrier(void) { -#if CONFIG_SSE2 +#if IS_ENABLED(CONFIG_SSE2) // Needed for movnti asm volatile ( "sfence" diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 8d813b6..56285f1 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -22,7 +22,7 @@ #include <stdint.h> #include <reg_script.h> -#if CONFIG_ARCH_X86 +#if IS_ENABLED(CONFIG_ARCH_X86) #include <cpu/x86/msr.h> #endif @@ -369,7 +369,7 @@ static uint64_t reg_script_read_msr(struct reg_script_context *ctx) { -#if CONFIG_ARCH_X86 +#if IS_ENABLED(CONFIG_ARCH_X86) const struct reg_script *step = reg_script_get_step(ctx); msr_t msr = rdmsr(step->reg); uint64_t value = msr.hi; @@ -382,7 +382,7 @@ static void reg_script_write_msr(struct reg_script_context *ctx) { -#if CONFIG_ARCH_X86 +#if IS_ENABLED(CONFIG_ARCH_X86) const struct reg_script *step = reg_script_get_step(ctx); msr_t msr; msr.hi = step->value >> 32; -- To view, visit https://review.coreboot.org/20341 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idcea3f8b1a4246cb6b29999a84a191a3133e5c78 Gerrit-Change-Number: 20341 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: src/ec: add IS_ENABLED() around Kconfig symbol references
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20340 Change subject: src/ec: add IS_ENABLED() around Kconfig symbol references ...................................................................... src/ec: add IS_ENABLED() around Kconfig symbol references Change-Id: Ic2cdfa08cdae9f698eb2f8fa4c4ae061f1a7d903 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/ec/google/chromeec/acpi/ec.asl M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec_lpc.c M src/ec/quanta/ene_kb3940q/ec.c 4 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/20340/1 diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 43520f7..a532492 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -56,7 +56,7 @@ TBMD, 1, // Tablet mode } -#if CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) OperationRegion (EMEM, EmbeddedControl, EC_ACPI_MEM_MAPPED_BEGIN, EC_ACPI_MEM_MAPPED_SIZE) Field (EMEM, ByteAcc, Lock, Preserve) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index e622410..de17495 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -466,7 +466,7 @@ void google_chromeec_log_events(u32 mask) { -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) u8 event; u32 wake_mask; diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 9ead8c8..42a18e4 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -38,7 +38,7 @@ { int i; -#if CONFIG_EC_GOOGLE_CHROMEEC_MEC +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC) /* Access desired range though EMI interface */ if (port >= MEC_EMI_RANGE_START && port <= MEC_EMI_RANGE_END) { mec_io_bytes(0, port, length, dest, csum); @@ -73,7 +73,7 @@ { int i; -#if CONFIG_EC_GOOGLE_CHROMEEC_MEC +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC) /* Access desired range though EMI interface */ if (port >= MEC_EMI_RANGE_START && port <= MEC_EMI_RANGE_END) { mec_io_bytes(1, port, length, msg, csum); @@ -124,7 +124,7 @@ EC_LPC_CMDR_BUSY, 0); } -#if CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) /* Read memmap data through ACPI port 66/62 */ static int read_memmap(u8 *data, u8 offset) { @@ -158,7 +158,7 @@ { u8 id1, id2, flags; -#if CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) if (read_memmap(&id1, EC_MEMMAP_ID) || read_memmap(&id2, EC_MEMMAP_ID + 1) || read_memmap(&flags, EC_MEMMAP_HOST_CMD_FLAGS)) { diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index 8558d3d..b25a51b 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -129,7 +129,7 @@ #ifndef __SMM__ static void ene_kb3940q_log_events(void) { -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) u8 reason = ec_mem_read(EC_SHUTDOWN_REASON); if (reason) elog_add_event_byte(ELOG_TYPE_EC_SHUTDOWN, reason); -- To view, visit https://review.coreboot.org/20340 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic2cdfa08cdae9f698eb2f8fa4c4ae061f1a7d903 Gerrit-Change-Number: 20340 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: drivers/spi: add IS_ENABLED() around Kconfig symbol references
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20339 Change subject: drivers/spi: add IS_ENABLED() around Kconfig symbol references ...................................................................... drivers/spi: add IS_ENABLED() around Kconfig symbol references Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: If80e0c4e1c9911b44853561b03aef1c741255229 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/drivers/spi/adesto.c M src/drivers/spi/amic.c M src/drivers/spi/atmel.c M src/drivers/spi/eon.c M src/drivers/spi/gigadevice.c M src/drivers/spi/macronix.c M src/drivers/spi/spansion.c M src/drivers/spi/spi_flash.c M src/drivers/spi/sst.c M src/drivers/spi/stmicro.c M src/drivers/spi/winbond.c 11 files changed, 35 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/20339/1 diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c index 3e857fc..3e3e7d4 100644 --- a/src/drivers/spi/adesto.c +++ b/src/drivers/spi/adesto.c @@ -90,7 +90,7 @@ cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); @@ -116,7 +116,7 @@ offset += chunk_len; } -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF: adesto: Successfully programmed %zu bytes @" " 0x%lx\n", len, (unsigned long)(offset - len)); #endif diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c index 239681c..64bdab3 100644 --- a/src/drivers/spi/amic.c +++ b/src/drivers/spi/amic.c @@ -72,7 +72,7 @@ cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); @@ -99,7 +99,7 @@ byte_addr = 0; } -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF: AMIC: Successfully programmed %zu bytes @" " 0x%lx\n", len, (unsigned long)(offset - len)); #endif diff --git a/src/drivers/spi/atmel.c b/src/drivers/spi/atmel.c index 07bbf16..d81e0e3 100644 --- a/src/drivers/spi/atmel.c +++ b/src/drivers/spi/atmel.c @@ -118,7 +118,7 @@ cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); @@ -144,7 +144,7 @@ offset += chunk_len; } -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF: Atmel: Successfully programmed %zu bytes @" " 0x%lx\n", len, (unsigned long)(offset - len)); #endif diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index a072e4e..49b56b4 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -95,7 +95,7 @@ cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); @@ -117,7 +117,7 @@ offset += chunk_len; } -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF: EON: Successfully programmed %zu bytes @ %#x\n", len, (unsigned int)(offset - len)); #endif diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index becc215..2d7544c 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -136,7 +136,7 @@ cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "PP gigadevice.c: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, @@ -158,7 +158,7 @@ offset += chunk_len; } -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF gigadevice.c: Successfully programmed %zu bytes @ %#x\n", len, (unsigned int)(offset - len)); diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index fd2d25b..b7f2c49 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -158,7 +158,7 @@ cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); @@ -184,7 +184,7 @@ offset += chunk_len; } -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF: Macronix: Successfully programmed %zu bytes @" " 0x%lx\n", len, (unsigned long)(offset - len)); #endif diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index cb528d3..16c5180 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -212,7 +212,7 @@ cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); @@ -238,7 +238,7 @@ offset += chunk_len; } -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF: SPANSION: Successfully programmed %zu bytes @ 0x%x\n", len, offset); #endif diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index c145379..74187a5 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -185,7 +185,7 @@ spi_flash_addr(offset, cmd); offset += erase_size; -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], cmd[2], cmd[3], offset); #endif @@ -244,38 +244,38 @@ struct spi_flash *flash); } flashes[] = { /* Keep it sorted by define name */ -#if CONFIG_SPI_FLASH_AMIC +#if IS_ENABLED(CONFIG_SPI_FLASH_AMIC) { 0, 0x37, spi_flash_probe_amic, }, #endif -#if CONFIG_SPI_FLASH_ATMEL +#if IS_ENABLED(CONFIG_SPI_FLASH_ATMEL) { 0, 0x1f, spi_flash_probe_atmel, }, #endif -#if CONFIG_SPI_FLASH_EON +#if IS_ENABLED(CONFIG_SPI_FLASH_EON) { 0, 0x1c, spi_flash_probe_eon, }, #endif -#if CONFIG_SPI_FLASH_GIGADEVICE +#if IS_ENABLED(CONFIG_SPI_FLASH_GIGADEVICE) { 0, 0xc8, spi_flash_probe_gigadevice, }, #endif -#if CONFIG_SPI_FLASH_MACRONIX +#if IS_ENABLED(CONFIG_SPI_FLASH_MACRONIX) { 0, 0xc2, spi_flash_probe_macronix, }, #endif -#if CONFIG_SPI_FLASH_SPANSION +#if IS_ENABLED(CONFIG_SPI_FLASH_SPANSION) { 0, 0x01, spi_flash_probe_spansion, }, #endif -#if CONFIG_SPI_FLASH_SST +#if IS_ENABLED(CONFIG_SPI_FLASH_SST) { 0, 0xbf, spi_flash_probe_sst, }, #endif -#if CONFIG_SPI_FLASH_STMICRO +#if IS_ENABLED(CONFIG_SPI_FLASH_STMICRO) { 0, 0x20, spi_flash_probe_stmicro, }, #endif -#if CONFIG_SPI_FLASH_WINBOND +#if IS_ENABLED(CONFIG_SPI_FLASH_WINBOND) { 0, 0xef, spi_flash_probe_winbond, }, #endif /* Keep it sorted by best detection */ -#if CONFIG_SPI_FLASH_STMICRO +#if IS_ENABLED(CONFIG_SPI_FLASH_STMICRO) { 0, 0xff, spi_flash_probe_stmicro, }, #endif -#if CONFIG_SPI_FLASH_ADESTO +#if IS_ENABLED(CONFIG_SPI_FLASH_ADESTO) { 0, 0x1f, spi_flash_probe_adesto, }, #endif }; diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index ce67e9b..559969a 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -153,7 +153,7 @@ offset, }; -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", spi_w8r8(&flash->spi, CMD_SST_RDSR), buf, cmd[0], offset); #endif @@ -208,7 +208,7 @@ cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); @@ -235,7 +235,7 @@ } done: -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF: SST: program %s %zu bytes @ 0x%lx\n", ret ? "failure" : "success", len, (unsigned long)offset - actual); #endif @@ -269,7 +269,7 @@ cmd[3] = offset; for (; actual < len - 1; actual += 2) { -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", spi_w8r8(&flash->spi, CMD_SST_RDSR), buf + actual, cmd[0], offset); @@ -298,7 +298,7 @@ ret = sst_byte_write(flash, offset, buf + actual); done: -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF: SST: program %s %zu bytes @ 0x%lx\n", ret ? "failure" : "success", len, (unsigned long)offset - actual); #endif diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index 68eb37b..240d182 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -186,7 +186,7 @@ cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); @@ -212,7 +212,7 @@ offset += chunk_len; } -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF: STMicro: Successfully programmed %zu bytes @" " 0x%lx\n", len, (unsigned long)(offset - len)); #endif diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 77064ea..2fc8209 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -148,7 +148,7 @@ cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); @@ -174,7 +174,7 @@ offset += chunk_len; } -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) printk(BIOS_SPEW, "SF: Winbond: Successfully programmed %zu bytes @" " 0x%lx\n", len, (unsigned long)(offset - len)); #endif -- To view, visit https://review.coreboot.org/20339 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If80e0c4e1c9911b44853561b03aef1c741255229 Gerrit-Change-Number: 20339 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: src/device: add IS_ENABLED() around Kconfig symbol references
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20338 Change subject: src/device: add IS_ENABLED() around Kconfig symbol references ...................................................................... src/device: add IS_ENABLED() around Kconfig symbol references Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: I66cde1adcf373889b03f144793c0b4f46d21ca31 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/device/device.c M src/device/oprom/realmode/x86.c M src/device/oprom/realmode/x86_interrupts.c M src/device/pci_device.c M src/device/pci_early.c M src/device/pci_rom.c 6 files changed, 23 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/20338/1 diff --git a/src/device/device.c b/src/device/device.c index 0231ec7..35f5909 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -46,7 +46,7 @@ #include <stdlib.h> #include <string.h> #include <smp/spinlock.h> -#if CONFIG_ARCH_X86 +#if IS_ENABLED(CONFIG_ARCH_X86) #include <arch/ebda.h> #endif #include <timer.h> @@ -102,7 +102,7 @@ DECLARE_SPIN_LOCK(dev_lock) -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) /* IGD UMA memory */ uint64_t uma_memory_base = 0; uint64_t uma_memory_size = 0; @@ -1130,7 +1130,7 @@ return; if (!dev->initialized && dev->ops && dev->ops->init) { -#if CONFIG_HAVE_MONOTONIC_TIMER +#if IS_ENABLED(CONFIG_HAVE_MONOTONIC_TIMER) struct stopwatch sw; stopwatch_init(&sw); #endif @@ -1142,7 +1142,7 @@ printk(BIOS_DEBUG, "%s init ...\n", dev_path(dev)); dev->initialized = 1; dev->ops->init(dev); -#if CONFIG_HAVE_MONOTONIC_TIMER +#if IS_ENABLED(CONFIG_HAVE_MONOTONIC_TIMER) printk(BIOS_DEBUG, "%s init finished in %ld usecs\n", dev_path(dev), stopwatch_duration_usecs(&sw)); #endif @@ -1178,7 +1178,7 @@ printk(BIOS_INFO, "Initializing devices...\n"); -#if CONFIG_ARCH_X86 +#if IS_ENABLED(CONFIG_ARCH_X86) /* Ensure EBDA is prepared before Option ROMs. */ setup_default_ebda(); #endif diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 69ac1fe..d9fac36 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -212,7 +212,7 @@ write_idt_stub((void *)0xffe6e, 0x1a); } -#if CONFIG_FRAMEBUFFER_SET_VESA_MODE +#if IS_ENABLED(CONFIG_FRAMEBUFFER_SET_VESA_MODE) vbe_mode_info_t mode_info; static int mode_info_valid; @@ -268,7 +268,7 @@ } vbe_set_mode(&mode_info); -#if CONFIG_BOOTSPLASH +#if IS_ENABLED(CONFIG_BOOTSPLASH) struct jpeg_decdata *decdata; unsigned char *jpeg = cbfs_boot_map_with_leak("bootsplash.jpg", CBFS_TYPE_BOOTSPLASH, @@ -349,13 +349,13 @@ realmode_call(addr + 0x0003, num_dev, 0xffff, 0x0000, 0xffff, 0x0, 0x0); printk(BIOS_DEBUG, "... Option ROM returned.\n"); -#if CONFIG_FRAMEBUFFER_SET_VESA_MODE +#if IS_ENABLED(CONFIG_FRAMEBUFFER_SET_VESA_MODE) if ((dev->class >> 8)== PCI_CLASS_DISPLAY_VGA) vbe_set_graphics(); #endif } -#if CONFIG_GEODE_VSA +#if IS_ENABLED(CONFIG_GEODE_VSA) #define VSA2_BUFFER 0x60000 #define VSA2_ENTRY_POINT 0x60020 @@ -459,7 +459,7 @@ cs = cs_ip >> 16; flags = stackflags; -#if CONFIG_REALMODE_DEBUG +#if IS_ENABLED(CONFIG_REALMODE_DEBUG) printk(BIOS_DEBUG, "oprom: INT# 0x%x\n", intnumber); printk(BIOS_DEBUG, "oprom: eax: %08x ebx: %08x ecx: %08x edx: %08x\n", eax, ebx, ecx, edx); diff --git a/src/device/oprom/realmode/x86_interrupts.c b/src/device/oprom/realmode/x86_interrupts.c index 05cdd4a..7ec77f8 100644 --- a/src/device/oprom/realmode/x86_interrupts.c +++ b/src/device/oprom/realmode/x86_interrupts.c @@ -212,7 +212,7 @@ break; } -#if CONFIG_REALMODE_DEBUG +#if IS_ENABLED(CONFIG_REALMODE_DEBUG) printk(BIOS_DEBUG, "0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", func, bus, devfn, reg, X86_ECX); #endif diff --git a/src/device/pci_device.c b/src/device/pci_device.c index e423151..75e9a79 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -664,7 +664,7 @@ ((device & 0xffff) << 16) | (vendor & 0xffff)); } -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) static int should_run_oprom(struct device *dev) { static int should_run = -1; @@ -677,7 +677,7 @@ */ should_run = display_init_required(); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) if (!should_run) should_run = vboot_wants_oprom(); #endif @@ -706,7 +706,7 @@ /** Default handler: only runs the relevant PCI BIOS. */ void pci_dev_init(struct device *dev) { -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) struct rom_header *rom, *ram; /* Only execute VGA ROMs. */ @@ -783,7 +783,7 @@ */ static struct device_operations *get_pci_bridge_ops(device_t dev) { -#if CONFIG_PCIX_PLUGIN_SUPPORT +#if IS_ENABLED(CONFIG_PCIX_PLUGIN_SUPPORT) unsigned int pcixpos; pcixpos = pci_find_capability(dev, PCI_CAP_ID_PCIX); if (pcixpos) { @@ -791,7 +791,7 @@ return &default_pcix_ops_bus; } #endif -#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT +#if IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) unsigned int htpos = 0; while ((htpos = pci_find_next_capability(dev, PCI_CAP_ID_HT, htpos))) { u16 flags; @@ -804,7 +804,7 @@ } } #endif -#if CONFIG_PCIEXP_PLUGIN_SUPPORT +#if IS_ENABLED(CONFIG_PCIEXP_PLUGIN_SUPPORT) unsigned int pciexpos; pciexpos = pci_find_capability(dev, PCI_CAP_ID_PCIE); if (pciexpos) { @@ -894,7 +894,7 @@ goto bad; dev->ops = get_pci_bridge_ops(dev); break; -#if CONFIG_CARDBUS_PLUGIN_SUPPORT +#if IS_ENABLED(CONFIG_CARDBUS_PLUGIN_SUPPORT) case PCI_HEADER_TYPE_CARDBUS: dev->ops = &default_cardbus_ops_bus; break; @@ -1445,7 +1445,7 @@ return target_pin; } -#if CONFIG_PC80_SYSTEM +#if IS_ENABLED(CONFIG_PC80_SYSTEM) /** * Assign IRQ numbers. * @@ -1494,7 +1494,7 @@ printk(BIOS_DEBUG, " Readback = %d\n", irq); #endif -#if CONFIG_PC80_SYSTEM +#if IS_ENABLED(CONFIG_PC80_SYSTEM) /* Change to level triggered. */ i8259_configure_irq_trigger(pIntAtoD[line - 1], IRQ_LEVEL_TRIGGERED); diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 7107738..6baebe0 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -71,7 +71,7 @@ #endif /* __PRE_RAM__ */ -#if CONFIG_EARLY_PCI_BRIDGE +#if IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE) static void pci_bridge_reset_secondary(device_t p2p_bridge) { diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index a3f5775..6456d17 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -63,7 +63,7 @@ rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); if (rom_address == 0x00000000 || rom_address == 0xffffffff) { -#if CONFIG_BOARD_EMULATION_QEMU_X86 +#if IS_ENABLED(CONFIG_BOARD_EMULATION_QEMU_X86) if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) rom_address = 0xc0000; else @@ -149,7 +149,7 @@ * devices have a mismatch between the hardware and the ROM. */ if (PCI_CLASS_DISPLAY_VGA == (dev->class >> 8)) { -#if !CONFIG_MULTIPLE_VGA_ADAPTERS +#if !IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) extern device_t vga_pri; /* Primary VGA device (device.c). */ if (dev != vga_pri) return NULL; /* Only one VGA supported. */ #endif -- To view, visit https://review.coreboot.org/20338 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I66cde1adcf373889b03f144793c0b4f46d21ca31 Gerrit-Change-Number: 20338 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: device/oprom/yabel: add IS_ENABLED() around Kconfig symbol r...
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20337 Change subject: device/oprom/yabel: add IS_ENABLED() around Kconfig symbol references ...................................................................... device/oprom/yabel: add IS_ENABLED() around Kconfig symbol references Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: I82bf68a7ee54ff88f65aacc9eb0dbc30d013aae0 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/device/oprom/yabel/biosemu.c M src/device/oprom/yabel/compat/functions.c M src/device/oprom/yabel/device.c M src/device/oprom/yabel/device.h M src/device/oprom/yabel/interrupt.c M src/device/oprom/yabel/io.c M src/device/oprom/yabel/mem.c M src/device/oprom/yabel/vbe.c 8 files changed, 50 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/20337/1 diff --git a/src/device/oprom/yabel/biosemu.c b/src/device/oprom/yabel/biosemu.c index a0a407f..a77157f 100644 --- a/src/device/oprom/yabel/biosemu.c +++ b/src/device/oprom/yabel/biosemu.c @@ -52,7 +52,7 @@ #include <device/device.h> #include "compat/rtas.h" -#if CONFIG_X86EMU_DEBUG_TIMINGS +#if IS_ENABLED(CONFIG_X86EMU_DEBUG_TIMINGS) struct mono_time zero; #endif @@ -87,44 +87,44 @@ { u8 *rom_image; int i = 0; -#if CONFIG_X86EMU_DEBUG +#if IS_ENABLED(CONFIG_X86EMU_DEBUG) debug_flags = 0; -#if CONFIG_X86EMU_DEBUG_JMP +#if IS_ENABLED(CONFIG_X86EMU_DEBUG_JMP) debug_flags |= DEBUG_JMP; #endif -#if CONFIG_X86EMU_DEBUG_TRACE +#if IS_ENABLED(CONFIG_X86EMU_DEBUG_TRACE) debug_flags |= DEBUG_TRACE_X86EMU; #endif -#if CONFIG_X86EMU_DEBUG_PNP +#if IS_ENABLED(CONFIG_X86EMU_DEBUG_PNP) debug_flags |= DEBUG_PNP; #endif -#if CONFIG_X86EMU_DEBUG_DISK +#if IS_ENABLED(CONFIG_X86EMU_DEBUG_DISK) debug_flags |= DEBUG_DISK; #endif -#if CONFIG_X86EMU_DEBUG_PMM +#if IS_ENABLED(CONFIG_X86EMU_DEBUG_PMM) debug_flags |= DEBUG_PMM; #endif -#if CONFIG_X86EMU_DEBUG_VBE +#if IS_ENABLED(CONFIG_X86EMU_DEBUG_VBE) debug_flags |= DEBUG_VBE; #endif -#if CONFIG_X86EMU_DEBUG_INT10 +#if IS_ENABLED(CONFIG_X86EMU_DEBUG_INT10) debug_flags |= DEBUG_PRINT_INT10; #endif -#if CONFIG_X86EMU_DEBUG_INTERRUPTS +#if IS_ENABLED(CONFIG_X86EMU_DEBUG_INTERRUPTS) debug_flags |= DEBUG_INTR; #endif -#if CONFIG_X86EMU_DEBUG_CHECK_VMEM_ACCESS +#if IS_ENABLED(CONFIG_X86EMU_DEBUG_CHECK_VMEM_ACCESS) debug_flags |= DEBUG_CHECK_VMEM_ACCESS; #endif -#if CONFIG_X86EMU_DEBUG_MEM +#if IS_ENABLED(CONFIG_X86EMU_DEBUG_MEM) debug_flags |= DEBUG_MEM; #endif -#if CONFIG_X86EMU_DEBUG_IO +#if IS_ENABLED(CONFIG_X86EMU_DEBUG_IO) debug_flags |= DEBUG_IO; #endif #endif -#if CONFIG_X86EMU_DEBUG_TIMINGS +#if IS_ENABLED(CONFIG_X86EMU_DEBUG_TIMINGS) /* required for i915tool compatible output */ zero.microseconds = 0; #endif @@ -345,7 +345,7 @@ * some boot device status in AX (see PNP BIOS Spec Section 3.3 */ DEBUG_PRINTF_CS_IP("Option ROM Exit Status: %04x\n", M.x86.R_AX); -#if CONFIG_X86EMU_DEBUG +#if IS_ENABLED(CONFIG_X86EMU_DEBUG) DEBUG_PRINTF("Exit Status Decode:\n"); if (M.x86.R_AX & 0x100) { // bit 8 DEBUG_PRINTF diff --git a/src/device/oprom/yabel/compat/functions.c b/src/device/oprom/yabel/compat/functions.c index 283c3eb..5a51f18 100644 --- a/src/device/oprom/yabel/compat/functions.c +++ b/src/device/oprom/yabel/compat/functions.c @@ -45,7 +45,7 @@ #define VMEM_SIZE (1024 * 1024) /* 1 MB */ -#if !CONFIG_YABEL_DIRECTHW +#if !IS_ENABLED(CONFIG_YABEL_DIRECTHW) #if CONFIG_YABEL_VIRTMEM_LOCATION u8* vmem = (u8 *) CONFIG_YABEL_VIRTMEM_LOCATION; #else @@ -63,7 +63,7 @@ biosemu(vmem, VMEM_SIZE, dev, addr); -#if CONFIG_FRAMEBUFFER_SET_VESA_MODE +#if IS_ENABLED(CONFIG_FRAMEBUFFER_SET_VESA_MODE) vbe_set_graphics(); #endif } @@ -73,7 +73,7 @@ u64 get_time(void) { u64 act = 0; -#if CONFIG_ARCH_X86 +#if IS_ENABLED(CONFIG_ARCH_X86) u32 eax, edx; __asm__ __volatile__( diff --git a/src/device/oprom/yabel/device.c b/src/device/oprom/yabel/device.c index ee920d5..b3e5d19 100644 --- a/src/device/oprom/yabel/device.c +++ b/src/device/oprom/yabel/device.c @@ -58,7 +58,7 @@ u64 size; } __attribute__ ((__packed__)) assigned_address_t; -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) /* coreboot version */ static void @@ -131,7 +131,7 @@ } // store last entry index of translate_address_array taa_last_entry = taa_index - 1; -#if CONFIG_X86EMU_DEBUG +#if IS_ENABLED(CONFIG_X86EMU_DEBUG) //dump translate_address_array printf("translate_address_array:\n"); translate_address_t ta; @@ -215,7 +215,7 @@ } // store last entry index of translate_address_array taa_last_entry = taa_index - 1; -#if CONFIG_X86EMU_DEBUG +#if IS_ENABLED(CONFIG_X86EMU_DEBUG) //dump translate_address_array printf("translate_address_array:\n"); translate_address_t ta; @@ -247,7 +247,7 @@ translate_address_array[taa_index].address_offset = 0; } -#if !CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if !IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) // to simulate accesses to legacy VGA Memory (0xA0000-0xBFFFF) // we look for the first prefetchable memory BAR, if no prefetchable BAR found, // we use the first memory BAR @@ -309,7 +309,7 @@ { u32 pci_config_0; -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) pci_config_0 = pci_read_config32(bios_device.dev, 0x0); #else pci_config_0 = @@ -371,7 +371,7 @@ memcpy(&pci_ds, (void *) (rom_base_addr + pci_ds_offset), sizeof(pci_ds)); clr_ci(); -#if CONFIG_X86EMU_DEBUG +#if IS_ENABLED(CONFIG_X86EMU_DEBUG) DEBUG_PRINTF("PCI Data Structure @%lx:\n", rom_base_addr + pci_ds_offset); dump((void *) &pci_ds, sizeof(pci_ds)); @@ -435,7 +435,7 @@ DEBUG_PRINTF("%s\n", __func__); memset(&bios_device, 0, sizeof(bios_device)); -#if !CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if !IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) bios_device.ihandle = of_open(device_name); if (bios_device.ihandle == 0) { DEBUG_PRINTF("%s is no valid device!\n", device_name); @@ -446,7 +446,7 @@ bios_device.dev = device; #endif biosemu_dev_get_addr_info(); -#if !CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if !IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) biosemu_dev_find_vmem_addr(); biosemu_dev_get_puid(); #endif @@ -463,7 +463,7 @@ { int i = 0; translate_address_t ta; -#if !CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if !IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) /* we don't need this hack for coreboot... we can access legacy areas */ //check if it is an access to legacy VGA Mem... if it is, map the address //to the vmem BAR and then translate it... diff --git a/src/device/oprom/yabel/device.h b/src/device/oprom/yabel/device.h index 72a4d53..98b5c07 100644 --- a/src/device/oprom/yabel/device.h +++ b/src/device/oprom/yabel/device.h @@ -105,7 +105,7 @@ } biosemu_device_t; typedef struct { -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) unsigned long info; #else u8 info; @@ -149,7 +149,7 @@ static inline void out32le(void *addr, u32 val) { -#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARM +#if IS_ENABLED(CONFIG_ARCH_X86) || IS_ENABLED(CONFIG_ARCH_ARM) *((u32*) addr) = cpu_to_le32(val); #else asm volatile ("stwbrx %0, 0, %1"::"r" (val), "r"(addr)); @@ -160,7 +160,7 @@ in32le(void *addr) { u32 val; -#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARM +#if IS_ENABLED(CONFIG_ARCH_X86) || IS_ENABLED(CONFIG_ARCH_ARM) val = cpu_to_le32(*((u32 *) addr)); #else asm volatile ("lwbrx %0, 0, %1":"=r" (val):"r"(addr)); @@ -171,7 +171,7 @@ static inline void out16le(void *addr, u16 val) { -#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARM +#if IS_ENABLED(CONFIG_ARCH_X86) || IS_ENABLED(CONFIG_ARCH_ARM) *((u16*) addr) = cpu_to_le16(val); #else asm volatile ("sthbrx %0, 0, %1"::"r" (val), "r"(addr)); @@ -182,7 +182,7 @@ in16le(void *addr) { u16 val; -#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARM +#if IS_ENABLED(CONFIG_ARCH_X86) || IS_ENABLED(CONFIG_ARCH_ARM) val = cpu_to_le16(*((u16*) addr)); #else asm volatile ("lhbrx %0, 0, %1":"=r" (val):"r"(addr)); diff --git a/src/device/oprom/yabel/interrupt.c b/src/device/oprom/yabel/interrupt.c index e826fbf..67abe81 100644 --- a/src/device/oprom/yabel/interrupt.c +++ b/src/device/oprom/yabel/interrupt.c @@ -362,7 +362,7 @@ DEBUG_PRINTF_INTR("%s(): function: %x: PCI Find Device\n", __func__, M.x86.R_AX); /* FixME: support SI != 0 */ -#if CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES +#if IS_ENABLED(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) dev = dev_find_device(M.x86.R_DX, M.x86.R_CX, 0); if (dev != 0) { DEBUG_PRINTF_INTR @@ -403,7 +403,7 @@ offs = M.x86.R_DI; DEBUG_PRINTF_INTR("%s(): function: %x: PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n", __func__, M.x86.R_AX, bus, devfn, offs); -#if CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES +#if IS_ENABLED(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) dev = dev_find_slot(bus, devfn); DEBUG_PRINTF_INTR("%s(): function: %x: dev_find_slot() returned: %s\n", __func__, M.x86.R_AX, dev_path(dev)); @@ -427,7 +427,7 @@ switch (M.x86.R_AX) { case 0xb108: M.x86.R_CL = -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) pci_read_config8(dev, offs); #else (u8) rtas_pci_config_read(bios_device. @@ -442,7 +442,7 @@ break; case 0xb109: M.x86.R_CX = -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) pci_read_config16(dev, offs); #else (u16) rtas_pci_config_read(bios_device. @@ -457,7 +457,7 @@ break; case 0xb10a: M.x86.R_ECX = -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) pci_read_config32(dev, offs); #else (u32) rtas_pci_config_read(bios_device. @@ -495,7 +495,7 @@ } else { switch (M.x86.R_AX) { case 0xb10b: -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) pci_write_config8(bios_device.dev, offs, M.x86.R_CL); #else rtas_pci_config_write(bios_device.puid, 1, bus, @@ -507,7 +507,7 @@ M.x86.R_CL); break; case 0xb10c: -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) pci_write_config16(bios_device.dev, offs, M.x86.R_CX); #else rtas_pci_config_write(bios_device.puid, 2, bus, @@ -519,7 +519,7 @@ M.x86.R_CX); break; case 0xb10d: -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) pci_write_config32(bios_device.dev, offs, M.x86.R_ECX); #else rtas_pci_config_write(bios_device.puid, 4, bus, diff --git a/src/device/oprom/yabel/io.c b/src/device/oprom/yabel/io.c index b824acc..d673801 100644 --- a/src/device/oprom/yabel/io.c +++ b/src/device/oprom/yabel/io.c @@ -47,7 +47,7 @@ #include <arch/io.h> -#if CONFIG_YABEL_DIRECTHW +#if IS_ENABLED(CONFIG_YABEL_DIRECTHW) u8 my_inb(X86EMU_pioAddr addr) { u8 val; @@ -426,7 +426,7 @@ offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly DEBUG_PRINTF_INTR("%s(): PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n", __func__, bus, devfn, offs); -#if CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES +#if IS_ENABLED(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) dev = dev_find_slot(bus, devfn); DEBUG_PRINTF_INTR("%s(): dev_find_slot() returned: %s\n", __func__, dev_path(dev)); @@ -446,7 +446,7 @@ HALT_SYS(); return 0; } else { -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) switch (size) { case 1: rval = pci_read_config8(dev, offs); @@ -495,11 +495,11 @@ printf ("Config write access invalid! PCI device %x:%x.%x, offs: %x\n", bus, devfn >> 3, devfn & 7, offs); -#if !CONFIG_YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG +#if !IS_ENABLED(CONFIG_YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG) HALT_SYS(); #endif } else { -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) switch (size) { case 1: pci_write_config8(bios_device.dev, offs, val); diff --git a/src/device/oprom/yabel/mem.c b/src/device/oprom/yabel/mem.c index d4221f8..86d9982 100644 --- a/src/device/oprom/yabel/mem.c +++ b/src/device/oprom/yabel/mem.c @@ -41,10 +41,10 @@ #include "compat/time.h" #include <device/resource.h> -#if !CONFIG_YABEL_DIRECTHW || !CONFIG_YABEL_DIRECTHW +#if !IS_ENABLED(CONFIG_YABEL_DIRECTHW) || !IS_ENABLED(CONFIG_YABEL_DIRECTHW) // define a check for access to certain (virtual) memory regions (interrupt handlers, BIOS Data Area, ...) -#if CONFIG_X86EMU_DEBUG +#if IS_ENABLED(CONFIG_X86EMU_DEBUG) static u8 in_check = 0; // to avoid recursion... static inline void DEBUG_CHECK_VMEM_READ(u32 _addr, u32 _rval) diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index ec99901..876df23 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -34,7 +34,7 @@ #include <string.h> #include <types.h> -#if CONFIG_FRAMEBUFFER_SET_VESA_MODE +#if IS_ENABLED(CONFIG_FRAMEBUFFER_SET_VESA_MODE) #include <boot/coreboot_tables.h> #endif @@ -66,7 +66,7 @@ u8 *biosmem; u32 biosmem_size; -#if CONFIG_FRAMEBUFFER_SET_VESA_MODE +#if IS_ENABLED(CONFIG_FRAMEBUFFER_SET_VESA_MODE) static inline u8 vbe_prepare(void) { @@ -734,7 +734,7 @@ vbe_get_mode_info(&mode_info); vbe_set_mode(&mode_info); -#if CONFIG_BOOTSPLASH +#if IS_ENABLED(CONFIG_BOOTSPLASH) unsigned char *framebuffer = (unsigned char *) le32_to_cpu(mode_info.vesa.phys_base_ptr); DEBUG_PRINTF_VBE("FRAMEBUFFER: 0x%p\n", framebuffer); -- To view, visit https://review.coreboot.org/20337 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I82bf68a7ee54ff88f65aacc9eb0dbc30d013aae0 Gerrit-Change-Number: 20337 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: cpu/intel: add IS_ENABLED() around Kconfig symbol references
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20336 Change subject: cpu/intel: add IS_ENABLED() around Kconfig symbol references ...................................................................... cpu/intel: add IS_ENABLED() around Kconfig symbol references Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: Ie685bbbb1cbf06d32631ea40ad120b6f45374b2e Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/cpu/intel/fsp_model_206ax/model_206ax_init.c M src/cpu/intel/haswell/bootblock.c M src/cpu/intel/haswell/romstage.c M src/cpu/intel/hyperthreading/intel_sibling.c M src/cpu/intel/model_2065x/bootblock.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/bootblock.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/turbo/turbo.c 9 files changed, 13 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/20336/1 diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index aedd467..be1f28b 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -316,7 +316,7 @@ cpu->path.apic.apic_id, new->path.apic.apic_id); -#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 +#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1 /* Start the new CPU */ if (!start_cpu(new)) { /* Record the error in cpu? */ diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index 0522f94..57e1bbb 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -24,7 +24,7 @@ #include <cpu/intel/microcode/microcode.c> #include "haswell.h" -#if CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT) /* Needed for RCBA access to set Soft Reset Data register */ #include <southbridge/intel/lynxpoint/pch.h> #else diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index ac45ee6..c6162dc 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -34,7 +34,7 @@ #include <romstage_handoff.h> #include <reset.h> #include <vendorcode/google/chromeos/chromeos.h> -#if CONFIG_EC_GOOGLE_CHROMEEC +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) #include <ec/google/chromeec/ec.h> #endif #include "haswell.h" @@ -182,7 +182,7 @@ wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); -#if CONFIG_EC_GOOGLE_CHROMEEC +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) /* Ensure the EC is in the right mode for recovery */ google_chromeec_early_init(); #endif @@ -197,7 +197,7 @@ printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); if (wake_from_s3) { -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Resume from S3 detected.\n"); #else printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); @@ -239,7 +239,7 @@ /* Save data returned from MRC on non-S3 resumes. */ save_mrc_data(params->pei_data); } else if (cbmem_initialize()) { - #if CONFIG_HAVE_ACPI_RESUME + #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) /* Failed S3 resume, reset to come up cleanly */ reset_system(); #endif diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 57aa00c..d965470 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -20,7 +20,7 @@ #include <smp/spinlock.h> #include <assert.h> -#if CONFIG_PARALLEL_CPU_INIT +#if IS_ENABLED(CONFIG_PARALLEL_CPU_INIT) #error Intel hyper-threading requires serialized CPU init #endif diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c index a57f166..ed528d1 100644 --- a/src/cpu/intel/model_2065x/bootblock.c +++ b/src/cpu/intel/model_2065x/bootblock.c @@ -23,7 +23,7 @@ #include <cpu/intel/microcode/microcode.c> -#if CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK) #include <southbridge/intel/ibexpeak/pch.h> #include "model_2065x.h" #else diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index fe095c4..f7e6c1d 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -295,7 +295,7 @@ cpu->path.apic.apic_id, new->path.apic.apic_id); -#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 +#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1 /* Start the new CPU */ if (!start_cpu(new)) { /* Record the error in cpu? */ diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index 493d089..670b097 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -24,7 +24,8 @@ #include <cpu/intel/microcode/microcode.c> #include "model_206ax.h" -#if CONFIG_SOUTHBRIDGE_INTEL_BD82X6X || CONFIG_SOUTHBRIDGE_INTEL_C216 +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) || \ + IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216) /* Needed for RCBA access to set Soft Reset Data register */ #include <southbridge/intel/bd82x6x/pch.h> #else diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 2722454..589f3b6 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -489,7 +489,7 @@ cpu->path.apic.apic_id, new->path.apic.apic_id); -#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 +#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1 /* Start the new CPU */ if (!start_cpu(new)) { /* Record the error in cpu? */ diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c index 3fae3f0..9b93870 100644 --- a/src/cpu/intel/turbo/turbo.c +++ b/src/cpu/intel/turbo/turbo.c @@ -19,7 +19,7 @@ #include <cpu/x86/msr.h> #include <arch/cpu.h> -#if CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED +#if IS_ENABLED(CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED) static inline int get_global_turbo_state(void) { return TURBO_UNKNOWN; -- To view, visit https://review.coreboot.org/20336 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie685bbbb1cbf06d32631ea40ad120b6f45374b2e Gerrit-Change-Number: 20336 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: cpu/amd: add IS_ENABLED() around Kconfig symbol references
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20335 Change subject: cpu/amd: add IS_ENABLED() around Kconfig symbol references ...................................................................... cpu/amd: add IS_ENABLED() around Kconfig symbol references Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: I9f4155285529ec28e826637a61436478f648704c Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/cpu/amd/agesa/amd_late_init.c M src/cpu/amd/car/cache_as_ram.inc M src/cpu/amd/dualcore/dualcore.c M src/cpu/amd/family_10h-family_15h/fidvid.c M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/cpu/amd/family_10h-family_15h/model_10xxx_init.c M src/cpu/amd/geode_gx2/syspreinit.c M src/cpu/amd/geode_lx/syspreinit.c M src/cpu/amd/model_fxx/fidvid.c M src/cpu/amd/model_fxx/init_cpus.c M src/cpu/amd/model_fxx/microcode_blob.c M src/cpu/amd/model_fxx/model_fxx_init.c M src/cpu/amd/model_fxx/model_fxx_update_microcode.c M src/cpu/amd/model_fxx/powernow_acpi.c M src/cpu/amd/model_fxx/processor_name.c M src/cpu/amd/pi/00630F01/model_15_init.c M src/cpu/amd/pi/00660F01/model_15_init.c M src/cpu/amd/pi/00670F00/model_15_init.c M src/cpu/amd/pi/00730F01/model_16_init.c M src/cpu/amd/quadcore/quadcore.c 20 files changed, 85 insertions(+), 84 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/20335/1 diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index a55ebd8..9bb6b27 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -18,7 +18,7 @@ #include <northbridge/amd/agesa/agesawrapper.h> -#if CONFIG_AMD_SB_CIMX +#if IS_ENABLED(CONFIG_AMD_SB_CIMX) #include <sb_cimx.h> #endif @@ -29,7 +29,7 @@ agesawrapper_amdinitlate(); -#if CONFIG_AMD_SB_CIMX +#if IS_ENABLED(CONFIG_AMD_SB_CIMX) sb_Late_Post(); #endif if (!acpi_s3_resume_allowed()) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 156333f..e48d25c 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -143,7 +143,7 @@ CAR_FAM10_errata_applied: -#if CONFIG_MMCONF_SUPPORT +#if IS_ENABLED(CONFIG_MMCONF_SUPPORT) #if (CONFIG_MMCONF_BASE_ADDRESS > 0xFFFFFFFF) #error "MMCONF_BASE_ADDRESS too big" #elif (CONFIG_MMCONF_BASE_ADDRESS & 0xFFFFF) diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c index 83302ca..f3cb0972 100644 --- a/src/cpu/amd/dualcore/dualcore.c +++ b/src/cpu/amd/dualcore/dualcore.c @@ -15,7 +15,7 @@ #include "cpu/amd/dualcore/dualcore_id.c" #include <pc80/mc146818rtc.h> -#if CONFIG_HAVE_OPTION_TABLE +#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE) #include "option_table.h" #endif @@ -30,7 +30,7 @@ static inline uint8_t set_apicid_cpuid_lo(void) { -#if !CONFIG_K8_REV_F_SUPPORT +#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) if (is_cpu_pre_e0()) return 0; // pre_e0 can not be set #endif diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 1262718..12fc2c7 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -94,21 +94,21 @@ static inline void print_debug_fv(const char *str, u32 val) { -#if CONFIG_SET_FIDVID_DEBUG +#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG) printk(BIOS_DEBUG, "%s%x\n", str, val); #endif } static inline void print_debug_fv_8(const char *str, u8 val) { -#if CONFIG_SET_FIDVID_DEBUG +#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG) printk(BIOS_DEBUG, "%s%02x\n", str, val); #endif } static inline void print_debug_fv_64(const char *str, u32 val, u32 val2) { -#if CONFIG_SET_FIDVID_DEBUG +#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG) printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2); #endif } @@ -503,7 +503,7 @@ } /* TODO: look into C1E state and F3xA0[IdleExitEn]*/ - #if CONFIG_SVI_HIGH_FREQ + #if IS_ENABLED(CONFIG_SVI_HIGH_FREQ) if (cpuRev & AMD_FAM10_C3) { dword |= SVI_HIGH_FREQ_ON; } @@ -583,7 +583,7 @@ if (cpuRev & AMD_DR_Bx ) { smaf001 = 0xA6; } else { - #if CONFIG_SVI_HIGH_FREQ + #if IS_ENABLED(CONFIG_SVI_HIGH_FREQ) if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) { smaf001 = 0xF6; } @@ -1034,7 +1034,7 @@ } -#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST +#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) struct ap_apicid_st { u32 num; // it could use 256 bytes for 64 node quad core system @@ -1053,7 +1053,7 @@ int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) { -#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST +#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) struct ap_apicid_st ap_apicidx; u32 i; #endif @@ -1068,7 +1068,8 @@ print_debug_fv("BSP fid = ", fv.common_fid); -#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST && !CONFIG_SET_FIDVID_CORE0_ONLY +#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) && \ + !IS_ENABLED(CONFIG_SET_FIDVID_CORE0_ONLY) /* For all APs (We know the APIC ID of all APs even when the APIC ID is lifted) remote read from AP LAPIC_MSG_REG about max fid. Then calculate the common max fid that can be used for all diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 2f90f43..c151aac 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -16,7 +16,7 @@ #include "init_cpus.h" -#if CONFIG_HAVE_OPTION_TABLE +#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE) #include "option_table.h" #endif #include <pc80/mc146818rtc.h> @@ -36,7 +36,7 @@ #include "cpu/amd/car/post_cache_as_ram.c" -#if CONFIG_PCI_IO_CFG_EXT +#if IS_ENABLED(CONFIG_PCI_IO_CFG_EXT) static void set_EnableCf8ExtCfg(void) { // set the NB_CFG[46]=1; @@ -152,7 +152,7 @@ /* get_nodes define in ht_wrapper.c */ nodes = get_nodes(); - if (!CONFIG_LOGICAL_CPUS || + if (!IS_ENABLED(CONFIG_LOGICAL_CPUS) || read_option(multi_core, 0) != 0) { // 0 means multi core disable_siblings = 1; } else { @@ -182,8 +182,8 @@ for (j = jstart; j <= jend; j++) { ap_apicid = get_boot_apic_id(i, j); -#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET > 0) -#if !CONFIG_LIFT_BSP_APIC_ID +#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0) +#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID) if ((i != 0) || (j != 0)) /* except bsp */ #endif ap_apicid += CONFIG_APIC_ID_OFFSET; @@ -227,7 +227,7 @@ return result; } -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid); #endif @@ -398,17 +398,17 @@ if (!is_fam15h()) set_apicid_cpuid_lo(); set_EnableCf8ExtCfg(); -#if CONFIG_ENABLE_APIC_EXT_ID +#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) enable_apic_ext_id(id.nodeid); #endif } enable_lapic(); -#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET > 0) +#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0) u32 initial_apicid = get_initial_apicid(); -#if !CONFIG_LIFT_BSP_APIC_ID +#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID) if (initial_apicid != 0) // other than bsp #endif { @@ -420,7 +420,7 @@ lapic_write(LAPIC_ID, dword); } -#if CONFIG_LIFT_BSP_APIC_ID +#if IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID) bsp_apicid += CONFIG_APIC_ID_OFFSET; #endif @@ -473,8 +473,8 @@ } } -#if CONFIG_SET_FIDVID -#if CONFIG_LOGICAL_CPUS && CONFIG_SET_FIDVID_CORE0_ONLY +#if IS_ENABLED(CONFIG_SET_FIDVID) +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) && IS_ENABLED(CONFIG_SET_FIDVID_CORE0_ONLY) // Run on all AP for proper FID/VID setup. if (id.coreid == 0) // only need set fid for core0 #endif @@ -574,7 +574,7 @@ /* Enable routing table */ printk(BIOS_DEBUG, "Start node %02x", node); -#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) /* For FAM10 support, we need to set Dram base/limit for the new node */ pci_write_config32(NODE_MP(node), 0x44, 0); pci_write_config32(NODE_MP(node), 0x40, 3); @@ -1865,7 +1865,7 @@ cpuSetAMDPCI(i); } -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) // Prep each node for FID/VID setup. prep_fid_change(); #endif diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c index b002b62..361a866 100644 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c @@ -64,7 +64,7 @@ u8 i; msr_t msr; struct node_core_id id; -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; #endif uint8_t delay_start; @@ -124,7 +124,7 @@ /* Set the processor name string */ init_processor_name(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/geode_gx2/syspreinit.c b/src/cpu/amd/geode_gx2/syspreinit.c index 350e6df..aa1a39d 100644 --- a/src/cpu/amd/geode_gx2/syspreinit.c +++ b/src/cpu/amd/geode_gx2/syspreinit.c @@ -26,7 +26,7 @@ void SystemPreInit(void) { /* they want a jump ... */ -#if !CONFIG_CACHE_AS_RAM +#if !IS_ENABLED(CONFIG_CACHE_AS_RAM) __asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n"); #endif StartTimer1(); diff --git a/src/cpu/amd/geode_lx/syspreinit.c b/src/cpu/amd/geode_lx/syspreinit.c index 4a59d02..de6e141 100644 --- a/src/cpu/amd/geode_lx/syspreinit.c +++ b/src/cpu/amd/geode_lx/syspreinit.c @@ -32,7 +32,7 @@ void SystemPreInit(void) { /* they want a jump ... */ -#if !CONFIG_CACHE_AS_RAM +#if !IS_ENABLED(CONFIG_CACHE_AS_RAM) __asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n"); #endif StartTimer1(); diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index 20d0906..371d4b9 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -11,7 +11,7 @@ * GNU General Public License for more details. */ -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) #ifndef SB_VFSMAF #define SB_VFSMAF 1 @@ -21,21 +21,21 @@ static inline void print_debug_fv(const char *str, u32 val) { -#if CONFIG_SET_FIDVID_DEBUG +#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG) printk(BIOS_DEBUG, "%s%x\n", str, val); #endif } static inline void print_debug_fv_8(const char *str, u8 val) { -#if CONFIG_SET_FIDVID_DEBUG +#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG) printk(BIOS_DEBUG, "%s%02x\n", str, val); #endif } static inline void print_debug_fv_64(const char *str, u32 val, u32 val2) { -#if CONFIG_SET_FIDVID_DEBUG +#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG) printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2); #endif } @@ -59,7 +59,7 @@ /* disable the DRAM interface at first, it will be enabled * by raminit again (see also erratum #181) */ -#if CONFIG_K8_REV_F_SUPPORT +#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) dword = pci_read_config32(PCI_DEV(0, 0x18 + i, 2), 0x94); dword |= (1 << 14); pci_write_config32(PCI_DEV(0, 0x18 + i, 2), 0x94, dword); @@ -76,7 +76,7 @@ // dword = 0x00070000; /* enable FID/VID change */ pci_write_config32(PCI_DEV(0, 0x18 + i, 3), 0x80, dword); -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) dword = 0x21132113; #else dword = 0x00132113; @@ -86,7 +86,7 @@ } } -#if !CONFIG_SET_FIDVID_ONE_BY_ONE +#if !IS_ENABLED(CONFIG_SET_FIDVID_ONE_BY_ONE) static unsigned set_fidvid_without_init(unsigned fidvid) { msr_t msr; @@ -292,7 +292,7 @@ ldtstop_sb(); #endif -#if CONFIG_SET_FIDVID_DEBUG +#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG) if (showmessage) { print_debug_fv_8("set_fidvid APICID = ", apicid); print_debug_fv_64("fidvid ctrl msr ", msr.hi, msr.lo); @@ -306,7 +306,7 @@ } fid_cur = msr.lo & 0x3f; -#if CONFIG_SET_FIDVID_DEBUG +#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG) if (showmessage) { print_debug_fv_64("fidvid status msr ", msr.hi, msr.lo); } @@ -387,7 +387,7 @@ send |= ((msr.hi >> (48 - 32)) & 0x3f) << 16; /* max vid */ send |= (apicid << 24); /* ap apicid */ -#if CONFIG_SET_FIDVID_ONE_BY_ONE +#if IS_ENABLED(CONFIG_SET_FIDVID_ONE_BY_ONE) vid_cur = msr.hi & 0x3f; fid_cur = msr.lo & 0x3f; @@ -418,7 +418,7 @@ } if (loop > 0) { -#if CONFIG_SET_FIDVID_ONE_BY_ONE +#if IS_ENABLED(CONFIG_SET_FIDVID_ONE_BY_ONE) readback = set_fidvid(apicid, readback & 0xffff00, 1); // this AP #else readback = set_fidvid_without_init(readback & 0xffff00); // this AP @@ -521,7 +521,7 @@ print_debug_fv("\treadback=", readback); } -#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST +#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) struct ap_apicid_st { u32 num; unsigned apicid[16]; /* 8 way dual core need 16 */ @@ -543,7 +543,7 @@ struct fidvid_st fv; -#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST +#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) struct ap_apicid_st ap_apicidx; unsigned i; #endif @@ -573,7 +573,7 @@ /* calculate the common max fid/vid that could be used for * all APs and BSP */ -#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST +#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) ap_apicidx.num = 0; for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, store_ap_apicid, &ap_apicidx); @@ -609,7 +609,7 @@ #endif -#if CONFIG_SET_FIDVID_ONE_BY_ONE +#if IS_ENABLED(CONFIG_SET_FIDVID_ONE_BY_ONE) /* set BSP fid and vid */ print_debug_fv("bsp apicid=", bsp_apicid); fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1); @@ -623,7 +623,7 @@ fv.common_fidvid &= 0xffff00; /* set state 2 allow is in init_fidvid_bsp_stage2 */ -#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST +#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) for (i = 0; i < ap_apicidx.num; i++) { init_fidvid_bsp_stage2(ap_apicidx.apicid[i], &fv); } @@ -631,7 +631,7 @@ for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage2, &fv); #endif -#if !CONFIG_SET_FIDVID_ONE_BY_ONE +#if !IS_ENABLED(CONFIG_SET_FIDVID_ONE_BY_ONE) /* set BSP fid and vid */ print_debug_fv("bsp apicid=", bsp_apicid); fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1); diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 035453e..48920bb 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -15,7 +15,7 @@ #include <northbridge/amd/amdk8/amdk8.h> #include "cpu/amd/car/post_cache_as_ram.c" -#if CONFIG_HAVE_OPTION_TABLE +#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE) #include "option_table.h" #endif @@ -61,7 +61,7 @@ 3); if (nb_cfg_54) { if (j == 0) { // if it is single core, we need to increase siblings for APIC calculation -#if !CONFIG_K8_REV_F_SUPPORT +#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) e0_later_single_core = is_e0_later_in_bsp(i); // single core #else e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 @@ -93,8 +93,8 @@ i * (nb_cfg_54 ? (siblings + 1) : 1) + j * (nb_cfg_54 ? 1 : 8); -#if CONFIG_ENABLE_APIC_EXT_ID -#if !CONFIG_LIFT_BSP_APIC_ID +#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) +#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID) if ((i != 0) || (j != 0)) /* except bsp */ #endif ap_apicid += CONFIG_APIC_ID_OFFSET; @@ -140,7 +140,7 @@ #define LAPIC_MSG_REG 0x380 -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) static void init_fidvid_ap(u32 bsp_apicid, u32 apicid); #endif @@ -223,7 +223,7 @@ stop_this_cpu(); } -#if CONFIG_RAMINIT_SYSINFO +#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO) static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) #else static u32 init_cpus(u32 cpu_init_detectedx) @@ -265,10 +265,10 @@ enable_lapic(); // init_timer(); // We need TMICT to pass msg for FID/VID change -#if CONFIG_ENABLE_APIC_EXT_ID +#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) u32 initial_apicid = get_initial_apicid(); -#if !CONFIG_LIFT_BSP_APIC_ID +#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID) if (initial_apicid != 0) // other than bsp #endif { @@ -280,7 +280,7 @@ lapic_write(LAPIC_ID, dword); } -#if CONFIG_LIFT_BSP_APIC_ID +#if IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID) bsp_apicid += CONFIG_APIC_ID_OFFSET; #endif @@ -315,8 +315,8 @@ u32 timeout = 1; u32 loop = 100; -#if CONFIG_SET_FIDVID -#if CONFIG_LOGICAL_CPUS && CONFIG_SET_FIDVID_CORE0_ONLY +#if IS_ENABLED(CONFIG_SET_FIDVID) +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) && IS_ENABLED(CONFIG_SET_FIDVID_CORE0_ONLY) if (id.coreid == 0) // only need set fid for core0 #endif init_fidvid_ap(bsp_apicid, apicid); @@ -333,7 +333,7 @@ } lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x44); // bsp can not check it before stop_this_cpu set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); -#if CONFIG_K8_REV_F_SUPPORT +#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) #if CONFIG_MEM_TRAIN_SEQ == 1 train_ram_on_node(id.nodeid, id.coreid, sysinfo, (unsigned)STOP_CAR_AND_CPU); diff --git a/src/cpu/amd/model_fxx/microcode_blob.c b/src/cpu/amd/model_fxx/microcode_blob.c index 691ae83..98b418b 100644 --- a/src/cpu/amd/model_fxx/microcode_blob.c +++ b/src/cpu/amd/model_fxx/microcode_blob.c @@ -12,7 +12,7 @@ */ unsigned char microcode[] __attribute__ ((aligned(16))) = { -#if !CONFIG_K8_REV_F_SUPPORT +#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) #include "../../../../3rdparty/blobs/cpu/amd/model_fxx/microcode.h" #endif }; diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 8f4bae2..c21bce6 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -39,10 +39,10 @@ #include <cpu/amd/multicore.h> #include <cpu/amd/msr.h> -#if CONFIG_WAIT_BEFORE_CPUS_INIT +#if IS_ENABLED(CONFIG_WAIT_BEFORE_CPUS_INIT) void cpus_ready_for_init(void) { -#if CONFIG_K8_REV_F_SUPPORT +#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) #if CONFIG_MEM_TRAIN_SEQ == 1 struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); // wait for ap memory to trained @@ -511,7 +511,7 @@ /* Enable the local CPU APICs */ setup_lapic(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { @@ -559,7 +559,7 @@ }; static struct cpu_device_id cpu_table[] = { -#if !CONFIG_K8_REV_F_SUPPORT +#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) { X86_VENDOR_AMD, 0xf40 }, /* SH-B0 (socket 754) */ { X86_VENDOR_AMD, 0xf50 }, /* SH-B0 (socket 940) */ { X86_VENDOR_AMD, 0xf51 }, /* SH-B3 (socket 940) */ @@ -601,7 +601,7 @@ { X86_VENDOR_AMD, 0x30ff2 }, /* E4 ? */ #endif -#if CONFIG_K8_REV_F_SUPPORT +#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) /* * AMD F0 support. * diff --git a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c index 4b70e58..6ae055b 100644 --- a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c +++ b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c @@ -26,7 +26,7 @@ static u16 get_equivalent_processor_rev_id(u32 orig_id) { static const struct id_mapping id_mapping_table[] = { - #if !CONFIG_K8_REV_F_SUPPORT + #if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) { 0x0f48, 0x0048 }, { 0x0f58, 0x0048 }, @@ -49,7 +49,7 @@ { 0x20fb1, 0x0210 }, #endif - #if CONFIG_K8_REV_F_SUPPORT + #if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) /* FIXME * Microcode files for CPU revision 0xf do * not seem to be available... diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c index 9979055..c718351 100644 --- a/src/cpu/amd/model_fxx/powernow_acpi.c +++ b/src/cpu/amd/model_fxx/powernow_acpi.c @@ -69,7 +69,7 @@ acpigen_pop_len(); } -#if CONFIG_K8_REV_F_SUPPORT +#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) /* * Details about this algorithm , refer to BDKG 10.5.1 * Two parts are included, the another is the DSDT reconstruction process diff --git a/src/cpu/amd/model_fxx/processor_name.c b/src/cpu/amd/model_fxx/processor_name.c index 60dbf6e..de6a514 100644 --- a/src/cpu/amd/model_fxx/processor_name.c +++ b/src/cpu/amd/model_fxx/processor_name.c @@ -39,7 +39,7 @@ * your mainboard will not be posted on the AMD Recommended Motherboard Website */ -#if !CONFIG_K8_REV_F_SUPPORT +#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) static const char *processor_names[]={ /* 0x00 */ "AMD Engineering Sample", /* 0x01-0x03 */ NULL, NULL, NULL, @@ -99,7 +99,7 @@ int init_processor_name(void) { -#if !CONFIG_K8_REV_F_SUPPORT +#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) u32 EightBitBrandId; #endif u32 BrandId; @@ -113,7 +113,7 @@ char program_string[48]; unsigned int *program_values = (unsigned int *)program_string; -#if !CONFIG_K8_REV_F_SUPPORT +#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) /* Find out which CPU brand it is */ EightBitBrandId = cpuid_ebx(0x00000001) & 0xff; BrandId = cpuid_ebx(0x80000001) & 0xffff; @@ -137,7 +137,7 @@ processor_name_string = "AMD Processor model unknown"; #endif -#if CONFIG_K8_REV_F_SUPPORT +#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) u32 Socket; u32 CmpCap; u32 PwrLmt; @@ -394,7 +394,7 @@ for (i=0; i<47; i++) { // 48 -1 if (program_string[i] == program_string[i+1]) { switch (program_string[i]) { -#if !CONFIG_K8_REV_F_SUPPORT +#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) case 'X': ModelNumber = 22+ NN; break; case 'Y': ModelNumber = 38 + (2*NN); break; case 'Z': @@ -403,7 +403,7 @@ case 'V': ModelNumber = 9 + NN; break; #endif -#if CONFIG_K8_REV_F_SUPPORT +#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) case 'R': ModelNumber = NN - 1; break; case 'P': ModelNumber = 26 + NN; break; case 'T': ModelNumber = 15 + (CmpCap * 10) + NN; break; diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index c2f2e9d..317aca8 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -39,7 +39,7 @@ msr_t msr; int msrno; unsigned int cpu_idx; -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; #endif @@ -79,7 +79,7 @@ /* Enable the local CPU APICs */ setup_lapic(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c index c31dec8..8f739cf 100644 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -54,7 +54,7 @@ u8 i; msr_t msr; int msrno; -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; #endif @@ -93,7 +93,7 @@ /* Enable the local CPU APICs */ setup_lapic(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/pi/00670F00/model_15_init.c b/src/cpu/amd/pi/00670F00/model_15_init.c index 02e5b79..5550b99 100644 --- a/src/cpu/amd/pi/00670F00/model_15_init.c +++ b/src/cpu/amd/pi/00670F00/model_15_init.c @@ -54,7 +54,7 @@ u8 i; msr_t msr; int msrno; -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; #endif @@ -92,7 +92,7 @@ /* Enable the local CPU APICs */ setup_lapic(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 294814f..ddea603 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -37,7 +37,7 @@ u8 i; msr_t msr; int msrno; -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; #endif @@ -76,7 +76,7 @@ /* Enable the local CPU APICs */ setup_lapic(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c index 2f0822e..097a88f 100644 --- a/src/cpu/amd/quadcore/quadcore.c +++ b/src/cpu/amd/quadcore/quadcore.c @@ -16,7 +16,7 @@ #include <console/console.h> #include <pc80/mc146818rtc.h> -#if CONFIG_HAVE_OPTION_TABLE +#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE) #include "option_table.h" #endif -- To view, visit https://review.coreboot.org/20335 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9f4155285529ec28e826637a61436478f648704c Gerrit-Change-Number: 20335 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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coreboot-gerrit June 2017