coreboot-gerrit June 2017

coreboot-gerrit@coreboot.org

1 participants
2269 discussions

Change in coreboot[master]: src/include: add IS_ENABLED() around Kconfig symbol references
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20354 Change subject: src/include: add IS_ENABLED() around Kconfig symbol references ...................................................................... src/include: add IS_ENABLED() around Kconfig symbol references Change-Id: I2fbe6376a1cf98d328464556917638a5679641d2 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/include/cpu/amd/car.h M src/include/cpu/x86/lapic.h M src/include/cpu/x86/post_code.h M src/include/cpu/x86/smm.h M src/include/cpu/x86/tsc.h M src/include/device/device.h M src/include/device/pci.h M src/include/device/pci_ehci.h M src/include/elog.h M src/include/option.h M src/include/pc80/mc146818rtc.h M src/include/smp/atomic.h M src/include/smp/node.h M src/include/smp/spinlock.h M src/include/stddef.h M src/include/thread.h M src/include/timestamp.h M src/include/trace.h M src/include/watchdog.h 19 files changed, 27 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/20354/1 diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h index b4fbd60..47a9dfa 100644 --- a/src/include/cpu/amd/car.h +++ b/src/include/cpu/amd/car.h @@ -10,7 +10,7 @@ void cache_as_ram_switch_stack(void *stacktop); void cache_as_ram_new_stack(void); -#if CONFIG_CPU_AMD_AGESA || CONFIG_CPU_AMD_PI +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA) || IS_ENABLED(CONFIG_CPU_AMD_PI) void disable_cache_as_ram(void); #endif diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 6f3cbdb..e781b5a 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -7,7 +7,7 @@ #include <smp/node.h> /* See if I need to initialize the local APIC */ -#if CONFIG_SMP || CONFIG_IOAPIC +#if IS_ENABLED(CONFIG_SMP) || IS_ENABLED(CONFIG_IOAPIC) # define NEED_LAPIC 1 #else # define NEED_LAPIC 0 @@ -54,7 +54,7 @@ return lapic_read(LAPIC_ID) >> 24; } -#if !CONFIG_AP_IN_SIPI_WAIT +#if !IS_ENABLED(CONFIG_AP_IN_SIPI_WAIT) /* If we need to go back to sipi wait, we use the long non-inlined version of * this function in lapic_cpu_init.c */ @@ -149,7 +149,7 @@ void setup_lapic(void); -#if CONFIG_SMP +#if IS_ENABLED(CONFIG_SMP) struct device; int start_cpu(struct device *cpu); #endif /* CONFIG_SMP */ diff --git a/src/include/cpu/x86/post_code.h b/src/include/cpu/x86/post_code.h index 6acfe10..cd3d159 100644 --- a/src/include/cpu/x86/post_code.h +++ b/src/include/cpu/x86/post_code.h @@ -2,7 +2,7 @@ #include <console/post_codes.h> -#if CONFIG_POST_IO +#if IS_ENABLED(CONFIG_POST_IO) #define post_code(value) \ movb $value, %al; \ outb %al, $CONFIG_POST_IO_PORT diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 15e3ed3..41afd08 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -478,7 +478,7 @@ void southbridge_smi_set_eos(void); -#if CONFIG_SMM_TSEG +#if IS_ENABLED(CONFIG_SMM_TSEG) void cpu_smi_handler(void); void northbridge_smi_handler(void); void southbridge_smi_handler(void); @@ -493,7 +493,7 @@ int mainboard_smi_apmc(u8 data); void mainboard_smi_sleep(u8 slp_typ); -#if !CONFIG_SMM_TSEG +#if !IS_ENABLED(CONFIG_SMM_TSEG) void smi_release_lock(void); #endif diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 5a7fbc2..4cf4fbc 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -3,9 +3,9 @@ #include <stdint.h> -#if CONFIG_TSC_SYNC_MFENCE +#if IS_ENABLED(CONFIG_TSC_SYNC_MFENCE) #define TSC_SYNC "mfence\n" -#elif CONFIG_TSC_SYNC_LFENCE +#elif IS_ENABLED(CONFIG_TSC_SYNC_LFENCE) #define TSC_SYNC "lfence\n" #else #define TSC_SYNC diff --git a/src/include/device/device.h b/src/include/device/device.h index 5bc4d1c..242d297 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -53,7 +53,7 @@ void (*disable)(device_t dev); void (*set_link)(device_t dev, unsigned int link); void (*reset_bus)(struct bus *bus); -#if CONFIG_GENERATE_SMBIOS_TABLES +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) int (*get_smbios_data)(device_t dev, int *handle, unsigned long *current); void (*get_smbios_strings)(device_t dev, struct smbios_type11 *t); @@ -163,7 +163,7 @@ extern const char mainboard_name[]; -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) /* IGD UMA memory */ extern uint64_t uma_memory_base; extern uint64_t uma_memory_size; diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 4f6dfbc..4283141 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -15,7 +15,7 @@ #ifndef PCI_H #define PCI_H -#if CONFIG_PCI +#if IS_ENABLED(CONFIG_PCI) #include <stdint.h> #include <stddef.h> diff --git a/src/include/device/pci_ehci.h b/src/include/device/pci_ehci.h index 1eb3cd0..48178c8 100644 --- a/src/include/device/pci_ehci.h +++ b/src/include/device/pci_ehci.h @@ -29,7 +29,7 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base); #ifndef __PRE_RAM__ -#if !CONFIG_USBDEBUG +#if !IS_ENABLED(CONFIG_USBDEBUG) #define pci_ehci_read_resources pci_dev_read_resources #else /* Relocation of EHCI Debug Port BAR diff --git a/src/include/elog.h b/src/include/elog.h index ecda87d..f6f0bdd 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -206,7 +206,7 @@ /* Deep Sx wake variant */ #define ELOG_TYPE_ACPI_DEEP_WAKE 0xad -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) /* Eventlog backing storage must be initialized before calling elog_init(). */ extern int elog_init(void); extern int elog_clear(void); diff --git a/src/include/option.h b/src/include/option.h index 83f3a84..f6ede96 100644 --- a/src/include/option.h +++ b/src/include/option.h @@ -6,7 +6,7 @@ * storage can be used. This will benefit machines without CMOS as well as those * without a battery-backed CMOS (e.g. some laptops). */ -#if CONFIG_USE_OPTION_TABLE +#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) #include <pc80/mc146818rtc.h> #else #include <types.h> diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index ec0bf8e..f6a1c04 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -1,7 +1,7 @@ #ifndef PC80_MC146818RTC_H #define PC80_MC146818RTC_H -#if CONFIG_ARCH_X86 +#if IS_ENABLED(CONFIG_ARCH_X86) #include <arch/io.h> #include <types.h> @@ -193,8 +193,8 @@ #define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, \ CMOS_VLEN_ ##name, (default)) -#if CONFIG_CMOS_POST -#if CONFIG_USE_OPTION_TABLE +#if IS_ENABLED(CONFIG_CMOS_POST) +#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) # include "option_table.h" # define CMOS_POST_OFFSET (CMOS_VSTART_cmos_post_offset >> 3) #else @@ -241,7 +241,7 @@ /* Initialize to zero */ cmos_write(0, CMOS_POST_BANK_0_OFFSET); cmos_write(0, CMOS_POST_BANK_1_OFFSET); -#if CONFIG_CMOS_POST_EXTRA +#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA) cmos_write32(CMOS_POST_BANK_0_EXTRA, 0); cmos_write32(CMOS_POST_BANK_1_EXTRA, 0); #endif diff --git a/src/include/smp/atomic.h b/src/include/smp/atomic.h index 56df9f5..5db59e9 100644 --- a/src/include/smp/atomic.h +++ b/src/include/smp/atomic.h @@ -1,7 +1,7 @@ #ifndef SMP_ATOMIC_H #define SMP_ATOMIC_H -#if CONFIG_SMP +#if IS_ENABLED(CONFIG_SMP) #include <arch/smp/atomic.h> #else diff --git a/src/include/smp/node.h b/src/include/smp/node.h index 4e45c46..65931bc 100644 --- a/src/include/smp/node.h +++ b/src/include/smp/node.h @@ -1,7 +1,7 @@ #ifndef _SMP_NODE_H_ #define _SMP_NODE_H_ -#if CONFIG_SMP +#if IS_ENABLED(CONFIG_SMP) int boot_cpu(void); #else #define boot_cpu(x) 1 diff --git a/src/include/smp/spinlock.h b/src/include/smp/spinlock.h index f181f45..a7b8001 100644 --- a/src/include/smp/spinlock.h +++ b/src/include/smp/spinlock.h @@ -1,7 +1,7 @@ #ifndef SMP_SPINLOCK_H #define SMP_SPINLOCK_H -#if CONFIG_SMP +#if IS_ENABLED(CONFIG_SMP) #include <arch/smp/spinlock.h> #else /* !CONFIG_SMP */ diff --git a/src/include/stddef.h b/src/include/stddef.h index af63196..5df7735 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -37,7 +37,7 @@ #endif /* Work around non-writable data segment in execute-in-place romstage on x86. */ -#if defined(__PRE_RAM__) && CONFIG_ARCH_X86 +#if defined(__PRE_RAM__) && IS_ENABLED(CONFIG_ARCH_X86) #define MAYBE_STATIC #else #define MAYBE_STATIC static diff --git a/src/include/thread.h b/src/include/thread.h index 586fb3a..ed04beb 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -21,7 +21,7 @@ #include <timer.h> #include <arch/cpu.h> -#if CONFIG_COOP_MULTITASKING && !defined(__SMM__) && !defined(__PRE_RAM__) +#if IS_ENABLED(CONFIG_COOP_MULTITASKING) && !defined(__SMM__) && !defined(__PRE_RAM__) struct thread { int id; diff --git a/src/include/timestamp.h b/src/include/timestamp.h index 58edb52..d073529 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -18,7 +18,7 @@ #include <commonlib/timestamp_serialized.h> -#if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT \ +#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) \ || !defined(__PRE_RAM__)) /* * timestamp_init() needs to be called once for each of these cases: diff --git a/src/include/trace.h b/src/include/trace.h index 8745966..12c7fa6 100644 --- a/src/include/trace.h +++ b/src/include/trace.h @@ -25,7 +25,7 @@ #else /* !__PRE_RAM__ */ -#if CONFIG_TRACE && !defined(__SMM__) +#if IS_ENABLED(CONFIG_TRACE) && !defined(__SMM__) void __cyg_profile_func_enter(void *, void *) __attribute__ ((no_instrument_function)); diff --git a/src/include/watchdog.h b/src/include/watchdog.h index 375563d..e8de580 100644 --- a/src/include/watchdog.h +++ b/src/include/watchdog.h @@ -1,7 +1,7 @@ #ifndef WATCHDOG_H #define WATCHDOG_H -#if CONFIG_USE_WATCHDOG_ON_BOOT +#if IS_ENABLED(CONFIG_USE_WATCHDOG_ON_BOOT) void watchdog_off(void); #else #define watchdog_off() { while (0); } -- To view, visit https://review.coreboot.org/20354 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2fbe6376a1cf98d328464556917638a5679641d2 Gerrit-Change-Number: 20354 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: src/southbridge: add IS_ENABLED() around Kconfig symbol refe...
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20353 Change subject: src/southbridge: add IS_ENABLED() around Kconfig symbol references ...................................................................... src/southbridge: add IS_ENABLED() around Kconfig symbol references Change-Id: Ie965cbcf7f7b6f6c9e9a69e2a1ff0ba491246cbe Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/southbridge/nvidia/ck804/early_setup.c M src/southbridge/nvidia/ck804/early_setup_car.c M src/southbridge/nvidia/mcp55/early_setup_car.c M src/southbridge/nvidia/mcp55/smbus.c M src/southbridge/via/k8t890/bridge.c M src/southbridge/via/k8t890/ctrl.c M src/southbridge/via/k8t890/dram.c M src/southbridge/via/k8t890/early_car.c M src/southbridge/via/k8t890/romstrap.S M src/southbridge/via/vt8237r/ide.c M src/southbridge/via/vt8237r/lpc.c M src/southbridge/via/vt8237r/nic.c M src/southbridge/via/vt8237r/pirq.c M src/southbridge/via/vt8237r/usb.c M src/southbridge/via/vt8237r/vt8237r.h 15 files changed, 55 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/20353/1 diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c index 79c9eff..673c44d 100644 --- a/src/southbridge/nvidia/ck804/early_setup.c +++ b/src/southbridge/nvidia/ck804/early_setup.c @@ -250,7 +250,7 @@ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), -#if CONFIG_CK804_USE_NIC +#if IS_ENABLED(CONFIG_CK804_USE_NIC) RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040, RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), @@ -258,7 +258,7 @@ RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1 , 0, 0xe4), ~(1 << 23), (1 << 23), #endif -#if CONFIG_CK804_USE_ACI +#if IS_ENABLED(CONFIG_CK804_USE_ACI) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), #endif @@ -268,7 +268,7 @@ #endif #if CONFIG_CK804_NUM > 1 -#if CONFIG_CK804_USE_NIC +#if IS_ENABLED(CONFIG_CK804_USE_NIC) RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040, RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index aeea41b..6472abf 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -198,7 +198,7 @@ /* SYSCTRL */ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), -#if CONFIG_CK804_USE_NIC +#if IS_ENABLED(CONFIG_CK804_USE_NIC) RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040, RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), @@ -206,7 +206,7 @@ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe4), ~(1 << 23), (1 << 23), #endif -#if CONFIG_CK804_USE_ACI +#if IS_ENABLED(CONFIG_CK804_USE_ACI) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), #endif @@ -280,7 +280,7 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8), -#if CONFIG_CK804_USE_NIC +#if IS_ENABLED(CONFIG_CK804_USE_NIC) RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040, RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 7f1d03b..8019a8e 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -250,7 +250,7 @@ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, #endif -#if CONFIG_MCP55_USE_AZA +#if IS_ENABLED(CONFIG_MCP55_USE_AZA) RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE, #endif @@ -260,7 +260,7 @@ MCP55_MB_SETUP #endif -#if CONFIG_MCP55_USE_AZA +#if IS_ENABLED(CONFIG_MCP55_USE_AZA) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3 << 2), (2 << 2), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3 << 2), (2 << 2), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3 << 2), (2 << 2), @@ -284,7 +284,7 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012, -#if CONFIG_MCP55_USE_NIC +#if IS_ENABLED(CONFIG_MCP55_USE_NIC) RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1 << 22) | (1 << 20)), (1 << 22) | (1 << 20), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c index 7829a28..c41445b 100644 --- a/src/southbridge/nvidia/mcp55/smbus.c +++ b/src/southbridge/nvidia/mcp55/smbus.c @@ -89,7 +89,7 @@ .write_byte = lsmbus_write_byte, }; -#if CONFIG_HAVE_ACPI_TABLES +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) unsigned pm_base; #endif @@ -108,7 +108,7 @@ static void mcp55_sm_init(device_t dev) { -#if CONFIG_HAVE_ACPI_TABLES +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) struct resource *res; res = find_resource(dev, 0x60); diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c index e1b6bfe..f7ccd75 100644 --- a/src/southbridge/via/k8t890/bridge.c +++ b/src/southbridge/via/k8t890/bridge.c @@ -29,7 +29,7 @@ writeback(dev, 0x40, 0x91); writeback(dev, 0x41, 0x40); writeback(dev, 0x43, 0x44); -#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD) writeback(dev, 0x42, 0x80); writeback(dev, 0x44, 0x35); #else @@ -45,7 +45,7 @@ * (Forward VGA compatible memory and I/O cycles ) */ -#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD) writeback(dev, 0x3e, 0x0a); #else writeback(dev, 0x3e, 0x16); diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 7255a92..f5e248d 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -47,11 +47,11 @@ pci_write_config8(dev, 0x70, 0xc2); /* PCI Control */ -#if !CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD +#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD) pci_write_config8(dev, 0x72, 0xee); #endif pci_write_config8(dev, 0x73, 0x01); -#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD) pci_write_config8(dev, 0x74, 0x64); pci_write_config8(dev, 0x75, 0x3f); #else @@ -59,7 +59,7 @@ pci_write_config8(dev, 0x75, 0x0f); #endif pci_write_config8(dev, 0x76, 0x50); -#if !CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD +#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD) pci_write_config8(dev, 0x77, 0x08); #endif pci_write_config8(dev, 0x78, 0x01); @@ -156,7 +156,7 @@ /* PCI CFG Address bits[27:24] are used as extended register address bit[11:8] */ -#if !CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD +#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD) pci_write_config8(dev, 0x47, 0x30); #endif diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c index e907528..1f126cc 100644 --- a/src/southbridge/via/k8t890/dram.c +++ b/src/southbridge/via/k8t890/dram.c @@ -69,7 +69,7 @@ static void dram_enable_k8m890(struct device *dev) { -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) msr_t msr; int ret; unsigned int fbbits; @@ -121,7 +121,7 @@ static void dram_init_fb(struct device *dev) { -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) /* Important bits: * Enable the internal GFX bit 7 of reg 0xa1 plus in same reg: * bits 6:4 X fbuffer size will be 2^(X+2) or 100 = 64MB, 101 = 128MB diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c index 5f1e4c4..64f0425 100644 --- a/src/southbridge/via/k8t890/early_car.c +++ b/src/southbridge/via/k8t890/early_car.c @@ -32,7 +32,7 @@ /* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */ static u8 ldtreg[3] = {0x86, 0xa6, 0xc6}; -#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD) #define K8X8XX_HT_CFG_BASE 0xc0 #else #define K8X8XX_HT_CFG_BASE 0x60 @@ -50,7 +50,7 @@ u8 cldtwidth_in, cldtwidth_out, vldtwidth_in, vldtwidth_out, ldtnr, width; u16 vldtcaps; -#if !CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD +#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD) u8 reg; /* hack, enable NVRAM in chipset */ @@ -76,21 +76,21 @@ ldtnr = 2; } -#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M800 +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M800) printk(BIOS_DEBUG, "K8M800 found at LDT "); -#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800 +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800) printk(BIOS_DEBUG, "K8T800 found at LDT "); -#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD) printk(BIOS_DEBUG, "K8T800_OLD found at LDT "); pci_write_config8(PCI_DEV(0, 0x0, 0), 0x64, 0x00); pci_write_config8(PCI_DEV(0, 0x0, 0), 0xdd, 0x50); -#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800PRO +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800PRO) printk(BIOS_DEBUG, "K8T800 Pro found at LDT "); -#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890 +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890) printk(BIOS_DEBUG, "K8M890 found at LDT "); /* K8M890 fix HT delay */ pci_write_config8(PCI_DEV(0, 0x0, 2), 0xab, 0x22); -#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T890 +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T890) printk(BIOS_DEBUG, "K8T890 found at LDT "); #endif printk(BIOS_DEBUG, "%02x", ldtnr); diff --git a/src/southbridge/via/k8t890/romstrap.S b/src/southbridge/via/k8t890/romstrap.S index 2115eaa..cb384e9 100644 --- a/src/southbridge/via/k8t890/romstrap.S +++ b/src/southbridge/via/k8t890/romstrap.S @@ -29,7 +29,9 @@ * Below are some Dev0 Func2 HT control registers values, * depending on strap pin, one of below lines is used. */ -#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M800 || CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800 || CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M800) || \ + IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800) || \ + IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD) tblpointer: .long 0x50220000, 0X619707C2 @@ -48,7 +50,7 @@ .long 0x0 .long 0x0 -#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890 +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890) tblpointer: .long 0x504400FF, 0x61970FC2 //;200M @@ -68,7 +70,7 @@ .long 0x0 -#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T890 +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T890) tblpointer: .long 0x504400AA, 0x61970FC2 //;200M diff --git a/src/southbridge/via/vt8237r/ide.c b/src/southbridge/via/vt8237r/ide.c index 8550d46..4579171 100644 --- a/src/southbridge/via/vt8237r/ide.c +++ b/src/southbridge/via/vt8237r/ide.c @@ -101,7 +101,7 @@ cablesel |= vt8237_ide_80pin_detect(dev); pci_write_config32(dev, IDE_UDMA, cablesel); -#if CONFIG_EPIA_VT8237R_INIT +#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) device_t lpc_dev; /* Set PATA Output Drive Strength */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 9d91749..70ac5d9 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -34,7 +34,7 @@ static void southbridge_init_common(struct device *dev); -#if CONFIG_EPIA_VT8237R_INIT +#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) /* Interrupts for INT# A B C D */ static const unsigned char pciIrqs[4] = { 10, 11, 12, 0}; @@ -61,7 +61,7 @@ /** Set up PCI IRQ routing, route everything through APIC. */ static void pci_routing_fixup(struct device *dev) { -#if CONFIG_EPIA_VT8237R_INIT +#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) device_t pdev; #endif @@ -74,7 +74,7 @@ /* Gate Interrupts until RAM Writes are flushed */ pci_write_config8(dev, 0x49, 0x20); -#if CONFIG_EPIA_VT8237R_INIT +#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) /* Share INTE-INTH with INTA-INTD as per stock BIOS. */ pci_write_config8(dev, 0x46, 0x00); @@ -160,7 +160,7 @@ /* Set ACPI to 9, must set IRQ 9 override to level! Set PSON gating. */ pci_write_config8(dev, 0x82, 0x40 | VT8237R_ACPI_IRQ); -#if CONFIG_EPIA_VT8237R_INIT +#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) /* Primary interrupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ pci_write_config16(dev, 0x84, 0x3052); #else @@ -195,7 +195,7 @@ * 0 = USB Wakeup */ -#if CONFIG_EPIA_VT8237R_INIT +#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) pci_write_config8(dev, 0x95, 0xc2); #else tmp = 0xcc; @@ -263,7 +263,7 @@ cfg = dev->chip_info; -#if CONFIG_EPIA_VT8237R_INIT +#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); /* * TODO: Looks like stock BIOS can do this but causes a hang @@ -313,14 +313,15 @@ enables |= 0x08; pci_write_config8(dev, 0x4f, enables); -#if CONFIG_EPIA_VT8237R_INIT +#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) /* * Set Read Pass Write Control Enable */ pci_write_config8(dev, 0x48, 0x0c); #else - #if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800 || CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD + #if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800) || \ + IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD) /* It seems that when we pair with the K8T800, we need to disable * the A2 mask */ @@ -337,7 +338,7 @@ southbridge_init_common(dev); -#if !CONFIG_EPIA_VT8237R_INIT +#if !IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) /* FIXME: Intel needs more bit set for C2/C3. */ /* @@ -444,7 +445,7 @@ { u8 enables, byte; struct southbridge_via_vt8237r_config *cfg; -#if !CONFIG_EPIA_VT8237R_INIT +#if !IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) unsigned char pwr_on; #endif @@ -456,7 +457,7 @@ pci_write_config8(dev, PCI_COMMAND, byte); /* EPIA-N(L) Uses CN400 for BIOS Access */ -#if !CONFIG_EPIA_VT8237R_INIT +#if !IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) /* Enable the internal I/O decode. */ enables = pci_read_config8(dev, 0x6C); enables |= 0x80; @@ -495,7 +496,7 @@ /* Delay transaction control */ pci_write_config8(dev, 0x43, 0xb); -#if CONFIG_EPIA_VT8237R_INIT +#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) /* I/O recovery time, default IDE routing */ pci_write_config8(dev, 0x4c, 0x04); @@ -555,7 +556,7 @@ /* Enable serial IRQ, 6PCI clocks. */ pci_write_config8(dev, 0x52, 0x9); #endif -#if CONFIG_HAVE_SMI_HANDLER +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) smm_lock(); #endif diff --git a/src/southbridge/via/vt8237r/nic.c b/src/southbridge/via/vt8237r/nic.c index ebebd37..aa60489 100644 --- a/src/southbridge/via/vt8237r/nic.c +++ b/src/southbridge/via/vt8237r/nic.c @@ -23,7 +23,7 @@ static void vt8237_eth_read_resources(struct device *dev) { -#if CONFIG_EPIA_VT8237R_INIT +#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) struct resource *res; /* Fix the I/O Resources of the USB2.0 Interface */ diff --git a/src/southbridge/via/vt8237r/pirq.c b/src/southbridge/via/vt8237r/pirq.c index ec393b4..fd55b1f 100644 --- a/src/southbridge/via/vt8237r/pirq.c +++ b/src/southbridge/via/vt8237r/pirq.c @@ -21,7 +21,7 @@ #include <device/pci_ids.h> #include <pc80/i8259.h> -#if (CONFIG_PIRQ_ROUTE == 1 && CONFIG_GENERATE_PIRQ_TABLE == 1) +#if IS_ENABLED(CONFIG_PIRQ_ROUTE) && IS_ENABLED(CONFIG_GENERATE_PIRQ_TABLE) void pirq_assign_irqs(const unsigned char route[4]) { device_t pdev; diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c index 42da53a..057a07d 100644 --- a/src/southbridge/via/vt8237r/usb.c +++ b/src/southbridge/via/vt8237r/usb.c @@ -21,13 +21,13 @@ #include "chip.h" #include "vt8237r.h" -#if CONFIG_EPIA_VT8237R_INIT +#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) u32 usb_io_addr[4] = {0xcc00, 0xd000, 0xd400, 0xd800}; #endif static void usb_i_init(struct device *dev) { -#if CONFIG_EPIA_VT8237R_INIT +#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) u8 reg8; printk(BIOS_DEBUG, "Entering %s\n", __func__); @@ -66,7 +66,7 @@ static void vt8237_usb_i_read_resources(struct device *dev) { -#if CONFIG_EPIA_VT8237R_INIT +#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) struct resource *res; u8 function = (u8) dev->path.pci.devfn & 0x7; @@ -92,7 +92,7 @@ static void usb_ii_init(struct device *dev) { struct southbridge_via_vt8237r_config *cfg; -#if CONFIG_EPIA_VT8237R_INIT +#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) u8 reg8; printk(BIOS_DEBUG, "Entering %s\n", __func__); @@ -136,7 +136,7 @@ static void vt8237_usb_ii_read_resources(struct device *dev) { -#if CONFIG_EPIA_VT8237R_INIT +#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT) struct resource *res; /* Fix the I/O Resources of the USB2.0 Interface */ diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h index 95f9750..f58b691 100644 --- a/src/southbridge/via/vt8237r/vt8237r.h +++ b/src/southbridge/via/vt8237r/vt8237r.h @@ -89,7 +89,7 @@ #define I2C_TRANS_CMD 0x40 #define CLOCK_SLAVE_ADDRESS 0x69 -#if CONFIG_DEBUG_SMBUS +#if IS_ENABLED(CONFIG_DEBUG_SMBUS) #define PRINT_DEBUG(x) printk(BIOS_DEBUG, x) #define PRINT_DEBUG_HEX16(x) printk(BIOS_DEBUG, "%04x", x) #else -- To view, visit https://review.coreboot.org/20353 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie965cbcf7f7b6f6c9e9a69e2a1ff0ba491246cbe Gerrit-Change-Number: 20353 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: src/drivers: add IS_ENABLED() around Kconfig symbol references
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20352 Change subject: src/drivers: add IS_ENABLED() around Kconfig symbol references ...................................................................... src/drivers: add IS_ENABLED() around Kconfig symbol references Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: Ib3a1cf04482a8f19b159c31cfb16a7b492748d91 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/drivers/elog/boot_count.c M src/drivers/elog/elog.c M src/drivers/intel/gma/int15.h M src/drivers/pc80/pc/i8254.c M src/drivers/pc80/rtc/mc146818rtc.c M src/drivers/pc80/rtc/mc146818rtc_romcc.c M src/drivers/uart/util.c M src/drivers/usb/ehci_debug.c 8 files changed, 19 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/20352/1 diff --git a/src/drivers/elog/boot_count.c b/src/drivers/elog/boot_count.c index 9d717d8..8988287 100644 --- a/src/drivers/elog/boot_count.c +++ b/src/drivers/elog/boot_count.c @@ -26,7 +26,7 @@ * This can either be declared as part of the option * table or statically defined in the board config. */ -#if CONFIG_USE_OPTION_TABLE +#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) # include "option_table.h" # define BOOT_COUNT_CMOS_OFFSET (CMOS_VSTART_boot_count_offset >> 3) #else diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 27b6e29..1c17561 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -13,13 +13,13 @@ * GNU General Public License for more details. */ -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) #include <arch/acpi.h> #endif #include <bootstate.h> #include <cbmem.h> #include <console/console.h> -#if CONFIG_ARCH_X86 +#if IS_ENABLED(CONFIG_ARCH_X86) #include <pc80/mc146818rtc.h> #endif #include <bcd.h> @@ -786,8 +786,8 @@ #if !defined(__SMM__) /* Log boot count event except in S3 resume */ -#if CONFIG_ELOG_BOOT_COUNT == 1 -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) if (!acpi_is_wakeup_s3()) #endif elog_add_event_dword(ELOG_TYPE_BOOT, boot_count_read()); @@ -796,9 +796,9 @@ elog_add_event_dword(ELOG_TYPE_BOOT, 0); #endif -#if CONFIG_ARCH_X86 +#if IS_ENABLED(CONFIG_ARCH_X86) /* Check and log POST codes from previous boot */ - if (CONFIG_CMOS_POST) + if (IS_ENABLED(CONFIG_CMOS_POST)) cmos_post_log(); #endif #endif diff --git a/src/drivers/intel/gma/int15.h b/src/drivers/intel/gma/int15.h index db83f6a..4a445e5 100644 --- a/src/drivers/intel/gma/int15.h +++ b/src/drivers/intel/gma/int15.h @@ -26,7 +26,7 @@ }; -#if CONFIG_VGA_ROM_RUN +#if IS_ENABLED(CONFIG_VGA_ROM_RUN) /* Install custom int15 handler for VGA OPROM */ void install_intel_vga_int15_handler(int active_lfp, int pfit, int display, int panel_type); #else diff --git a/src/drivers/pc80/pc/i8254.c b/src/drivers/pc80/pc/i8254.c index 5851ec0..eb91bf6 100644 --- a/src/drivers/pc80/pc/i8254.c +++ b/src/drivers/pc80/pc/i8254.c @@ -32,7 +32,7 @@ outb(0x12, TIMER1_PORT); } -#if CONFIG_UDELAY_TIMER2 +#if IS_ENABLED(CONFIG_UDELAY_TIMER2) static void load_timer2(unsigned int ticks) { /* Set up the timer gate, turn off the speaker */ diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 33860b8..0e9a88a 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -28,7 +28,7 @@ #include <cbfs.h> /* There's no way around this include guard. option_table.h is autogenerated */ -#if CONFIG_USE_OPTION_TABLE +#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) #include "option_table.h" #else #define LB_CKS_RANGE_START 0 diff --git a/src/drivers/pc80/rtc/mc146818rtc_romcc.c b/src/drivers/pc80/rtc/mc146818rtc_romcc.c index 8bebc42..dc4f2ef 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_romcc.c +++ b/src/drivers/pc80/rtc/mc146818rtc_romcc.c @@ -1,7 +1,7 @@ #include <stdint.h> #include <pc80/mc146818rtc.h> #include <fallback.h> -#if CONFIG_USE_OPTION_TABLE +#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) #include "option_table.h" #endif @@ -19,7 +19,7 @@ static int cmos_chksum_valid(void) { -#if CONFIG_USE_OPTION_TABLE +#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) unsigned char addr; u16 sum, old_sum; @@ -93,7 +93,7 @@ unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def) { -#if CONFIG_USE_OPTION_TABLE +#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) unsigned byte; byte = cmos_read(start/8); diff --git a/src/drivers/uart/util.c b/src/drivers/uart/util.c index e1b83ba..f0f885d 100644 --- a/src/drivers/uart/util.c +++ b/src/drivers/uart/util.c @@ -13,14 +13,14 @@ #include <console/console.h> #include <console/uart.h> -#if CONFIG_USE_OPTION_TABLE +#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) #include <option.h> #include "option_table.h" #endif unsigned int default_baudrate(void) { -#if !defined(__SMM__) && CONFIG_USE_OPTION_TABLE +#if !defined(__SMM__) && IS_ENABLED(CONFIG_USE_OPTION_TABLE) static const unsigned baud[8] = { 115200, 57600, 38400, 19200, 9600, 4800, 2400, 1200 }; unsigned b_index = 0; diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index cac043e..6fcf683 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -33,7 +33,7 @@ struct dbgp_pipe ep_pipe[DBGP_MAX_ENDPOINTS]; }; -#if CONFIG_DEBUG_USBDEBUG +#if IS_ENABLED(CONFIG_DEBUG_USBDEBUG) static void dbgp_print_data(struct ehci_dbg_port *ehci_debug); static int dbgp_enabled(void); # define dprintk(LEVEL, args...) \ @@ -197,7 +197,7 @@ bytes[i] = (hi >> (8*(i - 4))) & 0xff; } -#if CONFIG_DEBUG_USBDEBUG +#if IS_ENABLED(CONFIG_DEBUG_USBDEBUG) static void dbgp_print_data(struct ehci_dbg_port *ehci_debug) { u32 ctrl = read32(&ehci_debug->control); @@ -578,7 +578,7 @@ //return ret; next_debug_port: -#if CONFIG_USBDEBUG_DEFAULT_PORT==0 +#if CONFIG_USBDEBUG_DEFAULT_PORT == 0 port_map_tried |= (1 << (debug_port - 1)); new_debug_port = ((debug_port-1 + 1) % n_ports) + 1; if (port_map_tried != ((1 << n_ports) - 1)) { @@ -599,7 +599,7 @@ return -10; } -#if CONFIG_DEBUG_USBDEBUG +#if IS_ENABLED(CONFIG_DEBUG_USBDEBUG) static int dbgp_enabled(void) { struct dbgp_pipe *globals = &dbgp_ehci_info()->ep_pipe[DBGP_SETUP_EP0]; -- To view, visit https://review.coreboot.org/20352 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib3a1cf04482a8f19b159c31cfb16a7b492748d91 Gerrit-Change-Number: 20352 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: src/superio: add IS_ENABLED() around Kconfig symbol references
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20351 Change subject: src/superio: add IS_ENABLED() around Kconfig symbol references ...................................................................... src/superio: add IS_ENABLED() around Kconfig symbol references Change-Id: Ie9a7127b50db8dc9a2b543843ca4d815afe3d07e Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/superio/ite/it8716f/it8716f.h M src/superio/ite/it8716f/superio.c M src/superio/via/vt1211/vt1211.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/20351/1 diff --git a/src/superio/ite/it8716f/it8716f.h b/src/superio/ite/it8716f/it8716f.h index d4f40fa..3531a13 100644 --- a/src/superio/ite/it8716f/it8716f.h +++ b/src/superio/ite/it8716f/it8716f.h @@ -34,7 +34,7 @@ #define IT8716F_GAME 0x09 /* GAME port */ #define IT8716F_IR 0x0a /* Consumer IR */ -#if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL +#if IS_ENABLED(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) /* Provided by mainboard, called by IT8716F superio.c. */ void init_ec(u16 base); #endif diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c index 09c8bb9..2ec3875 100644 --- a/src/superio/ite/it8716f/superio.c +++ b/src/superio/ite/it8716f/superio.c @@ -27,7 +27,7 @@ #include "it8716f.h" -#if !CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL +#if !IS_ENABLED(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) static void init_ec(u16 base) { diff --git a/src/superio/via/vt1211/vt1211.c b/src/superio/via/vt1211/vt1211.c index c40741a..28586ba 100644 --- a/src/superio/via/vt1211/vt1211.c +++ b/src/superio/via/vt1211/vt1211.c @@ -112,7 +112,7 @@ { struct resource *res; -#if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO +#if IS_ENABLED(CONFIG_CONSOLE_SERIAL) && IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) /* TODO: Do the same for SP2? */ if (dev->path.pnp.device == VT1211_SP1) { for (res = dev->resource_list; res; res = res->next) { -- To view, visit https://review.coreboot.org/20351 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie9a7127b50db8dc9a2b543843ca4d815afe3d07e Gerrit-Change-Number: 20351 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: southbridge/intel: add IS_ENABLED() around Kconfig symbol re...
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20350 Change subject: southbridge/intel: add IS_ENABLED() around Kconfig symbol references ...................................................................... southbridge/intel: add IS_ENABLED() around Kconfig symbol references Change-Id: I2b532522938123bb7844cef94cda0b44bcb98e45 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/southbridge/intel/bd82x6x/finalize.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/bd82x6x/smi.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/spi.c M src/southbridge/intel/common/usb_debug.c M src/southbridge/intel/fsp_bd82x6x/early_init.c M src/southbridge/intel/fsp_bd82x6x/finalize.c M src/southbridge/intel/fsp_bd82x6x/lpc.c M src/southbridge/intel/fsp_bd82x6x/me.c M src/southbridge/intel/fsp_bd82x6x/me_8.x.c M src/southbridge/intel/fsp_bd82x6x/pch.h M src/southbridge/intel/fsp_bd82x6x/smi.c M src/southbridge/intel/fsp_bd82x6x/smihandler.c M src/southbridge/intel/fsp_i89xx/early_init.c M src/southbridge/intel/fsp_i89xx/finalize.c M src/southbridge/intel/fsp_i89xx/lpc.c M src/southbridge/intel/fsp_i89xx/me.c M src/southbridge/intel/fsp_i89xx/me_8.x.c M src/southbridge/intel/fsp_i89xx/pch.h M src/southbridge/intel/fsp_i89xx/romstage.c M src/southbridge/intel/fsp_i89xx/smi.c M src/southbridge/intel/fsp_i89xx/smihandler.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/fsp_rangeley/soc.h M src/southbridge/intel/i82371eb/isa.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/acpi/sleepstates.asl M src/southbridge/intel/i82801ix/i82801ix.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/ibexpeak/smi.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/lynxpoint/acpi/pch.asl M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/finalize.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/pmutil.c M src/southbridge/intel/lynxpoint/smi.c M src/southbridge/intel/lynxpoint/smihandler.c 48 files changed, 119 insertions(+), 119 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/20350/1 diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index 9c453e4..a9cfa38 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -45,7 +45,7 @@ /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); -#if CONFIG_SPI_FLASH_SMM +#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index c9fee89..bb9b817 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -76,7 +76,7 @@ /* Set packet length and toggle silent mode bit for one frame. */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); -#if !CONFIG_SERIRQ_CONTINUOUS_MODE +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); #endif @@ -285,7 +285,7 @@ if (rtc_failed) { reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(dev, GEN_PMCON_3, reg8); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) elog_add_event(ELOG_TYPE_RTC_RESET); #endif } @@ -668,7 +668,7 @@ gnvs->ndid = gfx->ndid; memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) chromeos_init_vboot(&(gnvs->chromeos)); #endif diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 0e5187c..70ba301 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -42,7 +42,7 @@ #include "me.h" #include "pch.h" -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -61,7 +61,7 @@ /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -457,7 +457,7 @@ } #endif -#if CONFIG_CHROMEOS && 0 /* DISABLED */ +#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ int mkhi_global_reset(void) { @@ -589,7 +589,7 @@ if (hfs.error_code || hfs.fpt_bad) path = ME_ERROR_BIOS_PATH; -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -678,7 +678,7 @@ } printk(BIOS_DEBUG, "\n"); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 94cec3e..2e29233 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -42,7 +42,7 @@ #include "me.h" #include "pch.h" -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -63,7 +63,7 @@ /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -424,7 +424,7 @@ } #endif -#if CONFIG_CHROMEOS && 0 /* DISABLED */ +#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ static int mkhi_global_reset(void) { @@ -576,7 +576,7 @@ path = ME_ERROR_BIOS_PATH; } -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -665,7 +665,7 @@ } printk(BIOS_DEBUG, "\n"); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif @@ -706,7 +706,7 @@ if (intel_me_read_mbp(&mbp_data)) break; -#if CONFIG_CHROMEOS && 0 /* DISABLED */ +#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ /* * Unlock ME in recovery mode. */ diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 1e05c9c..0ae9826 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -75,7 +75,7 @@ int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void gpi_route_interrupt(u8 gpi, u8 mode); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) void pch_log_state(void); #endif #else /* __PRE_RAM__ */ diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c index c7cb146..2248904 100644 --- a/src/southbridge/intel/bd82x6x/smi.c +++ b/src/southbridge/intel/bd82x6x/smi.c @@ -227,7 +227,7 @@ u16 pm1_en; u32 gpe0_en; -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) /* Log events from chipset before clearing */ pch_log_state(); #endif diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 4cef988..165acab 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -432,7 +432,7 @@ /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -534,7 +534,7 @@ return NULL; } -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -621,7 +621,7 @@ mainboard_finalized = 1; break; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) case ELOG_GSMI_APM_CNT: southbridge_smi_gsmi(); break; @@ -645,7 +645,7 @@ // power button pressed u32 reg32; reg32 = (7 << 10) | (1 << 13); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif outl(reg32, pmbase + PM1_CNT); diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 13db224..486d0db 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -187,7 +187,7 @@ SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 }; -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) static u8 readb_(const void *addr) { diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c index 23c732f..eeac6d9 100644 --- a/src/southbridge/intel/common/usb_debug.c +++ b/src/southbridge/intel/common/usb_debug.c @@ -27,7 +27,7 @@ u32 class; pci_devfn_t dev; -#if CONFIG_HAVE_USBDEBUG_OPTIONS +#if IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS) if (hcd_idx==2) dev = PCI_DEV(0, 0x1a, 0); else @@ -37,7 +37,7 @@ #endif class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8; -#if CONFIG_HAVE_USBDEBUG_OPTIONS +#if IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS) if (class != PCI_EHCI_CLASSCODE) { /* If we enter here before RCBA programming, EHCI function may * appear with the highest function number instead. diff --git a/src/southbridge/intel/fsp_bd82x6x/early_init.c b/src/southbridge/intel/fsp_bd82x6x/early_init.c index 54329c3..f9f3134 100644 --- a/src/southbridge/intel/fsp_bd82x6x/early_init.c +++ b/src/southbridge/intel/fsp_bd82x6x/early_init.c @@ -151,7 +151,7 @@ outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ printk(BIOS_DEBUG, " done.\n"); -#if CONFIG_ELOG_BOOT_COUNT +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) /* Increment Boot Counter for non-S3 resume */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) @@ -160,7 +160,7 @@ printk(BIOS_DEBUG, " done.\n"); -#if CONFIG_ELOG_BOOT_COUNT +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) /* Increment Boot Counter except when resuming from S3 */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) diff --git a/src/southbridge/intel/fsp_bd82x6x/finalize.c b/src/southbridge/intel/fsp_bd82x6x/finalize.c index 22165b9..5b65fb0 100644 --- a/src/southbridge/intel/fsp_bd82x6x/finalize.c +++ b/src/southbridge/intel/fsp_bd82x6x/finalize.c @@ -30,7 +30,7 @@ /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); -#if CONFIG_SPI_FLASH_SMM +#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index 963359f..4a5bf68 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -85,7 +85,7 @@ /* Set packet length and toggle silent mode bit for one frame. */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); -#if !CONFIG_SERIRQ_CONTINUOUS_MODE +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); #endif @@ -295,7 +295,7 @@ if (rtc_failed) { reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(dev, GEN_PMCON_3, reg8); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) elog_add_event(ELOG_TYPE_RTC_RESET); #endif } diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c index a634134..a4b5f03 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.c +++ b/src/southbridge/intel/fsp_bd82x6x/me.c @@ -41,7 +41,7 @@ #include "me.h" #include "pch.h" -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -60,7 +60,7 @@ /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -456,7 +456,7 @@ } #endif -#if CONFIG_CHROMEOS && 0 /* DISABLED */ +#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ int mkhi_global_reset(void) { @@ -588,7 +588,7 @@ if (hfs.error_code || hfs.fpt_bad) path = ME_ERROR_BIOS_PATH; -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -677,7 +677,7 @@ } printk(BIOS_DEBUG, "\n"); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c index 4001fb9..d89502e 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c +++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c @@ -40,7 +40,7 @@ #include "me.h" #include "pch.h" -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -61,7 +61,7 @@ /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -422,7 +422,7 @@ } #endif -#if CONFIG_CHROMEOS && 0 /* DISABLED */ +#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ static int mkhi_global_reset(void) { @@ -574,7 +574,7 @@ path = ME_ERROR_BIOS_PATH; } -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -663,7 +663,7 @@ } printk(BIOS_DEBUG, "\n"); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif @@ -704,7 +704,7 @@ if (intel_me_read_mbp(&mbp_data)) break; -#if CONFIG_CHROMEOS && 0 /* DISABLED */ +#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ /* * Unlock ME in recovery mode. */ diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h index 7fe40f7..84f21a7 100644 --- a/src/southbridge/intel/fsp_bd82x6x/pch.h +++ b/src/southbridge/intel/fsp_bd82x6x/pch.h @@ -67,7 +67,7 @@ int pch_silicon_supported(int type, int rev); void pch_enable(device_t dev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) void pch_log_state(void); #endif #else diff --git a/src/southbridge/intel/fsp_bd82x6x/smi.c b/src/southbridge/intel/fsp_bd82x6x/smi.c index d97801e..14637e6 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smi.c +++ b/src/southbridge/intel/fsp_bd82x6x/smi.c @@ -227,7 +227,7 @@ u16 pm1_en; u32 gpe0_en; -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) /* Log events from chipset before clearing */ pch_log_state(); #endif diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index 19337e9..394e0a9 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -331,7 +331,7 @@ /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -433,7 +433,7 @@ return NULL; } -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -505,7 +505,7 @@ printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) case ELOG_GSMI_APM_CNT: southbridge_smi_gsmi(); break; @@ -529,7 +529,7 @@ // power button pressed u32 reg32; reg32 = (7 << 10) | (1 << 13); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif outl(reg32, pmbase + PM1_CNT); diff --git a/src/southbridge/intel/fsp_i89xx/early_init.c b/src/southbridge/intel/fsp_i89xx/early_init.c index 887bf3c..7ce3c7f 100644 --- a/src/southbridge/intel/fsp_i89xx/early_init.c +++ b/src/southbridge/intel/fsp_i89xx/early_init.c @@ -38,7 +38,7 @@ outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ printk(BIOS_DEBUG, " done.\n"); -#if CONFIG_ELOG_BOOT_COUNT +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) /* Increment Boot Counter for non-S3 resume */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) @@ -47,7 +47,7 @@ printk(BIOS_DEBUG, " done.\n"); -#if CONFIG_ELOG_BOOT_COUNT +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) /* Increment Boot Counter except when resuming from S3 */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) diff --git a/src/southbridge/intel/fsp_i89xx/finalize.c b/src/southbridge/intel/fsp_i89xx/finalize.c index 22165b9..5b65fb0 100644 --- a/src/southbridge/intel/fsp_i89xx/finalize.c +++ b/src/southbridge/intel/fsp_i89xx/finalize.c @@ -30,7 +30,7 @@ /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); -#if CONFIG_SPI_FLASH_SMM +#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif diff --git a/src/southbridge/intel/fsp_i89xx/lpc.c b/src/southbridge/intel/fsp_i89xx/lpc.c index 5ba2969..8a815c5 100644 --- a/src/southbridge/intel/fsp_i89xx/lpc.c +++ b/src/southbridge/intel/fsp_i89xx/lpc.c @@ -85,7 +85,7 @@ /* Set packet length and toggle silent mode bit for one frame. */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); -#if !CONFIG_SERIRQ_CONTINUOUS_MODE +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); #endif @@ -295,7 +295,7 @@ if (rtc_failed) { reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(dev, GEN_PMCON_3, reg8); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) elog_add_event(ELOG_TYPE_RTC_RESET); #endif } diff --git a/src/southbridge/intel/fsp_i89xx/me.c b/src/southbridge/intel/fsp_i89xx/me.c index 704f209..4b5a4b3 100644 --- a/src/southbridge/intel/fsp_i89xx/me.c +++ b/src/southbridge/intel/fsp_i89xx/me.c @@ -41,7 +41,7 @@ #include "me.h" #include "pch.h" -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -60,7 +60,7 @@ /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -555,7 +555,7 @@ if (hfs.error_code || hfs.fpt_bad) path = ME_ERROR_BIOS_PATH; -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -644,7 +644,7 @@ } printk(BIOS_DEBUG, "\n"); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif diff --git a/src/southbridge/intel/fsp_i89xx/me_8.x.c b/src/southbridge/intel/fsp_i89xx/me_8.x.c index b68a5dc..b094524 100644 --- a/src/southbridge/intel/fsp_i89xx/me_8.x.c +++ b/src/southbridge/intel/fsp_i89xx/me_8.x.c @@ -40,7 +40,7 @@ #include "me.h" #include "pch.h" -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -61,7 +61,7 @@ /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -543,7 +543,7 @@ path = ME_ERROR_BIOS_PATH; } -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -632,7 +632,7 @@ } printk(BIOS_DEBUG, "\n"); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif diff --git a/src/southbridge/intel/fsp_i89xx/pch.h b/src/southbridge/intel/fsp_i89xx/pch.h index 6d8b873..9ae9467 100644 --- a/src/southbridge/intel/fsp_i89xx/pch.h +++ b/src/southbridge/intel/fsp_i89xx/pch.h @@ -65,7 +65,7 @@ int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_enable(device_t dev); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) void pch_log_state(void); #endif #else diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c index c2b5221..385e4d6 100644 --- a/src/southbridge/intel/fsp_i89xx/romstage.c +++ b/src/southbridge/intel/fsp_i89xx/romstage.c @@ -137,7 +137,7 @@ pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); post_code(0x46); if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Resume from S3 detected.\n"); boot_mode = 2; /* Clear SLP_TYPE. This will break stage2 but diff --git a/src/southbridge/intel/fsp_i89xx/smi.c b/src/southbridge/intel/fsp_i89xx/smi.c index f28d966..6dc58f0 100644 --- a/src/southbridge/intel/fsp_i89xx/smi.c +++ b/src/southbridge/intel/fsp_i89xx/smi.c @@ -227,7 +227,7 @@ u16 pm1_en; u32 gpe0_en; -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) /* Log events from chipset before clearing */ pch_log_state(); #endif diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c index 099fb84..ff76c20 100644 --- a/src/southbridge/intel/fsp_i89xx/smihandler.c +++ b/src/southbridge/intel/fsp_i89xx/smihandler.c @@ -331,7 +331,7 @@ /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -433,7 +433,7 @@ return NULL; } -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -505,7 +505,7 @@ printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) case ELOG_GSMI_APM_CNT: southbridge_smi_gsmi(); break; @@ -529,7 +529,7 @@ // power button pressed u32 reg32; reg32 = (7 << 10) | (1 << 13); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif outl(reg32, pmbase + PM1_CNT); diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index d621a41..cbb2297 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -94,7 +94,7 @@ /* Set packet length and toggle silent mode bit for one frame. */ write8(ibase + ILB_SERIRQ_CNTL, (1 << 7)); -#if !CONFIG_SERIRQ_CONTINUOUS_MODE +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) write8(ibase + ILB_SERIRQ_CNTL, 0); #endif } @@ -435,7 +435,7 @@ memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); acpi_save_gnvs((unsigned long)gnvs); -#if CONFIG_HAVE_SMI_HANDLER +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); #endif diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index 0674dca..4409f1e 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -65,7 +65,7 @@ #include <arch/acpi.h> void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) void soc_log_state(void); #endif #else diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index bd0e964..2bab05c 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -28,7 +28,7 @@ #endif #include "i82371eb.h" -#if CONFIG_IOAPIC +#if IS_ENABLED(CONFIG_IOAPIC) static void enable_intel_82093aa_ioapic(void) { u16 reg16; @@ -84,7 +84,7 @@ /* Initialize ISA DMA. */ isa_dma_init(); -#if CONFIG_IOAPIC +#if IS_ENABLED(CONFIG_IOAPIC) /* * Unlike most other southbridges the 82371EB doesn't have a built-in * IOAPIC. Instead, 82371EB-based boards that support multiple CPUs @@ -115,7 +115,7 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_RESERVE; -#if CONFIG_IOAPIC +#if IS_ENABLED(CONFIG_IOAPIC) res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR; res->size = 0x00001000; diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index e650d82..a26b9f8 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -329,7 +329,7 @@ RCBA32(CG) = reg32; } -#if CONFIG_HAVE_SMI_HANDLER +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) static void i82801gx_lock_smm(struct device *dev) { #if TEST_SMM_FLASH_LOCKDOWN @@ -448,7 +448,7 @@ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); -#if CONFIG_HAVE_SMI_HANDLER +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) i82801gx_lock_smm(dev); #endif diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 6bd9517..d3c32fd 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -414,7 +414,7 @@ printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break; } -#if !CONFIG_SMM_TSEG +#if !IS_ENABLED(CONFIG_SMM_TSEG) /* Unlock the SMI semaphore. We're currently in SMM, and the semaphore * will never be unlocked because the next outl will switch off the CPU. * This might open a small race between the smi_release_lock() and the outl() diff --git a/src/southbridge/intel/i82801ix/acpi/sleepstates.asl b/src/southbridge/intel/i82801ix/acpi/sleepstates.asl index 62bb026..d7fb2a5 100644 --- a/src/southbridge/intel/i82801ix/acpi/sleepstates.asl +++ b/src/southbridge/intel/i82801ix/acpi/sleepstates.asl @@ -15,7 +15,7 @@ */ Name(\_S0, Package(){0x0,0x0,0x0,0x0}) -#if !CONFIG_HAVE_ACPI_RESUME +#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) Name(\_S1, Package(){0x1,0x0,0x0,0x0}) #else Name(\_S3, Package(){0x5,0x0,0x0,0x0}) diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index 0f3a08c..7d44fba 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -222,7 +222,7 @@ i82801ix_hide_functions(); /* Reset watchdog timer. */ -#if !CONFIG_HAVE_SMI_HANDLER +#if !IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */ #endif outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */ diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 8212b0a..bc45b9d 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -369,7 +369,7 @@ RCBA32(0x38c0) |= 7; } -#if CONFIG_HAVE_SMI_HANDLER +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) static void i82801ix_lock_smm(struct device *dev) { #if TEST_SMM_FLASH_LOCKDOWN @@ -464,7 +464,7 @@ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); -#if CONFIG_HAVE_SMI_HANDLER +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) i82801ix_lock_smm(dev); #endif } diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index f01d8b2..a152dfe 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -71,7 +71,7 @@ /* Set packet length and toggle silent mode bit for one frame. */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); -#if !CONFIG_SERIRQ_CONTINUOUS_MODE +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); #endif @@ -280,7 +280,7 @@ if (rtc_failed) { reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(dev, GEN_PMCON_3, reg8); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) elog_add_event(ELOG_TYPE_RTC_RESET); #endif } diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index da6bfa8..70dbcbf 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -41,7 +41,7 @@ #include "me.h" #include "pch.h" -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -60,7 +60,7 @@ /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -470,7 +470,7 @@ if (hfs.error_code || hfs.fpt_bad) path = ME_ERROR_BIOS_PATH; -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -559,7 +559,7 @@ } printk(BIOS_DEBUG, "\n"); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index d87f8e0..63307d9 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -70,7 +70,7 @@ int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void gpi_route_interrupt(u8 gpi, u8 mode); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) void pch_log_state(void); #endif #else /* __PRE_RAM__ */ diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c index 950dbe0..f1bcf03 100644 --- a/src/southbridge/intel/ibexpeak/smi.c +++ b/src/southbridge/intel/ibexpeak/smi.c @@ -228,7 +228,7 @@ u16 pm1_en; u32 gpe0_en; -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) /* Log events from chipset before clearing */ pch_log_state(); #endif diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index a0b963e..88f64f1 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -433,7 +433,7 @@ /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -535,7 +535,7 @@ return NULL; } -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -607,7 +607,7 @@ printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) case ELOG_GSMI_APM_CNT: southbridge_smi_gsmi(); break; @@ -631,7 +631,7 @@ // power button pressed u32 reg32; reg32 = (7 << 10) | (1 << 13); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif outl(reg32, pmbase + PM1_CNT); diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index c30bfa4..fbbd26d 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -96,7 +96,7 @@ #include "smbus.asl" // Serial IO -#if CONFIG_INTEL_LYNXPOINT_LP +#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) #include "serialio.asl" #include "lpt_lp.asl" #endif diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 0e4fa3d..cb4bc7e 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -24,7 +24,7 @@ #include "pch.h" #include "chip.h" -#if CONFIG_INTEL_LYNXPOINT_LP +#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) #include "lp_gpio.h" #else #include "southbridge/intel/common/gpio.h" @@ -133,7 +133,7 @@ pch_enable_bars(); -#if CONFIG_INTEL_LYNXPOINT_LP +#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) setup_pch_lp_gpios(gpio_map); #else setup_pch_gpios(gpio_map); @@ -154,7 +154,7 @@ wake_from_s3 = sleep_type_s3(); -#if CONFIG_ELOG_BOOT_COUNT +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) if (!wake_from_s3) boot_count_increment(); #endif diff --git a/src/southbridge/intel/lynxpoint/finalize.c b/src/southbridge/intel/lynxpoint/finalize.c index 1ff38e9..39a555e 100644 --- a/src/southbridge/intel/lynxpoint/finalize.c +++ b/src/southbridge/intel/lynxpoint/finalize.c @@ -34,7 +34,7 @@ /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); -#if CONFIG_SPI_FLASH_SMM +#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index d295c88..55edaf9 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -77,7 +77,7 @@ /* Set packet length and toggle silent mode bit for one frame. */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); -#if !CONFIG_SERIRQ_CONTINUOUS_MODE +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); #endif @@ -292,7 +292,7 @@ if (rtc_failed) { reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(dev, GEN_PMCON_3, reg8); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) elog_add_event(ELOG_TYPE_RTC_RESET); #endif } @@ -498,7 +498,7 @@ static void pch_set_acpi_mode(void) { -#if CONFIG_HAVE_SMI_HANDLER +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) if (!acpi_is_wakeup_s3()) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); @@ -760,7 +760,7 @@ gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) chromeos_init_vboot(&(gnvs->chromeos)); #endif diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 355db4b..c393feb 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -37,7 +37,7 @@ #include "me.h" #include "pch.h" -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -59,7 +59,7 @@ static u32 *mei_base_address; void intel_me_mbp_clear(device_t dev); -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -519,7 +519,7 @@ #endif /* CONFIG_DEBUG_INTEL_ME */ #endif -#if CONFIG_CHROMEOS && 0 /* DISABLED */ +#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ static int mkhi_global_reset(void) { @@ -579,7 +579,7 @@ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) return; -#if CONFIG_ME_MBP_CLEAR_LATE +#if IS_ENABLED(CONFIG_ME_MBP_CLEAR_LATE) /* Wait for ME MBP Cleared indicator */ intel_me_mbp_clear(PCH_ME_DEV); #endif @@ -707,7 +707,7 @@ path = ME_ERROR_BIOS_PATH; } -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -796,7 +796,7 @@ } printk(BIOS_DEBUG, "\n"); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif @@ -835,7 +835,7 @@ #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) me_print_fw_version(mbp_data.fw_version_name); -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) me_print_fwcaps(mbp_data.fw_capabilities); #endif @@ -991,7 +991,7 @@ host.interrupt_generate = 1; write_host_csr(&host); -#if !CONFIG_ME_MBP_CLEAR_LATE +#if !IS_ENABLED(CONFIG_ME_MBP_CLEAR_LATE) /* Wait for the mbp_cleared indicator. */ intel_me_mbp_clear(dev); #endif @@ -1000,7 +1000,7 @@ #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", mbp->header.num_entries, mbp->header.mbp_size); -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) for (i = 0; i < mbp->header.mbp_size - 1; i++) { printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); } diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 8cae50a..9b061c6 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -72,7 +72,7 @@ #define SMBUS_IO_BASE 0x0400 #define SMBUS_SLAVE_ADDR 0x24 -#if CONFIG_INTEL_LYNXPOINT_LP +#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) #define DEFAULT_PMBASE 0x1000 #define DEFAULT_GPIOBASE 0x1400 #define DEFAULT_GPIOSIZE 0x400 @@ -181,7 +181,7 @@ u32 pch_iobp_read(u32 address); void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) void pch_log_state(void); #endif void acpi_create_intel_hpet(acpi_hpet_t * hpet); diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index 90045d1..d70cb5d 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -26,7 +26,7 @@ #include <console/console.h> #include "pch.h" -#if CONFIG_INTEL_LYNXPOINT_LP +#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) #include "lp_gpio.h" #endif diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 8c9cb58..5f1bdf7 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -29,7 +29,7 @@ { u32 smi_en; -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) /* Log events from chipset before clearing */ pch_log_state(); #endif @@ -123,7 +123,7 @@ /* * Finalize system before payload boot if not in ChromeOS environment. */ -#if !CONFIG_CHROMEOS +#if !IS_ENABLED(CONFIG_CHROMEOS) static void finalize_boot(void *unused) { diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 0102308..37a7a2b 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -130,13 +130,13 @@ mainboard_smi_sleep(slp_typ); /* USB sleep preparations */ -#if !CONFIG_FINALIZE_USB_ROUTE_XHCI +#if !IS_ENABLED(CONFIG_FINALIZE_USB_ROUTE_XHCI) usb_ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ); usb_ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ); #endif usb_xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -243,7 +243,7 @@ return NULL; } -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -314,7 +314,7 @@ case 0xca: usb_xhci_route_all(); break; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) case ELOG_GSMI_APM_CNT: southbridge_smi_gsmi(); break; @@ -333,7 +333,7 @@ */ if (pm1_sts & PWRBTN_STS) { // power button pressed -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif disable_pm1_control(-1UL); -- To view, visit https://review.coreboot.org/20350 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2b532522938123bb7844cef94cda0b44bcb98e45 Gerrit-Change-Number: 20350 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: southbridge/amd: add IS_ENABLED() around Kconfig symbol refe...
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20349 Change subject: southbridge/amd: add IS_ENABLED() around Kconfig symbol references ...................................................................... southbridge/amd: add IS_ENABLED() around Kconfig symbol references Change-Id: I8fabb7331435eb518a5c95cb29c4ff5ca98560d2 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/southbridge/amd/agesa/hudson/acpi/fch.asl M src/southbridge/amd/agesa/hudson/acpi/usb.asl M src/southbridge/amd/agesa/hudson/fadt.c M src/southbridge/amd/agesa/hudson/hudson.c M src/southbridge/amd/agesa/hudson/imc.c M src/southbridge/amd/agesa/hudson/spi.c M src/southbridge/amd/amd8111/acpi.c M src/southbridge/amd/amd8111/lpc.c M src/southbridge/amd/cimx/sb700/Platform.h M src/southbridge/amd/cimx/sb800/SBPLATFORM.h M src/southbridge/amd/cimx/sb800/bootblock.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/cimx/sb900/early.c M src/southbridge/amd/cs5536/early_setup.c M src/southbridge/amd/cs5536/pirq.c M src/southbridge/amd/pi/hudson/acpi/fch.asl M src/southbridge/amd/pi/hudson/acpi/sleepstates.asl M src/southbridge/amd/pi/hudson/acpi/usb.asl M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/amd/rs690/cmn.c M src/southbridge/amd/rs690/ht.c M src/southbridge/amd/rs780/cmn.c M src/southbridge/amd/rs780/early_setup.c M src/southbridge/amd/rs780/gfx.c M src/southbridge/amd/rs780/rs780.c M src/southbridge/amd/sb700/early_setup.c M src/southbridge/amd/sb700/lpc.c M src/southbridge/amd/sb700/sata.c M src/southbridge/amd/sb700/sb700.c M src/southbridge/amd/sb700/usb.c M src/southbridge/amd/sr5650/early_setup.c 31 files changed, 60 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/20349/1 diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index 7b0232a..bc9e4c1 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -62,7 +62,7 @@ Name(_ADR, 0x00140007) } /* end SDCN */ -#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE +#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) /* 0:14.4 - PCI slot 1, 2, 3 */ Device(PIBR) { @@ -175,7 +175,7 @@ /* Determine the OS we're running on */ OSFL() -#if defined(CONFIG_HUDSON_IMC_FWM) && CONFIG_HUDSON_IMC_FWM +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) && IS_ENABLED(CONFIG_HUDSON_IMC_FWM) #include "acpi/AmdImc.asl" /* Hudson IMC function */ ITZE() /* enable IMC Fan Control*/ #endif diff --git a/src/southbridge/amd/agesa/hudson/acpi/usb.asl b/src/southbridge/amd/agesa/hudson/acpi/usb.asl index 0794bf3..d83b935 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/usb.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/usb.asl @@ -50,7 +50,7 @@ Name(_PRW, Package() {0x0B, 3}) } /* end UOH5 */ -#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE +#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) /* 0:14.5 - OHCI */ Device(UEH1) { Name(_ADR, 0x00140005) @@ -64,7 +64,7 @@ Name(_PRW, Package() {0x0B, 4}) } /* end XHC0 */ -#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE +#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) /* 0:10.1 - XHCI 1*/ Device(XHC1) { Name(_ADR, 0x00100001) diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index 276ded2..c1d9b72 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -25,7 +25,7 @@ #include "hudson.h" #include "smi.h" -#if CONFIG_HUDSON_LEGACY_FREE +#if IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE) #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE #else #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042) diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index 20af2e7..101f5d4 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -181,7 +181,7 @@ static void hudson_final(void *chip_info) { -#if !CONFIG_ACPI_ENABLE_THERMAL_ZONE +#if !IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE) #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) /* AMD AGESA does not enable thermal zone, so we enable it here. */ enable_imc_thermal_zone(); diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c index 049eca95..799cc32 100644 --- a/src/southbridge/amd/agesa/hudson/imc.c +++ b/src/southbridge/amd/agesa/hudson/imc.c @@ -35,7 +35,7 @@ write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x03, 0xff); write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x04, 0xff); -#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE +#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x10, 0x06); write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x11, 0x06); write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x12, 0xf7); @@ -43,7 +43,7 @@ write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x14, 0xff); #endif -#if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) UINT8 PciData; PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index 71fddc6..46121db 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -110,7 +110,7 @@ readoffby1 = bytesout ? 0 : 1; -#if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) spi_write(0x1E, 5); spi_write(0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */ spi_write(0x1E, 6); diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c index 2a6cf8d..fd3fe49 100644 --- a/src/southbridge/amd/amd8111/acpi.c +++ b/src/southbridge/amd/amd8111/acpi.c @@ -89,7 +89,7 @@ } -#if CONFIG_HAVE_ACPI_TABLES +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) unsigned pm_base; #endif @@ -161,7 +161,7 @@ (on*12)+(on>>1),(on&1)*5); } -#if CONFIG_HAVE_ACPI_TABLES +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) pm_base = pci_read_config16(dev, 0x58) & 0xff00; printk(BIOS_DEBUG, "pm_base: 0x%04x\n",pm_base); #endif diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index 8841760..00c56f6 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -129,7 +129,7 @@ } static void southbridge_acpi_fill_ssdt_generator(device_t device) { -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) amd_generate_powernow(pm_base + 0x10, 6, 1); acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); #endif diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h index 7476cb9..08cff4a 100644 --- a/src/southbridge/amd/cimx/sb700/Platform.h +++ b/src/southbridge/amd/cimx/sb700/Platform.h @@ -59,7 +59,7 @@ #ifdef TRACE #undef TRACE #endif - #if CONFIG_REDIRECT_SBCIMX_TRACE_TO_SERIAL + #if IS_ENABLED(CONFIG_REDIRECT_SBCIMX_TRACE_TO_SERIAL) #define TRACE(Arguments) printk Arguments #else #define TRACE(Arguments) do {} while (0) diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index c933207..7d3c7de 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -49,7 +49,7 @@ #endif #define FIXUP_PTR(ptr) ptr -#if CONFIG_SB800_IMC_FWM +#if IS_ENABLED(CONFIG_SB800_IMC_FWM) #define IMC_ENABLE_OVER_WRITE 0x01 #endif @@ -154,7 +154,7 @@ #include "vendorcode/amd/cimx/sb800/AMDSBLIB.h" -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) #include <spi-generic.h> #endif diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 008a19b..585d5a8 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -99,7 +99,7 @@ // change twice. reg32 = *acpi_mmio; reg32 &= ~((1 << 2) | (3 << 0)); // enable, 14 MHz (power up default) -#if !CONFIG_SUPERIO_WANTS_14MHZ_CLOCK +#if !IS_ENABLED(CONFIG_SUPERIO_WANTS_14MHZ_CLOCK) reg32 |= 2 << 0; // Device_CLK1_sel = 48 MHz #endif *acpi_mmio = reg32; diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index f4b1769..6b3af0e 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -372,7 +372,7 @@ case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ clear_ioapic(VIO_APIC_VADDR); -#if CONFIG_CPU_AMD_AGESA +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA) /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); #else @@ -406,9 +406,9 @@ case (0x14 << 3) | 3: /* 0:14:3 LPC */ /* Initialize the fans */ -#if CONFIG_SB800_IMC_FAN_CONTROL +#if IS_ENABLED(CONFIG_SB800_IMC_FAN_CONTROL) init_sb800_IMC_fans(dev); -#elif CONFIG_SB800_MANUAL_FAN_CONTROL +#elif IS_ENABLED(CONFIG_SB800_MANUAL_FAN_CONTROL) init_sb800_MANUAL_fans(dev); #endif break; diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c index bee7d74..1f787f9 100644 --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -96,7 +96,7 @@ void sb_After_Pci_Init(void) { -#if !CONFIG_BOARD_AMD_DINAR +#if !IS_ENABLED(CONFIG_BOARD_AMD_DINAR) AMDSBCFG sb_early_cfg; printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - Start.\n"); @@ -128,7 +128,7 @@ void sb_Late_Post(void) { -#if !CONFIG_BOARD_AMD_DINAR +#if !IS_ENABLED(CONFIG_BOARD_AMD_DINAR) AMDSBCFG sb_early_cfg; u8 data; diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c index 013607b..6c69222 100644 --- a/src/southbridge/amd/cs5536/early_setup.c +++ b/src/southbridge/amd/cs5536/early_setup.c @@ -88,7 +88,7 @@ static void cs5536_setup_power_button(void) { -#if CONFIG_ENABLE_POWER_BUTTON +#if IS_ENABLED(CONFIG_ENABLE_POWER_BUTTON) outl(0x40020000, PMS_IO_BASE + 0x40); #endif diff --git a/src/southbridge/amd/cs5536/pirq.c b/src/southbridge/amd/cs5536/pirq.c index 0352dbc..466a2dc 100644 --- a/src/southbridge/amd/cs5536/pirq.c +++ b/src/southbridge/amd/cs5536/pirq.c @@ -19,7 +19,7 @@ #include <device/pci.h> #include <device/pci_ids.h> -#if (CONFIG_PIRQ_ROUTE == 1 && CONFIG_GENERATE_PIRQ_TABLE == 1) +#if IS_ENABLED(CONFIG_PIRQ_ROUTE) && IS_ENABLED(CONFIG_GENERATE_PIRQ_TABLE) void pirq_assign_irqs(const unsigned char pIntAtoD[4]) { device_t pdev; diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl index b8c0b35..5f00436 100644 --- a/src/southbridge/amd/pi/hudson/acpi/fch.asl +++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl @@ -51,7 +51,7 @@ #include "usb.asl" /* 0:14.2 - HD Audio */ -#if !CONFIG_SOUTHBRIDGE_AMD_PI_KERN +#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) #include "audio.asl" #endif diff --git a/src/southbridge/amd/pi/hudson/acpi/sleepstates.asl b/src/southbridge/amd/pi/hudson/acpi/sleepstates.asl index d93f068..c8ad520 100644 --- a/src/southbridge/amd/pi/hudson/acpi/sleepstates.asl +++ b/src/southbridge/amd/pi/hudson/acpi/sleepstates.asl @@ -23,7 +23,7 @@ If (LAnd(SSFG, 0x02)) { Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ } -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) If (LAnd(SSFG, 0x04)) { Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ } diff --git a/src/southbridge/amd/pi/hudson/acpi/usb.asl b/src/southbridge/amd/pi/hudson/acpi/usb.asl index 1989017..26192af 100644 --- a/src/southbridge/amd/pi/hudson/acpi/usb.asl +++ b/src/southbridge/amd/pi/hudson/acpi/usb.asl @@ -50,7 +50,7 @@ Name(_PRW, Package() {0x0B, 3}) } /* end UOH5 */ -#if !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_KERN +#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) && !CONFIG_SOUTHBRIDGE_AMD_PI_KERN /* 0:14.5 - OHCI */ Device(UEH1) { Name(_ADR, 0x00140005) @@ -64,7 +64,7 @@ Name(_PRW, Package() {0x0B, 4}) } /* end XHC0 */ -#if !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_KERN +#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) && !CONFIG_SOUTHBRIDGE_AMD_PI_KERN /* 0:10.1 - XHCI 1*/ Device(XHC1) { Name(_ADR, 0x00100001) diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index ce8ce6d..84c6a1d 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -25,7 +25,7 @@ #include "hudson.h" #include "smi.h" -#if CONFIG_HUDSON_LEGACY_FREE +#if IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE) #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE #else #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042) diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c index 2ca92c3..7ef9ac0 100644 --- a/src/southbridge/amd/rs690/cmn.c +++ b/src/southbridge/amd/rs690/cmn.c @@ -308,7 +308,7 @@ void rs690_set_tom(device_t nb_dev) { /* set TOM */ -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) pci_write_config32(nb_dev, 0x90, uma_memory_base); nbmc_write_index(nb_dev, 0x1e, uma_memory_base); #else diff --git a/src/southbridge/amd/rs690/ht.c b/src/southbridge/amd/rs690/ht.c index bbb33ef..3c56a37 100644 --- a/src/southbridge/amd/rs690/ht.c +++ b/src/southbridge/amd/rs690/ht.c @@ -24,7 +24,7 @@ static void ht_dev_set_resources(device_t dev) { -#if CONFIG_EXT_CONF_SUPPORT +#if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT) unsigned reg; device_t k8_f1; resource_t rbase, rend; @@ -83,7 +83,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) { -#if CONFIG_EXT_CONF_SUPPORT +#if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT) struct resource *res; resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; // default @@ -100,7 +100,7 @@ static void ht_dev_read_resources(device_t dev) { -#if CONFIG_EXT_CONF_SUPPORT +#if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT) struct resource *res; printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__); @@ -109,7 +109,7 @@ pci_dev_read_resources(dev); -#if CONFIG_EXT_CONF_SUPPORT +#if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT) /* Add an MMCONFIG resource. */ res = new_resource(dev, 0x1C); res->base = EXT_CONF_BASE_ADDRESS; diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index 49ba6eb..afa1aff 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -349,7 +349,7 @@ void rs780_set_tom(device_t nb_dev) { /* set TOM */ -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) pci_write_config32(nb_dev, 0x90, uma_memory_base); //nbmc_write_index(nb_dev, 0x1e, uma_memory_base); #else diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c index b0a40be..ec6c602 100644 --- a/src/southbridge/amd/rs780/early_setup.c +++ b/src/southbridge/amd/rs780/early_setup.c @@ -97,7 +97,7 @@ } } /* family 10 only, for reg > 0xFF */ -#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) static void set_fam10_ext_cfg_enable_bits(pci_devfn_t fam10_dev, u32 reg_pos, u32 mask, u32 val) { @@ -143,7 +143,7 @@ return (cpuid_eax(1) & 0xff00000) != 0; } -#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) static u8 l3_cache(void) { return (cpuid_edx(0x80000006) & (0x3FFF << 18)) != 0; @@ -242,7 +242,7 @@ } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) { printk(BIOS_INFO, "rs780_htinit: HT3 mode\n"); - #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 + #if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) /* HT3 mode, RPR 8.4.3 */ set_nbcfg_enable_bits(rs780_f0, 0x9c, 0x3 << 16, 0); @@ -282,7 +282,7 @@ } } -#if !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 +#if !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) /******************************************************* * Optimize k8 with UMA. * See BKDG_NPT_0F guide for details. @@ -338,7 +338,7 @@ #define k8_optimization() do {} while (0) #endif /* !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */ -#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) static void fam10_optimization(void) { pci_devfn_t cpu_f0, cpu_f2, cpu_f3; diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index 02be1f3..7f8bcb0 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -382,7 +382,7 @@ /* GFX_InitFBAccess finished. */ -#if CONFIG_GFXUMA /* for UMA mode. */ +#if IS_ENABLED(CONFIG_GFXUMA) /* for UMA mode. */ /* GFX_StartMC. */ set_nbmc_enable_bits(nb_dev, 0x02, 0x00000000, 0x80000000); set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000001); @@ -444,7 +444,7 @@ vgainfo.sHeader.ucTableFormatRevision = 1; vgainfo.sHeader.ucTableContentRevision = 2; -#if !CONFIG_GFXUMA /* SP mode. */ +#if !IS_ENABLED(CONFIG_GFXUMA) /* SP mode. */ // Side port support is incomplete, do not use it // These parameters must match the motherboard vgainfo.ulBootUpSidePortClock = 667*100; @@ -629,7 +629,7 @@ /* Transfer the Table to VBIOS. */ pointer = (u32 *)&vgainfo; for (i = 0; i < sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) { -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) *GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i; #else *GpuF0MMReg = 0x80000000 + 0x8000000 - 512 + i; @@ -758,7 +758,7 @@ device_t nb_dev = dev_find_slot(0, 0); msr_t sysmem; -#if !CONFIG_GFXUMA +#if !IS_ENABLED(CONFIG_GFXUMA) u32 FB_Start, FB_End; #endif @@ -801,7 +801,7 @@ set_nbmc_enable_bits(nb_dev, 0x25, 0xffffffff, 0x111f111f); set_htiu_enable_bits(nb_dev, 0x37, 1<<24, 1<<24); -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) /* GFX_InitUMA. */ /* Copy CPU DDR Controller to NB MC. */ device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1)); diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index c2da54d..10263f2 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -206,7 +206,7 @@ /* Program Straps. */ romstrap2 = 1 << 26; // enables audio function -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) // bits 7-9: aperture size // 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g if (uma_memory_size == 0x02000000) romstrap2 |= 3 << 7; diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 3ed4cac..0cd65a6 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -152,7 +152,7 @@ reg32 |= 1 << 20; pci_write_config32(dev, 0x64, reg32); -#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) post_code(0x66); dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ reg8 = pci_read_config8(dev, 0xBB); @@ -166,7 +166,7 @@ // XXX Serial port decode on LPC is hardcoded to 0x3f8 reg8 = pci_read_config8(dev, 0x44); reg8 |= 1 << 6; -#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) #if CONFIG_TTYS0_BASE == 0x2f8 reg8 |= 1 << 7; #endif @@ -532,7 +532,7 @@ pci_write_config8(dev, 0x50, 0x01); if (!sata_ahci_mode){ -#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) /* SP5100 default SATA mode is RAID5 MODE */ dev = pci_locate_device(PCI_ID(0x1002, 0x4392), 0); @@ -688,7 +688,7 @@ byte |= 0xc0; pmio_write(0xbb, byte); -#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) /* RPR 2.26 Alter CPU reset timing */ byte = pmio_read(0xb2); byte |= 0x1 << 2; /* Enable CPU reset timing option */ diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index fda30b8..8ee0395 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -47,7 +47,7 @@ pci_write_config32(sm_dev, 0x64, dword); /* Initialize isa dma */ -#if CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT) printk(BIOS_DEBUG, "Skipping isa_dma_init() to avoid getting stuck.\n"); #else isa_dma_init(); @@ -68,7 +68,7 @@ /* Disable LPC MSI Capability */ byte = pci_read_config8(dev, 0x78); byte &= ~(1 << 1); -#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) /* Disable FlowContrl, Always service the request from Host * whenever there is a request from Host pending */ diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index 235278d..537c2c0 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -350,7 +350,7 @@ byte |= 7 << 0; pci_write_config8(dev, 0x4, byte); -#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) /* Master Latency Timer */ pci_write_config32(dev, 0xC, 0x00004000); #endif diff --git a/src/southbridge/amd/sb700/sb700.c b/src/southbridge/amd/sb700/sb700.c index 74650e7..1068721 100644 --- a/src/southbridge/amd/sb700/sb700.c +++ b/src/southbridge/amd/sb700/sb700.c @@ -222,7 +222,7 @@ } } -#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) struct chip_operations southbridge_amd_sb700_ops = { CHIP_NAME("ATI SP5100") .enable_dev = sb7xx_51xx_enable, diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c index 0fdff78..6276008 100644 --- a/src/southbridge/amd/sb700/usb.c +++ b/src/southbridge/amd/sb700/usb.c @@ -181,7 +181,7 @@ dword |= 1 << 8; dword &= ~(1 << 27); /* 6.23 */ } -#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) /* SP5100 Erratum 36 */ dword &= ~(1 << 26); if (!ehci_async_data_cache) diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index fce25ab..6b4d81a 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -50,7 +50,8 @@ /* family 10 only, for reg > 0xFF */ -#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) || \ + IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10) static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask, u32 val) { @@ -221,7 +222,8 @@ /* Enable Protocol checker */ set_htiu_enable_bits(sr5650_f0, 0x1E, 0xFFFFFFFF, 0x7FFFFFFC); -#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 /* save some spaces */ +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) || \ + IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10) /* HT3 mode, RPR 5.4.3 */ set_nbcfg_enable_bits(sr5650_f0, 0x9c, 0x3 << 16, 0); @@ -299,7 +301,8 @@ } } -#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 /* save some spaces */ +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) || \ + IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10) void fam10_optimization(void) { device_t cpu_f0, cpu_f2, cpu_f3; -- To view, visit https://review.coreboot.org/20349 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8fabb7331435eb518a5c95cb29c4ff5ca98560d2 Gerrit-Change-Number: 20349 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: soc/intel: add IS_ENABLED() around Kconfig symbol references
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20348 Change subject: soc/intel: add IS_ENABLED() around Kconfig symbol references ...................................................................... soc/intel: add IS_ENABLED() around Kconfig symbol references Change-Id: I3c5f9e0d3d1efdd83442ce724043729c8648ea64 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/include/soc/pmc.h M src/soc/intel/baytrail/include/soc/ramstage.h M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/spi.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/include/soc/ramstage.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/broadwell/spi.c M src/soc/intel/common/acpi/acpi_debug.asl M src/soc/intel/fsp_baytrail/acpi/sleepstates.asl 19 files changed, 45 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/20348/1 diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 39ffa20..b3f5ea6 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -85,15 +85,15 @@ /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); -#if CONFIG_CONSOLE_CBMEM +#if IS_ENABLED(CONFIG_CONSOLE_CBMEM) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); #endif -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Initialize Verified Boot data */ chromeos_init_vboot(&(gnvs->chromeos)); -#if CONFIG_EC_GOOGLE_CHROMEEC +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif diff --git a/src/soc/intel/baytrail/include/soc/pmc.h b/src/soc/intel/baytrail/include/soc/pmc.h index c8d6a67..38136ec 100644 --- a/src/soc/intel/baytrail/include/soc/pmc.h +++ b/src/soc/intel/baytrail/include/soc/pmc.h @@ -281,7 +281,7 @@ void disable_gpe(uint32_t mask); void disable_all_gpe(void); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) void southcluster_log_state(void); #else static inline void southcluster_log_state(void) {} diff --git a/src/soc/intel/baytrail/include/soc/ramstage.h b/src/soc/intel/baytrail/include/soc/ramstage.h index 824df74..083bf77 100644 --- a/src/soc/intel/baytrail/include/soc/ramstage.h +++ b/src/soc/intel/baytrail/include/soc/ramstage.h @@ -25,7 +25,7 @@ void baytrail_init_cpus(device_t dev); void set_max_freq(void); void southcluster_enable_dev(device_t dev); -#if CONFIG_HAVE_REFCODE_BLOB +#if IS_ENABLED(CONFIG_HAVE_REFCODE_BLOB) void baytrail_run_reference_code(void); #else static inline void baytrail_run_reference_code(void) {} diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index 7913c20..a3f1fc7 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -41,7 +41,7 @@ void set_max_freq(void); int early_spi_read_wpsr(u8 *sr); -#if CONFIG_ENABLE_BUILTIN_COM1 +#if IS_ENABLED(CONFIG_ENABLE_BUILTIN_COM1) void byt_config_com1_and_enable(void); #else static inline void byt_config_com1_and_enable(void) { } diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 190231d..f9a5fd1 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -137,7 +137,7 @@ reset_system(); } else { printk(BIOS_DEBUG, "No MRC cache found.\n"); -#if CONFIG_EC_GOOGLE_CHROMEEC +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) if (prev_sleep_state == ACPI_S0) { /* Ensure EC is running RO firmware. */ google_chromeec_check_ec_image(EC_IMAGE_RO); @@ -168,7 +168,7 @@ if (prev_sleep_state != ACPI_S3) { cbmem_initialize_empty(); } else if (cbmem_initialize()) { - #if CONFIG_HAVE_ACPI_RESUME + #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ reset_system(); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index d457151..b6bc64c 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -21,7 +21,7 @@ #include <cbfs.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> -#if CONFIG_EC_GOOGLE_CHROMEEC +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) #include <ec/google/chromeec/ec.h> #endif #include <elog.h> @@ -128,7 +128,7 @@ gfx_init(); -#if CONFIG_EC_GOOGLE_CHROMEEC +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) /* Ensure the EC is in the right mode for recovery */ google_chromeec_early_init(); #endif @@ -221,7 +221,7 @@ printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state); -#if CONFIG_ELOG_BOOT_COUNT +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) if (prev_sleep_state != ACPI_S3) boot_count_increment(); #endif diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index dbd4218..683bf30 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -112,7 +112,7 @@ /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -208,7 +208,7 @@ return NULL; } -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -241,7 +241,7 @@ } finalize_done = 1; -#if CONFIG_SPI_FLASH_SMM +#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif @@ -346,7 +346,7 @@ printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) case ELOG_GSMI_APM_CNT: southbridge_smi_gsmi(); break; @@ -372,7 +372,7 @@ */ if (pm1_sts & PWRBTN_STS) { // power button pressed -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif disable_pm1_control(-1UL); diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index 6061116..9dd2555 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -162,7 +162,7 @@ SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 }; -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) static u8 readb_(const void *addr) { diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 6d20259..a23c8e2 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -169,15 +169,15 @@ /* CPU core count */ gnvs->pcnt = dev_count_cpu(); -#if CONFIG_CONSOLE_CBMEM +#if IS_ENABLED(CONFIG_CONSOLE_CBMEM) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); #endif -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Initialize Verified Boot data */ chromeos_init_vboot(&(gnvs->chromeos)); -#if CONFIG_EC_GOOGLE_CHROMEEC +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/soc/intel/broadwell/include/soc/ramstage.h index db67fe3..1009bba 100644 --- a/src/soc/intel/broadwell/include/soc/ramstage.h +++ b/src/soc/intel/broadwell/include/soc/ramstage.h @@ -23,7 +23,7 @@ void broadwell_init_cpus(device_t dev); void broadwell_pch_enable_dev(device_t dev); -#if CONFIG_HAVE_REFCODE_BLOB +#if IS_ENABLED(CONFIG_HAVE_REFCODE_BLOB) void broadwell_run_reference_code(void); #else static inline void broadwell_run_reference_code(void) { } diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 36e34fe..4430e73 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -221,7 +221,7 @@ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1114, (1 << 15) | (1 << 14)), /* Setup SERIRQ, enable continuous mode */ REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)), -#if !CONFIG_SERIRQ_CONTINUOUS_MODE +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0), #endif REG_SCRIPT_END @@ -431,7 +431,7 @@ static void pch_set_acpi_mode(void) { -#if CONFIG_HAVE_SMI_HANDLER +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) if (!acpi_is_wakeup_s3()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 73b3c2e..ed2f728 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -39,7 +39,7 @@ #include <soc/rcba.h> #include <soc/intel/broadwell/chip.h> -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -57,7 +57,7 @@ /* MMIO base address for MEI interface */ static u8 *mei_base_address; -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -482,7 +482,7 @@ vers_name->hotfix_version, vers_name->build_version); } -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", @@ -702,7 +702,7 @@ path = ME_ERROR_BIOS_PATH; } -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -791,7 +791,7 @@ } printk(BIOS_DEBUG, "\n"); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif @@ -803,7 +803,7 @@ { me_print_fw_version(mbp_data->fw_version_name); -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) me_print_fwcaps(mbp_data->fw_capabilities); #endif @@ -911,7 +911,7 @@ } /* Dump out the MBP contents. */ -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", mbp->header.num_entries, mbp->header.mbp_size); for (i = 0; i < mbp->header.mbp_size - 1; i++) diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 10cb733..34ab39c 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -22,7 +22,7 @@ #include <device/pci_def.h> #include <lib.h> #include <string.h> -#if CONFIG_EC_GOOGLE_CHROMEEC +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> #endif @@ -65,7 +65,7 @@ reset_system(); } else { printk(BIOS_DEBUG, "No MRC cache found.\n"); -#if CONFIG_EC_GOOGLE_CHROMEEC +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) if (pei_data->boot_mode == ACPI_S0) { /* Ensure EC is running RO firmware. */ google_chromeec_check_ec_image(EC_IMAGE_RO); @@ -110,7 +110,7 @@ if (pei_data->boot_mode != ACPI_S3) { cbmem_initialize_empty(); } else if (cbmem_initialize()) { -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ reset_system(); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index af95530..b5e5229 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -91,7 +91,7 @@ params->pei_data->boot_mode = params->power_state->prev_sleep_state; -#if CONFIG_ELOG_BOOT_COUNT +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) if (params->power_state->prev_sleep_state != ACPI_S3) boot_count_increment(); #endif @@ -110,7 +110,7 @@ romstage_handoff_init(params->power_state->prev_sleep_state == ACPI_S3); -#if CONFIG_LPC_TPM +#if IS_ENABLED(CONFIG_LPC_TPM) init_tpm(params->power_state->prev_sleep_state == ACPI_S3); #endif } diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index a73312c..eb70112 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -40,7 +40,7 @@ static int serialio_uart_is_debug(struct device *dev) { -#if CONFIG_INTEL_PCH_UART_CONSOLE +#if IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE) switch (dev->path.pci.devfn) { case PCH_DEVFN_UART0: /* UART0 */ return !!(CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 0); @@ -277,7 +277,7 @@ { pci_dev_set_resources(dev); -#if CONFIG_INTEL_PCH_UART_CONSOLE +#if IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE) /* Update UART base address if used for debug */ if (serialio_uart_is_debug(dev)) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 8a5b443..0b8a970 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -176,7 +176,7 @@ /* USB sleep preparations */ usb_xhci_sleep_prepare(PCH_DEV_XHCI, slp_typ); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -290,7 +290,7 @@ return NULL; } -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -323,7 +323,7 @@ } finalize_done = 1; -#if CONFIG_SPI_FLASH_SMM +#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif @@ -369,7 +369,7 @@ printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) case ELOG_GSMI_APM_CNT: southbridge_smi_gsmi(); break; @@ -388,7 +388,7 @@ */ if (pm1_sts & PWRBTN_STS) { /* power button pressed */ -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif disable_pm1_control(-1UL); diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index a573e32..b27ad23 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -161,7 +161,7 @@ SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 }; -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) static u8 readb_(const void *addr) { diff --git a/src/soc/intel/common/acpi/acpi_debug.asl b/src/soc/intel/common/acpi/acpi_debug.asl index 76805fe..aa7a1af 100644 --- a/src/soc/intel/common/acpi/acpi_debug.asl +++ b/src/soc/intel/common/acpi/acpi_debug.asl @@ -57,7 +57,7 @@ } Store (INDX, LENG) /* Length of the String */ -#if CONFIG_DRIVERS_UART_8250MEM_32 +#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32) OperationRegion (UBAR, SystemMemory, UART_DEBUG_BASE_ADDRESS, 24) Field (UBAR, AnyAcc, NoLock, Preserve) { diff --git a/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl b/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl index 2001f83..ae958c2 100644 --- a/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl +++ b/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl @@ -16,7 +16,7 @@ Name(\_S0, Package(){0x0,0x0,0x0,0x0}) // Name(\_S1, Package(){0x1,0x1,0x0,0x0}) -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) Name(\_S3, Package(){0x5,0x5,0x0,0x0}) #endif Name(\_S4, Package(){0x6,0x6,0x0,0x0}) -- To view, visit https://review.coreboot.org/20348 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3c5f9e0d3d1efdd83442ce724043729c8648ea64 Gerrit-Change-Number: 20348 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: src/northbridge: add IS_ENABLED() around Kconfig symbol refe...
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20347 Change subject: src/northbridge: add IS_ENABLED() around Kconfig symbol references ...................................................................... src/northbridge: add IS_ENABLED() around Kconfig symbol references Change-Id: I1095944e65bfacd9e878840cc88f8a0a24ecde72 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/northbridge/via/cn700/raminit.c M src/northbridge/via/cx700/early_smbus.c M src/northbridge/via/cx700/lpc.c M src/northbridge/via/cx700/raminit.c M src/northbridge/via/cx700/vga.c M src/northbridge/via/vx800/early_smbus.c M src/northbridge/via/vx800/raminit.c M src/northbridge/via/vx800/vga.c M src/northbridge/via/vx900/lpc.c 9 files changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/20347/1 diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c index 20c3c8c..e8a7a17 100644 --- a/src/northbridge/via/cn700/raminit.c +++ b/src/northbridge/via/cn700/raminit.c @@ -24,7 +24,7 @@ #include <delay.h> #include "cn700.h" -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) #define PRINT_DEBUG_MEM(x) printk(BIOS_DEBUG, x) #define PRINT_DEBUG_MEM_HEX8(x) printk(BIOS_DEBUG, "%02x", x) #define PRINT_DEBUG_MEM_HEX16(x) printk(BIOS_DEBUG, "%04x", x) diff --git a/src/northbridge/via/cx700/early_smbus.c b/src/northbridge/via/cx700/early_smbus.c index e106f09..84a0de1 100644 --- a/src/northbridge/via/cx700/early_smbus.c +++ b/src/northbridge/via/cx700/early_smbus.c @@ -43,7 +43,7 @@ #define SMBUS_DELAY() outb(0x80, 0x80) /* Internal functions */ -#if CONFIG_DEBUG_SMBUS +#if IS_ENABLED(CONFIG_DEBUG_SMBUS) static void smbus_print_error(unsigned char host_status_register, int loops) { /* Check if there actually was an error */ @@ -85,7 +85,7 @@ SMBUS_DELAY(); ++loops; } -#if CONFIG_DEBUG_SMBUS +#if IS_ENABLED(CONFIG_DEBUG_SMBUS) /* Some systems seem to have a flakey SMBus. No need to spew a lot of * errors on those, once we know that SMBus access is principally * working. @@ -211,7 +211,7 @@ } /* Debugging Function */ -#if CONFIG_DEBUG_SMBUS +#if IS_ENABLED(CONFIG_DEBUG_SMBUS) static void dump_spd_data(const struct mem_controller *ctrl) { int dimm, offset, regs; diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c index c90dab7..4915066 100644 --- a/src/northbridge/via/cx700/lpc.c +++ b/src/northbridge/via/cx700/lpc.c @@ -266,7 +266,7 @@ { cx700_set_lpc_registers(dev); -#if CONFIG_IOAPIC +#if IS_ENABLED(CONFIG_IOAPIC) #define IO_APIC_ID 2 setup_ioapic(VIO_APIC_VADDR, IO_APIC_ID); #endif diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c index a75be41..682f3be 100644 --- a/src/northbridge/via/cx700/raminit.c +++ b/src/northbridge/via/cx700/raminit.c @@ -20,7 +20,7 @@ #include "registers.h" /* Debugging macros. */ -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) #else #define PRINTK_DEBUG(x...) diff --git a/src/northbridge/via/cx700/vga.c b/src/northbridge/via/cx700/vga.c index 7cb84d2..093477a 100644 --- a/src/northbridge/via/cx700/vga.c +++ b/src/northbridge/via/cx700/vga.c @@ -27,7 +27,7 @@ #include <arch/interrupt.h> #include "registers.h" #include <x86emu/regs.h> -#if CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) #include <device/oprom/realmode/x86.h> #endif @@ -143,7 +143,7 @@ static void vga_enable_console(void) { -#if CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) /* Call VGA BIOS int10 function 0x4f14 to enable main console * Epia-M does not always autosense the main console so forcing * it on is good. diff --git a/src/northbridge/via/vx800/early_smbus.c b/src/northbridge/via/vx800/early_smbus.c index 2c8d5bf..816fe28 100644 --- a/src/northbridge/via/vx800/early_smbus.c +++ b/src/northbridge/via/vx800/early_smbus.c @@ -45,7 +45,7 @@ #define SMBUS_DELAY() outb(0x80, 0x80) -#if CONFIG_DEBUG_SMBUS +#if IS_ENABLED(CONFIG_DEBUG_SMBUS) #define DEBUG(x...) printk(BIOS_DEBUG, x) #else #define DEBUG(x...) while (0) { } @@ -208,7 +208,7 @@ } /* Debugging Function */ -#if CONFIG_DEBUG_SMBUS +#if IS_ENABLED(CONFIG_DEBUG_SMBUS) static void dump_spd_data(void) { int dimm, offset, regs; diff --git a/src/northbridge/via/vx800/raminit.c b/src/northbridge/via/vx800/raminit.c index 69b27c6..f97e2f5 100644 --- a/src/northbridge/via/vx800/raminit.c +++ b/src/northbridge/via/vx800/raminit.c @@ -24,7 +24,7 @@ #pragma clang diagnostic ignored "-Warray-bounds" #endif -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) #define PRINT_DEBUG_MEM(x) printk(BIOS_DEBUG, x) #define PRINT_DEBUG_MEM_HEX8(x) printk(BIOS_DEBUG, "%02x", x) #define PRINT_DEBUG_MEM_HEX16(x) printk(BIOS_DEBUG, "%04x", x) diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c index 70a916f..ce499b7 100644 --- a/src/northbridge/via/vx800/vga.c +++ b/src/northbridge/via/vx800/vga.c @@ -29,7 +29,7 @@ #include <cpu/x86/msr.h> #include <arch/interrupt.h> #include <x86emu/regs.h> -#if CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) #include <device/oprom/realmode/x86.h> #endif @@ -139,7 +139,7 @@ static void vga_enable_console(void) { -#if CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) /* Call VGA BIOS int10 function 0x4f14 to enable main console * Epia-M does not always autosense the main console so forcing * it on is good. diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index a9d24df..b36aaed 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -198,7 +198,7 @@ .device = PCI_DEVICE_ID_VIA_VX900_LPC, }; -#if CONFIG_PIRQ_ROUTE +#if IS_ENABLED(CONFIG_PIRQ_ROUTE) void pirq_assign_irqs(const u8 * pirq) { device_t lpc; -- To view, visit https://review.coreboot.org/20347 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1095944e65bfacd9e878840cc88f8a0a24ecde72 Gerrit-Change-Number: 20347 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: nb/intel: add IS_ENABLED() around Kconfig symbol references
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20346 Change subject: nb/intel: add IS_ENABLED() around Kconfig symbol references ...................................................................... nb/intel: add IS_ENABLED() around Kconfig symbol references Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: Id5bc8b75b1fa372f31982b8636f1efa4975b61a5 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl M src/northbridge/intel/fsp_sandybridge/early_init.c M src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i440bx/debug.c M src/northbridge/intel/i440bx/raminit.c M src/northbridge/intel/i440bx/raminit.h M src/northbridge/intel/i5000/raminit.c M src/northbridge/intel/i82810/debug.c M src/northbridge/intel/i82810/raminit.c M src/northbridge/intel/i82810/raminit.h M src/northbridge/intel/i82830/raminit.c M src/northbridge/intel/i82830/smihandler.c M src/northbridge/intel/i82830/vga.c M src/northbridge/intel/i855/raminit.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/i945/raminit.h M src/northbridge/intel/nehalem/acpi/nehalem.asl M src/northbridge/intel/nehalem/early_init.c M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/acpi/sandybridge.asl M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/raminit_mrc.c 28 files changed, 48 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/20346/1 diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 975a373..b38132a 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -41,7 +41,7 @@ // Unfortunately the code seems to chew up several K of space. //#define VALIDATE_DIMM_COMPATIBILITY -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) #define RAM_DEBUG_MESSAGE(x) printk(BIOS_DEBUG, x) #define RAM_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x) #define RAM_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x) @@ -1003,7 +1003,7 @@ ::: "edi" ); -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) unsigned int a1, a2; asm volatile("movd %%xmm2, %%eax;" : "=a" (a1) ::); asm volatile("movd %%xmm3, %%eax;" : "=a" (a2) ::); diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl index 79586cd..ea0dcf8 100644 --- a/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl @@ -33,7 +33,7 @@ Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH -#if CONFIG_CHROMEOS_RAMOOPS +#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) #endif diff --git a/src/northbridge/intel/fsp_sandybridge/early_init.c b/src/northbridge/intel/fsp_sandybridge/early_init.c index 5071def..1afb6cd 100644 --- a/src/northbridge/intel/fsp_sandybridge/early_init.c +++ b/src/northbridge/intel/fsp_sandybridge/early_init.c @@ -42,7 +42,7 @@ pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); -#if CONFIG_ELOG_BOOT_COUNT +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) /* Increment Boot Counter for non-S3 resume */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) @@ -51,7 +51,7 @@ printk(BIOS_DEBUG, " done.\n"); -#if CONFIG_ELOG_BOOT_COUNT +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) /* Increment Boot Counter except when resuming from S3 */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index 8395a95..726fbe4 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -33,7 +33,7 @@ Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH -#if CONFIG_CHROMEOS_RAMOOPS +#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) #endif diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index fa4dec9..76da5a0 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -30,7 +30,7 @@ #include "chip.h" #include "haswell.h" -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #endif diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 63cbb70..a8c8015 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -368,7 +368,7 @@ mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); -#if CONFIG_CHROMEOS_RAMOOPS +#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) reserved_ram_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c index 064df5b..c69725b 100644 --- a/src/northbridge/intel/i440bx/debug.c +++ b/src/northbridge/intel/i440bx/debug.c @@ -5,7 +5,7 @@ #include <spd.h> #include <console/console.h> -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) void dump_spd_registers(void) { int i; diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index e217c23..86e9595 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -32,7 +32,7 @@ #define NB PCI_DEV(0, 0, 0) /* Debugging macros. */ -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) #define PRINT_DEBUG(x...) printk(BIOS_DEBUG, x) #define DUMPNORTH() dump_pci_device(NB) #else @@ -301,7 +301,7 @@ * 0 = 3 clocks of RAS# precharge * 1 = 2 clocks of RAS# precharge */ -#if CONFIG_SDRAMPWR_4DIMM +#if IS_ENABLED(CONFIG_SDRAMPWR_4DIMM) SDRAMC + 0, 0x00, 0x10, /* The board has 4 DIMM slots. */ #else SDRAMC + 0, 0x00, 0x00, /* The board has 3 DIMM slots. */ diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index a10485a..609b591 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -26,7 +26,7 @@ void sdram_set_spd_registers(void); void sdram_enable(void); /* Debug */ -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) void dump_spd_registers(void); void dump_pci_device(unsigned dev); #else diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c index ffc2dc2..4c71a5a 100644 --- a/src/northbridge/intel/i5000/raminit.c +++ b/src/northbridge/intel/i5000/raminit.c @@ -1752,7 +1752,7 @@ if (setup.branch[1].used) i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_ACTIVE); -#if CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK +#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK) if (ram_check_nodie(0x000000, 0x0a0000) || ram_check_nodie(0x100000, MIN(setup.totalmem * 1048576, 0xd0000000))) { i5000_try_restart("RAM verification failed"); diff --git a/src/northbridge/intel/i82810/debug.c b/src/northbridge/intel/i82810/debug.c index 1b45bc2..d817138 100644 --- a/src/northbridge/intel/i82810/debug.c +++ b/src/northbridge/intel/i82810/debug.c @@ -5,7 +5,7 @@ #include <spd.h> #include <console/console.h> -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) void dump_spd_registers(void) { int i; diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c index cc8c328..6fe4fb5 100644 --- a/src/northbridge/intel/i82810/raminit.c +++ b/src/northbridge/intel/i82810/raminit.c @@ -30,7 +30,7 @@ -----------------------------------------------------------------------------*/ /* Debugging macros. */ -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) #define PRINT_DEBUG(x...) printk(BIOS_DEBUG, x) #define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0)) #else diff --git a/src/northbridge/intel/i82810/raminit.h b/src/northbridge/intel/i82810/raminit.h index 3d263ec..6b9d175 100644 --- a/src/northbridge/intel/i82810/raminit.h +++ b/src/northbridge/intel/i82810/raminit.h @@ -26,7 +26,7 @@ void sdram_enable(void); /* Debug */ -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) void dump_spd_registers(void); void dump_pci_device(unsigned dev); #else diff --git a/src/northbridge/intel/i82830/raminit.c b/src/northbridge/intel/i82830/raminit.c index 7850c87..e0f2c6e 100644 --- a/src/northbridge/intel/i82830/raminit.c +++ b/src/northbridge/intel/i82830/raminit.c @@ -25,7 +25,7 @@ -----------------------------------------------------------------------------*/ /* Debugging macros. */ -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) #define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0)) #else diff --git a/src/northbridge/intel/i82830/smihandler.c b/src/northbridge/intel/i82830/smihandler.c index cb35141..51841e5 100644 --- a/src/northbridge/intel/i82830/smihandler.c +++ b/src/northbridge/intel/i82830/smihandler.c @@ -31,7 +31,7 @@ /* If YABEL is enabled and it's not running at 0x00000000, we have to add some * offset to all our mbi object memory accesses */ -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL && !CONFIG_YABEL_DIRECTHW +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && !CONFIG_YABEL_DIRECTHW #define OBJ_OFFSET CONFIG_YABEL_VIRTMEM_LOCATION #else #define OBJ_OFFSET 0x00000 diff --git a/src/northbridge/intel/i82830/vga.c b/src/northbridge/intel/i82830/vga.c index e673170..20c9d0a 100644 --- a/src/northbridge/intel/i82830/vga.c +++ b/src/northbridge/intel/i82830/vga.c @@ -43,7 +43,7 @@ printk(BIOS_INFO, "Graphics Initialization Complete\n"); /* Enable TV-Out */ -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) #define PIPE_A_CRT (1 << 0) #define PIPE_A_LFP (1 << 1) #define PIPE_A_TV (1 << 3) diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c index 3fd5765..8041951 100644 --- a/src/northbridge/intel/i855/raminit.c +++ b/src/northbridge/intel/i855/raminit.c @@ -29,7 +29,7 @@ #define VALIDATE_DIMM_COMPATIBILITY /* Debugging macros. */ -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) #define DUMPNORTH() dump_pci_device(NORTHBRIDGE_MMC) #else @@ -868,11 +868,11 @@ static void spd_update(u8 reg, u32 new_value) { -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) u32 value1 = pci_read_config32(NORTHBRIDGE_MMC, reg); #endif pci_write_config32(NORTHBRIDGE_MMC, reg, new_value); -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) u32 value2 = pci_read_config32(NORTHBRIDGE_MMC, reg); PRINTK_DEBUG("update reg %02x, old: %08x, new: %08x, read back: %08x\n", reg, value1, new_value, value2); #endif diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 45501d1..1d473d3 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -944,9 +944,9 @@ i945_setup_root_complex_topology(); -#if !CONFIG_HAVE_ACPI_RESUME +#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) sdram_dump_mchbar_registers(); { diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 1f07425..b4c7d13 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -30,7 +30,7 @@ #include <cbmem.h> /* Debugging macros. */ -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) #else #define PRINTK_DEBUG(x...) @@ -93,7 +93,7 @@ read32((void *)offset); } -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) void sdram_dump_mchbar_registers(void) { int i; @@ -1075,7 +1075,7 @@ return nc; } -#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM +#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) /* Strength multiplier tables */ static const u8 dual_channel_strength_multiplier[] = { 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, @@ -1130,7 +1130,7 @@ 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, 0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11 }; -#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC +#elif IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) static const u8 dual_channel_strength_multiplier[] = { 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, @@ -2255,7 +2255,7 @@ /** * We add the indices according to our clocks from CLKCFG. */ -#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM +#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) static const u32 data_clock_crossing[] = { 0x00100401, 0x00000000, /* DDR400 FSB400 */ 0xffffffff, 0xffffffff, /* nonexistent */ @@ -2300,7 +2300,7 @@ 0xffffffff, 0xffffffff, /* nonexistent */ }; -#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC +#elif IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) /* i945 G/P */ static const u32 data_clock_crossing[] = { 0xffffffff, 0xffffffff, /* nonexistent */ @@ -2520,7 +2520,7 @@ if (sysinfo->interleaved) { reg32 = MCHBAR32(DCC); -#if CONFIG_CHANNEL_XOR_RANDOMIZATION +#if IS_ENABLED(CONFIG_CHANNEL_XOR_RANDOMIZATION) reg32 &= ~(1 << 10); reg32 |= (1 << 9); #else @@ -2897,9 +2897,9 @@ { u8 clocks[2] = { 0, 0 }; -#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM +#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) #define CLOCKS_WIDTH 2 -#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC +#elif IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) #define CLOCKS_WIDTH 3 #endif if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) @@ -2914,7 +2914,7 @@ if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH; -#if CONFIG_OVERRIDE_CLOCK_DISABLE +#if IS_ENABLED(CONFIG_OVERRIDE_CLOCK_DISABLE) /* Usually system firmware turns off system memory clock signals * to unused SO-DIMM slots to reduce EMI and power consumption. * However, the Kontron 986LCD-M does not like unused clock diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 0554900..bc4491f 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -68,7 +68,7 @@ int fixup_i945_errata(void); void udelay(u32 us); -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) void sdram_dump_mchbar_registers(void); #endif #endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/nehalem/acpi/nehalem.asl b/src/northbridge/intel/nehalem/acpi/nehalem.asl index aa97a77..20165f3 100644 --- a/src/northbridge/intel/nehalem/acpi/nehalem.asl +++ b/src/northbridge/intel/nehalem/acpi/nehalem.asl @@ -33,7 +33,7 @@ Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH -#if CONFIG_CHROMEOS_RAMOOPS +#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) #endif diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index b2f4089..3f55140 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -72,7 +72,7 @@ pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(5), 0x33); pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(6), 0x33); -#if CONFIG_ELOG_BOOT_COUNT +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) /* Increment Boot Counter for non-S3 resume */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) @@ -81,7 +81,7 @@ printk(BIOS_DEBUG, " done.\n"); -#if CONFIG_ELOG_BOOT_COUNT +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) /* Increment Boot Counter except when resuming from S3 */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 83c6506..b09460c 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -80,7 +80,7 @@ reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); -#if CONFIG_CHROMEOS_RAMOOPS +#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) reserved_ram_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index c811d38..8bf685d 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -28,7 +28,7 @@ #include <string.h> /* Debugging macros. */ -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) #else #define PRINTK_DEBUG(x...) @@ -134,7 +134,7 @@ d->tRCD = d->spd_data[29]; d->tWR = d->spd_data[36]; d->ranks = d->sides; // XXX -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) const char *ubso[2] = { "UB", "SO" }; #endif PRINTK_DEBUG("%s-DIMM %d\n", &ubso[d->type][0], i); @@ -318,7 +318,7 @@ } } -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) static u32 fsb_reg_to_mhz(u32 speed) { return (speed * 133) + 667; diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 61537e8..609106f 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -33,7 +33,7 @@ Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH -#if CONFIG_CHROMEOS_RAMOOPS +#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) #endif diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index efe27b1..3580f35 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -60,7 +60,7 @@ pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); -#if CONFIG_ELOG_BOOT_COUNT +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) /* Increment Boot Counter for non-S3 resume */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) @@ -69,7 +69,7 @@ printk(BIOS_DEBUG, " done.\n"); -#if CONFIG_ELOG_BOOT_COUNT +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) /* Increment Boot Counter except when resuming from S3 */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 5c5f41a..51fa4fe 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -100,7 +100,7 @@ reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); -#if CONFIG_CHROMEOS_RAMOOPS +#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) reserved_ram_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 09d82d6..3f7d1c6 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -39,7 +39,7 @@ * MRC scrambler seed offsets should be reserved in * mainboard cmos.layout and not covered by checksum. */ -#if CONFIG_USE_OPTION_TABLE +#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) #include "option_table.h" #define CMOS_OFFSET_MRC_SEED (CMOS_VSTART_mrc_scrambler_seed >> 3) #define CMOS_OFFSET_MRC_SEED_S3 (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3) @@ -236,7 +236,7 @@ die("UEFI PEI System Agent not found.\n"); } -#if CONFIG_USBDEBUG_IN_ROMSTAGE +#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) /* mrc.bin reconfigures USB, so reinit it to have debug */ usbdebug_init(); #endif -- To view, visit https://review.coreboot.org/20346 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id5bc8b75b1fa372f31982b8636f1efa4975b61a5 Gerrit-Change-Number: 20346 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: nb/amd: add IS_ENABLED() around Kconfig symbol references
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20345 Change subject: nb/amd: add IS_ENABLED() around Kconfig symbol references ...................................................................... nb/amd: add IS_ENABLED() around Kconfig symbol references Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: I763cbbc31dcd4cdd128c04793a742ab6daaf5f0c Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/northbridge/amd/agesa/family10/northbridge.c M src/northbridge/amd/agesa/family12/northbridge.c M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family15/northbridge.c M src/northbridge/amd/agesa/family15rl/northbridge.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/amdfam10/debug.c M src/northbridge/amd/amdfam10/debug.h M src/northbridge/amd/amdfam10/early_ht.c M src/northbridge/amd/amdfam10/northbridge.c M src/northbridge/amd/amdht/h3finit.c M src/northbridge/amd/amdk8/Makefile.inc M src/northbridge/amd/amdk8/amdk8.h M src/northbridge/amd/amdk8/coherent_ht.c M src/northbridge/amd/amdk8/debug.c M src/northbridge/amd/amdk8/incoherent_ht.c M src/northbridge/amd/amdk8/misc_control.c M src/northbridge/amd/amdk8/northbridge.c M src/northbridge/amd/amdk8/raminit.c M src/northbridge/amd/amdk8/raminit.h M src/northbridge/amd/amdk8/raminit_f.c M src/northbridge/amd/amdk8/raminit_f_dqs.c M src/northbridge/amd/amdmct/wrappers/mcti_d.c M src/northbridge/amd/cimx/rd890/NbPlatform.h M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00670F00/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c 29 files changed, 147 insertions(+), 147 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/20345/1 diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 6f7a053..242a812 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -27,7 +27,7 @@ #include <cpu/x86/lapic.h> #include <cbmem.h> -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #include <pc80/mc146818rtc.h> #endif @@ -496,7 +496,7 @@ * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_MULTIPLE_VGA_ADAPTERS +#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) extern device_t vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); @@ -800,7 +800,7 @@ ramtop = limitk * 1024; } -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); #else @@ -942,7 +942,7 @@ } disable_siblings = !CONFIG_LOGICAL_CPUS; -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) get_option(&disable_siblings, "multi_core"); #endif @@ -1117,7 +1117,7 @@ the global uma_memory variables already in its enable function. */ if (!done) { setup_bsp_ramtop(); -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) #error Northbridge does not set uma_memory_base or uma_memory_size. setup_uma_memory(); #endif diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index c931bf0..00e7e5b 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -362,7 +362,7 @@ } -#if CONFIG_CONSOLE_VGA_MULTI +#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI) extern device_t vga_pri; // the primary vga device, defined in device.c #endif @@ -376,7 +376,7 @@ * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_CONSOLE_VGA_MULTI +#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -600,7 +600,7 @@ printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); /* Must be called after PCI enumeration and resource allocation */ -#if CONFIG_AMD_SB_CIMX +#if IS_ENABLED(CONFIG_AMD_SB_CIMX) sb_After_Pci_Init(); sb_Mid_Post_Init(); #endif diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index e570096..d5bf730 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -353,7 +353,7 @@ report_resource_stored(dev, resource, buf); } -#if CONFIG_CONSOLE_VGA_MULTI +#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI) extern device_t vga_pri; // the primary vga device, defined in device.c #endif @@ -367,7 +367,7 @@ * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_CONSOLE_VGA_MULTI +#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary, @@ -581,7 +581,7 @@ static void domain_enable_resources(device_t dev) { -#if CONFIG_AMD_SB_CIMX +#if IS_ENABLED(CONFIG_AMD_SB_CIMX) if (!acpi_is_wakeup_s3()) { sb_After_Pci_Init(); sb_Mid_Post_Init(); diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 5cb0f91..ff06f2c 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -391,7 +391,7 @@ * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_MULTIPLE_VGA_ADAPTERS +#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) extern device_t vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); @@ -640,7 +640,7 @@ /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__); -#if CONFIG_AMD_SB_CIMX +#if IS_ENABLED(CONFIG_AMD_SB_CIMX) sb_After_Pci_Init(); #endif /* Enable MMIO on AMD CPU Address Map Controller */ @@ -1021,7 +1021,7 @@ lapicid_start = (lapicid_start + 1) * core_max; printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); } -#if CONFIG_CPU_AMD_SOCKET_G34 +#if IS_ENABLED(CONFIG_CPU_AMD_SOCKET_G34) u32 apic_id = (i / 2 * core_max) + j + lapicid_start + (i % 2 ? siblings + 1 : 0); #else u32 apic_id = (i * core_max) + j + lapicid_start; diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index aa24a6a..1d53301 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -390,7 +390,7 @@ * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_MULTIPLE_VGA_ADAPTERS +#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) extern struct device *vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 95787fc..93d3880 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -389,7 +389,7 @@ * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_MULTIPLE_VGA_ADAPTERS +#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) extern device_t vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index f91448a..f56dcb9 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -389,7 +389,7 @@ * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_MULTIPLE_VGA_ADAPTERS +#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) extern device_t vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index ed2b539..067c299 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -21,7 +21,7 @@ void print_debug_addr(const char *str, void *val) { -#if CONFIG_DEBUG_CAR +#if IS_ENABLED(CONFIG_DEBUG_CAR) printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val); #endif } @@ -205,7 +205,7 @@ } } -#if CONFIG_DEBUG_SMBUS +#if IS_ENABLED(CONFIG_DEBUG_SMBUS) void dump_spd_registers(const struct mem_controller *ctrl) { int i; @@ -315,14 +315,14 @@ #if IS_ENABLED(CONFIG_DIMM_DDR2) void print_tx(const char *strval, u32 val) { -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) printk(BIOS_DEBUG, "%s%08x\n", strval, val); #endif } void print_t(const char *strval) { -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) printk(BIOS_DEBUG, "%s", strval); #endif } @@ -330,7 +330,7 @@ void print_tf(const char *func, const char *strval) { -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) printk(BIOS_DEBUG, "%s: %s", func, strval); #endif } diff --git a/src/northbridge/amd/amdfam10/debug.h b/src/northbridge/amd/amdfam10/debug.h index df1f3a0..a4ecfe9 100644 --- a/src/northbridge/amd/amdfam10/debug.h +++ b/src/northbridge/amd/amdfam10/debug.h @@ -32,7 +32,7 @@ void dump_pci_devices(void); void dump_pci_devices_on_bus(u32 busn); -#if CONFIG_DEBUG_SMBUS +#if IS_ENABLED(CONFIG_DEBUG_SMBUS) void dump_spd_registers(const struct mem_controller *ctrl); void dump_smbus_registers(void); #endif diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index c3b02d7..c68b0c4 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -22,7 +22,7 @@ // mmconf is not ready yet void set_bsp_node_CHtExtNodeCfgEn(void) { -#if CONFIG_EXT_RT_TBL_SUPPORT +#if IS_ENABLED(CONFIG_EXT_RT_TBL_SUPPORT) u32 dword; dword = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x68); dword |= (1<<27) | (1<<25); diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index a306d25..7d02e9a 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -36,7 +36,7 @@ #include <cpu/amd/msr.h> #include <cpu/amd/family_10h-family_15h/ram_calc.h> -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #include <cpu/amd/multicore.h> #include <pc80/mc146818rtc.h> #endif @@ -50,7 +50,7 @@ #include <cpu/amd/model_10xxx_rev.h> #endif -#if CONFIG_AMD_SB_CIMX +#if IS_ENABLED(CONFIG_AMD_SB_CIMX) #include <sb_cimx.h> #endif @@ -320,7 +320,7 @@ { struct bus *link; -#if CONFIG_CPU_AMD_SOCKET_G34_NON_AGESA +#if IS_ENABLED(CONFIG_CPU_AMD_SOCKET_G34_NON_AGESA) if (is_fam15h()) { uint8_t current_link_number = 0; @@ -585,7 +585,7 @@ * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_MULTIPLE_VGA_ADAPTERS +#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) extern device_t vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); @@ -890,7 +890,7 @@ static void setup_uma_memory(void) { -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) uint32_t topmem = (uint32_t) bsp_topmem(); uma_memory_size = get_uma_memory_size(topmem); uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ @@ -989,7 +989,7 @@ i, mmio_basek, basek, limitk); } -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); #endif @@ -1330,7 +1330,7 @@ #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .acpi_name = amdfam10_domain_acpi_name, #endif -#if CONFIG_GENERATE_SMBIOS_TABLES +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) .get_smbios_data = amdfam10_get_smbios_data, #endif }; @@ -1359,7 +1359,7 @@ sysconf.bsp_apicid = lapicid(); sysconf.apicid_offset = sysconf.bsp_apicid; -#if CONFIG_ENABLE_APIC_EXT_ID +#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) if (pci_read_config32(dev, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST)) { sysconf.enabled_apic_ext_id = 1; @@ -1454,7 +1454,7 @@ } disable_siblings = !CONFIG_LOGICAL_CPUS; -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) get_option(&disable_siblings, "multi_core"); #endif @@ -1659,7 +1659,7 @@ } } -#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET > 0) +#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0) if (sysconf.enabled_apic_ext_id) { if (apic_id != 0 || sysconf.lift_bsp_apicid) { apic_id += sysconf.apicid_offset; @@ -1955,7 +1955,7 @@ detect_and_enable_probe_filter(dev); detect_and_enable_cache_partitioning(dev); initialize_cpus(dev->link_list); -#if CONFIG_AMD_SB_CIMX +#if IS_ENABLED(CONFIG_AMD_SB_CIMX) sb_After_Pci_Init(); sb_Mid_Post_Init(); #endif diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 6a9d898..fc0c2d2 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -1492,13 +1492,13 @@ cbPCBFreqLimit = ht_speed_mhz_to_hw(pDat->HtBlock->ht_link_configuration->ht_speed_limit); cbPCBFreqLimit = min(cbPCBFreqLimit, cbPCBFreqLimit_NVRAM); -#if CONFIG_LIMIT_HT_DOWN_WIDTH_8 +#if IS_ENABLED(CONFIG_LIMIT_HT_DOWN_WIDTH_8) cbPCBABDownstreamWidth = 8; #else cbPCBABDownstreamWidth = 16; #endif -#if CONFIG_LIMIT_HT_UP_WIDTH_8 +#if IS_ENABLED(CONFIG_LIMIT_HT_UP_WIDTH_8) cbPCBBAUpstreamWidth = 8; #else cbPCBBAUpstreamWidth = 16; diff --git a/src/northbridge/amd/amdk8/Makefile.inc b/src/northbridge/amd/amdk8/Makefile.inc index c6b1ac6..263e06f 100644 --- a/src/northbridge/amd/amdk8/Makefile.inc +++ b/src/northbridge/amd/amdk8/Makefile.inc @@ -20,7 +20,7 @@ # Not sure what to do with these yet. How did raminit_test even work? # Should be a target in -y form. -#if CONFIG_K8_REV_F_SUPPORT +#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) # #makerule raminit_test # depends "$(TOP)/src/northbridge/amd/amdk8/raminit_test.c" diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index e335a98..65b6fb6 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -2,7 +2,7 @@ #define AMDK8_H -#if CONFIG_K8_REV_F_SUPPORT +#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 @@ -26,7 +26,7 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr); int optimize_link_coherent_ht(void); unsigned int get_nodes(void); -#if CONFIG_RAMINIT_SYSINFO +#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO) void setup_coherent_ht_domain(void); #else int setup_coherent_ht_domain(void); diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 10ca6ee..b0865fb 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -73,7 +73,7 @@ #include <stdint.h> #include <arch/io.h> #include <pc80/mc146818rtc.h> -#if CONFIG_HAVE_OPTION_TABLE +#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE) #include "option_table.h" #endif @@ -258,8 +258,8 @@ freq_cap = pci_read_config16(dev, pos); freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */ -#if CONFIG_K8_HT_FREQ_1G_SUPPORT - #if !CONFIG_K8_REV_F_SUPPORT +#if IS_ENABLED(CONFIG_K8_HT_FREQ_1G_SUPPORT) + #if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) if (!is_cpu_pre_e0()) #endif { @@ -633,7 +633,7 @@ static void setup_uniprocessor(void) { printk(BIOS_SPEW, "Enabling UP settings\n"); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3; if (tmp > 0) return; #endif @@ -1516,7 +1516,7 @@ } #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */ -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) static unsigned verify_dualcore(unsigned nodes) { unsigned node, totalcpus, tmp; @@ -1535,10 +1535,10 @@ static void coherent_ht_finalize(unsigned nodes) { unsigned node; -#if !CONFIG_K8_REV_F_SUPPORT +#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) int rev_a0; #endif -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) unsigned total_cpus; if (read_option(multi_core, 0) == 0) { /* multi_core */ @@ -1556,7 +1556,7 @@ */ printk(BIOS_SPEW, "coherent_ht_finalize\n"); -#if !CONFIG_K8_REV_F_SUPPORT +#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) rev_a0 = is_cpu_rev_a0(); #endif for (node = 0; node < nodes; node++) { @@ -1567,7 +1567,7 @@ /* Set the Total CPU and Node count in the system */ val = pci_read_config32(dev, 0x60); val &= (~0x000F0070); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) val |= ((total_cpus-1)<<16)|((nodes-1)<<4); #else val |= ((nodes-1)<<16)|((nodes-1)<<4); @@ -1587,7 +1587,7 @@ (3 << HTTC_HI_PRI_BYP_CNT_SHIFT); pci_write_config32(dev, HT_TRANSACTION_CONTROL, val); -#if !CONFIG_K8_REV_F_SUPPORT +#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) if (rev_a0) { pci_write_config32(dev, 0x94, 0); pci_write_config32(dev, 0xb4, 0); @@ -1607,7 +1607,7 @@ pci_devfn_t dev; uint32_t cmd; dev = NODE_MC(node); -#if !CONFIG_K8_REV_F_SUPPORT +#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) if (is_cpu_pre_c0()) { /* Errata 66 @@ -1652,7 +1652,7 @@ #endif -#if !CONFIG_K8_REV_F_SUPPORT +#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) /* I can't touch this msr on early buggy cpus, and cannot apply either 169 or 131 */ if (!is_cpu_pre_b3()) #endif @@ -1770,7 +1770,7 @@ return needs_reset; } -#if CONFIG_RAMINIT_SYSINFO +#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO) void setup_coherent_ht_domain(void) #else int setup_coherent_ht_domain(void) @@ -1792,7 +1792,7 @@ } coherent_ht_finalize(nodes); -#if !CONFIG_RAMINIT_SYSINFO +#if !IS_ENABLED(CONFIG_RAMINIT_SYSINFO) return optimize_link_coherent_ht(); #endif } diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c index e1eade4..fd24bd5 100644 --- a/src/northbridge/amd/amdk8/debug.c +++ b/src/northbridge/amd/amdk8/debug.c @@ -11,7 +11,7 @@ void print_debug_addr(const char *str, void *val) { -#if CONFIG_DEBUG_CAR +#if IS_ENABLED(CONFIG_DEBUG_CAR) printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val); #endif } @@ -63,7 +63,7 @@ printk(BIOS_DEBUG, "\n"); } -#if CONFIG_K8_REV_F_SUPPORT +#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) { int i; @@ -135,7 +135,7 @@ } } -#if CONFIG_DEBUG_SMBUS +#if IS_ENABLED(CONFIG_DEBUG_SMBUS) void dump_spd_registers(const struct mem_controller *ctrl) { diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index d65af96..c1b6802 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -131,8 +131,8 @@ /* AMD K8 Unsupported 1GHz? */ if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) { - #if CONFIG_K8_HT_FREQ_1G_SUPPORT - #if !CONFIG_K8_REV_F_SUPPORT + #if IS_ENABLED(CONFIG_K8_HT_FREQ_1G_SUPPORT) + #if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) if (is_cpu_pre_e0()) { // only E0 later support 1GHz freq_cap &= ~(1 << HT_FREQ_1000Mhz); } @@ -144,7 +144,7 @@ printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\n", pos, freq_cap); -#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890 +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890) freq_cap &= 0x3f; printk(BIOS_INFO, "Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed.\n"); #endif @@ -283,7 +283,7 @@ return needs_reset; } -#if CONFIG_RAMINIT_SYSINFO +#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO) static void ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid, struct sys_info *sysinfo) #else @@ -296,7 +296,7 @@ uint8_t next_unitid, last_unitid; unsigned uoffs; -#if !CONFIG_RAMINIT_SYSINFO +#if !IS_ENABLED(CONFIG_RAMINIT_SYSINFO) int reset_needed = 0; #endif @@ -403,7 +403,7 @@ flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS); offs = ((flags>>10) & 1) ? PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS; - #if CONFIG_RAMINIT_SYSINFO + #if IS_ENABLED(CONFIG_RAMINIT_SYSINFO) /* store the link pair here and we will Setup the Hypertransport link later, after we get final FID/VID */ { struct link_pair_st *link_pair = &sysinfo->link_pair[sysinfo->link_pair_num]; @@ -439,7 +439,7 @@ flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f; pci_write_config16(PCI_DEV(bus, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags); - #if CONFIG_RAMINIT_SYSINFO + #if IS_ENABLED(CONFIG_RAMINIT_SYSINFO) // Here need to change the dev in the array int i; for (i = 0; i < sysinfo->link_pair_num; i++) @@ -458,7 +458,7 @@ } #endif -#if !CONFIG_RAMINIT_SYSINFO +#if !IS_ENABLED(CONFIG_RAMINIT_SYSINFO) return reset_needed; #endif @@ -527,7 +527,7 @@ return reset_needed; } -#if CONFIG_SOUTHBRIDGE_NVIDIA_CK804 // || CONFIG_SOUTHBRIDGE_NVIDIA_MCP55 +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_NVIDIA_CK804) static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val) { uint32_t dword; @@ -587,7 +587,7 @@ } #endif -#if CONFIG_RAMINIT_SYSINFO +#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO) static void ht_setup_chains(uint8_t ht_c_num, struct sys_info *sysinfo) #else static int ht_setup_chains(uint8_t ht_c_num) @@ -602,7 +602,7 @@ pci_devfn_t udev; uint8_t i; -#if !CONFIG_RAMINIT_SYSINFO +#if !IS_ENABLED(CONFIG_RAMINIT_SYSINFO) int reset_needed = 0; #else sysinfo->link_pair_num = 0; @@ -634,7 +634,7 @@ upos = ((reg & 0xf00)>>8) * 0x20 + 0x80; udev = PCI_DEV(0, devpos, 0); -#if CONFIG_RAMINIT_SYSINFO +#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO) ht_setup_chainx(udev,upos,busn, offset_unit_id(i == 0), sysinfo); // all not #else reset_needed |= ht_setup_chainx(udev,upos,busn, offset_unit_id(i == 0)); //all not @@ -642,7 +642,7 @@ } -#if !CONFIG_RAMINIT_SYSINFO +#if !IS_ENABLED(CONFIG_RAMINIT_SYSINFO) reset_needed |= optimize_link_read_pointers_chain(ht_c_num); return reset_needed; @@ -650,7 +650,7 @@ } -#if CONFIG_RAMINIT_SYSINFO +#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO) static void ht_setup_chains_x(struct sys_info *sysinfo) #else static int ht_setup_chains_x(void) @@ -662,7 +662,7 @@ uint8_t next_busn; uint8_t ht_c_num; uint8_t nodes; -#if CONFIG_K8_ALLOCATE_IO_RANGE +#if IS_ENABLED(CONFIG_K8_ALLOCATE_IO_RANGE) unsigned next_io_base; #endif @@ -672,7 +672,7 @@ reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64); /* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn = 0x3f+1 */ print_linkn_in("SBLink=", ((reg>>8) & 3)); -#if CONFIG_RAMINIT_SYSINFO +#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO) sysinfo->sblk = (reg>>8) & 3; sysinfo->sbbusn = 0; sysinfo->nodes = nodes; @@ -682,7 +682,7 @@ next_busn = 0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/ -#if CONFIG_K8_ALLOCATE_IO_RANGE +#if IS_ENABLED(CONFIG_K8_ALLOCATE_IO_RANGE) /* io range allocation */ tempreg = 0 | (((reg>>8) & 0x3) << 4)| (0x3<<12); //limit pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4, tempreg); @@ -695,7 +695,7 @@ for (ht_c_num = 1;ht_c_num < 4; ht_c_num++) { pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0); -#if CONFIG_K8_ALLOCATE_IO_RANGE +#if IS_ENABLED(CONFIG_K8_ALLOCATE_IO_RANGE) /* io range allocation */ pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc4 + ht_c_num * 8, 0); pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc0 + ht_c_num * 8, 0); @@ -728,7 +728,7 @@ pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg); next_busn+=0x3f+1; -#if CONFIG_K8_ALLOCATE_IO_RANGE +#if IS_ENABLED(CONFIG_K8_ALLOCATE_IO_RANGE) /* io range allocation */ tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg); @@ -752,7 +752,7 @@ pci_write_config32(dev, regpos, reg); } -#if CONFIG_K8_ALLOCATE_IO_RANGE +#if IS_ENABLED(CONFIG_K8_ALLOCATE_IO_RANGE) /* io range allocation */ for (i = 0; i < 4; i++) { unsigned regpos; @@ -778,7 +778,7 @@ } } -#if CONFIG_RAMINIT_SYSINFO +#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO) sysinfo->ht_c_num = i; ht_setup_chains(i, sysinfo); sysinfo->sbdn = get_sbdn(sysinfo->sbbusn); @@ -788,7 +788,7 @@ } -#if CONFIG_RAMINIT_SYSINFO +#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO) static int optimize_link_incoherent_ht(struct sys_info *sysinfo) { // We need to use recorded link pair info to optimize the link diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c index 3cbeb04..c472edf 100644 --- a/src/northbridge/amd/amdk8/misc_control.c +++ b/src/northbridge/amd/amdk8/misc_control.c @@ -121,7 +121,7 @@ cmd = pci_read_config32(dev, 0x44); cmd |= (1<<6) | (1<<25); pci_write_config32(dev, 0x44, cmd); -#if !CONFIG_K8_REV_F_SUPPORT +#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) if (is_cpu_pre_c0()) { /* Errata 58 diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index c957af0..b001a0f 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -25,7 +25,7 @@ #include <cpu/amd/mtrr.h> #include <cpu/amd/multicore.h> -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #include <pc80/mc146818rtc.h> #endif @@ -484,7 +484,7 @@ * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_MULTIPLE_VGA_ADAPTERS +#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) extern device_t vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); @@ -811,10 +811,10 @@ static void setup_uma_memory(void) { -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) uint32_t topmem = (uint32_t) bsp_topmem(); -#if !CONFIG_BOARD_ASROCK_939A785GMH && !CONFIG_BOARD_AMD_MAHOGANY +#if !IS_ENABLED(CONFIG_BOARD_ASROCK_939A785GMH) && !CONFIG_BOARD_AMD_MAHOGANY switch (topmem) { case 0x10000000: /* 256M system memory */ @@ -885,7 +885,7 @@ * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole. * otherwise We reset the hole to the mmio_basek */ - #if !CONFIG_K8_REV_F_SUPPORT + #if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) if (!is_cpu_pre_e0()) { #endif @@ -903,7 +903,7 @@ disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id); } - #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC + #if IS_ENABLED(CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC) //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some u32 basek_pri; for (i = 0; i < fx_devs; i++) { @@ -924,7 +924,7 @@ #endif } -#if !CONFIG_K8_REV_F_SUPPORT +#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) } // is_cpu_pre_e0 #endif @@ -953,7 +953,7 @@ } -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) printk(BIOS_DEBUG, "node %d : uma_memory_base/1024=0x%08llx, mmio_basek=0x%08lx, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); if ((uma_memory_base >> 10) < mmio_basek) printk(BIOS_ALERT, "node %d: UMA memory starts below mmio_basek\n", i); @@ -973,7 +973,7 @@ } #if CONFIG_HW_MEM_HOLE_SIZEK != 0 if (reset_memhole) - #if !CONFIG_K8_REV_F_SUPPORT + #if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) if (!is_cpu_pre_e0()) #endif sizek += hoist_memory(mmio_basek,i); @@ -998,7 +998,7 @@ ramtop = limitk * 1024; } -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) set_late_cbmem_top(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); #else @@ -1128,7 +1128,7 @@ sysconf.apicid_offset = bsp_apicid; disable_siblings = !CONFIG_LOGICAL_CPUS; -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) get_option(&disable_siblings, "multi_core"); #endif @@ -1201,7 +1201,7 @@ // That is the typical case if (j == 0) { - #if !CONFIG_K8_REV_F_SUPPORT + #if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) e0_later_single_core = is_e0_later_in_bsp(i); // single core #else e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 @@ -1250,7 +1250,7 @@ static void cpu_bus_init(device_t dev) { -#if CONFIG_WAIT_BEFORE_CPUS_INIT +#if IS_ENABLED(CONFIG_WAIT_BEFORE_CPUS_INIT) cpus_ready_for_init(); #endif initialize_cpus(dev->link_list); diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 43229ea..dae1584 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -15,7 +15,7 @@ #include <reset.h> #include "raminit.h" #include "amdk8.h" -#if CONFIG_HAVE_OPTION_TABLE +#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE) #include "option_table.h" #endif @@ -43,7 +43,7 @@ return pci_read_config32(ctrl->f0, 0) == 0x11001022; } -#if CONFIG_RAMINIT_SYSINFO +#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO) void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) #else void sdram_set_registers(const struct mem_controller *ctrl) @@ -592,7 +592,7 @@ unsigned long side2; unsigned long rows; unsigned long col; -#if CONFIG_QRANK_DIMM_SUPPORT +#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT) unsigned long rank; #endif }; @@ -606,7 +606,7 @@ sz.side2 = 0; sz.rows = 0; sz.col = 0; -#if CONFIG_QRANK_DIMM_SUPPORT +#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT) sz.rank = 0; #endif @@ -650,7 +650,7 @@ if ((value != 2) && (value != 4)) { goto val_err; } -#if CONFIG_QRANK_DIMM_SUPPORT +#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT) sz.rank = value; #endif @@ -679,7 +679,7 @@ sz.side2 = 0; sz.rows = 0; sz.col = 0; -#if CONFIG_QRANK_DIMM_SUPPORT +#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT) sz.rank = 0; #endif out: @@ -727,7 +727,7 @@ /* Set the appropriate DIMM base address register */ pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1); -#if CONFIG_QRANK_DIMM_SUPPORT +#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT) if (sz.rank == 4) { pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1); @@ -738,7 +738,7 @@ if (base0) { dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); dch |= DCH_MEMCLK_EN0 << index; -#if CONFIG_QRANK_DIMM_SUPPORT +#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT) if (sz.rank == 4) { dch |= DCH_MEMCLK_EN0 << (index + 2); } @@ -760,7 +760,7 @@ map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); map &= ~(0xf << (index * 4)); -#if CONFIG_QRANK_DIMM_SUPPORT +#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT) if (sz.rank == 4) { map &= ~(0xf << ((index + 2) * 4)); } @@ -771,7 +771,7 @@ if (sz.side1 >= (25 +3)) { if (is_cpu_pre_d0()) { map |= (sz.side1 - (25 + 3)) << (index *4); -#if CONFIG_QRANK_DIMM_SUPPORT +#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT) if (sz.rank == 4) { map |= (sz.side1 - (25 + 3)) << ((index + 2) * 4); } @@ -779,7 +779,7 @@ } else { map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << (index*4); -#if CONFIG_QRANK_DIMM_SUPPORT +#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT) if (sz.rank == 4) { map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ((index + 2) * 4); } @@ -1164,7 +1164,7 @@ if (unbuffered) { if ((has_dualch) && (!is_cpu_pre_d0())) { dcl |= DCL_UnBuffDimm; -#if CONFIG_CPU_AMD_SOCKET_939 +#if IS_ENABLED(CONFIG_CPU_AMD_SOCKET_939) if ((cpuid_eax(1) & 0x30) == 0x30) { /* CS[7:4] is copy of CS[3:0], should be set for 939 socket */ dcl |= DCL_UpperCSMap; @@ -1375,7 +1375,7 @@ static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_mask, int *freq_1t) { -#if CONFIG_CPU_AMD_SOCKET_939 +#if IS_ENABLED(CONFIG_CPU_AMD_SOCKET_939) /* + 1 raise so we detect 0 as bad field */ #define DDR200 (NBCAP_MEMCLK_100MHZ + 1) @@ -1488,7 +1488,7 @@ return NBCAP_MEMCLK_200MHZ; } -#elif CONFIG_CPU_AMD_SOCKET_754 +#elif IS_ENABLED(CONFIG_CPU_AMD_SOCKET_754) #define CFGIDX(DIMM1,DIMM2,DIMM3) ((DIMM3)*9+(DIMM2)*3+(DIMM1)) @@ -1657,7 +1657,7 @@ if (freq == sizeof(cl_at_freq)) goto hw_error; -#if CONFIG_CPU_AMD_SOCKET_754 +#if IS_ENABLED(CONFIG_CPU_AMD_SOCKET_754) if (freq < max_freq_1t || CONFIG_K8_FORCE_2T_DRAM_TIMING) { pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW) | DCL_En2T); @@ -1899,7 +1899,7 @@ { uint32_t dcl; int value; -#if CONFIG_QRANK_DIMM_SUPPORT +#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT) int rank; #endif int dimm; @@ -1908,7 +1908,7 @@ return -1; } -#if CONFIG_QRANK_DIMM_SUPPORT +#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT) rank = spd_read_byte(ctrl->channel0[i], 5); /* number of physical banks */ if (rank < 0) { return -1; @@ -1916,7 +1916,7 @@ #endif dimm = 1<<(DCL_x4DIMM_SHIFT+i); -#if CONFIG_QRANK_DIMM_SUPPORT +#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT) if (rank == 4) { dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2); } @@ -2168,7 +2168,7 @@ return dimm_mask; } -#if CONFIG_RAMINIT_SYSINFO +#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO) void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) #else void sdram_set_spd_registers(const struct mem_controller *ctrl) @@ -2277,7 +2277,7 @@ hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK; printk(BIOS_SPEW, "Handling memory hole at 0x%08x (default)\n", hole_startk); -#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +#if IS_ENABLED(CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC) /* We need to double check if hole_startk is valid. * If it is equal to the dram base address in K (base_k), * we need to decrease it. @@ -2327,7 +2327,7 @@ #endif -#if CONFIG_RAMINIT_SYSINFO +#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO) void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo) #else void sdram_enable(int controllers, const struct mem_controller *ctrl) diff --git a/src/northbridge/amd/amdk8/raminit.h b/src/northbridge/amd/amdk8/raminit.h index 0f4636b..4db0862 100644 --- a/src/northbridge/amd/amdk8/raminit.h +++ b/src/northbridge/amd/amdk8/raminit.h @@ -26,7 +26,7 @@ #define TIMEOUT_LOOPS 300000 -#if defined(__PRE_RAM__) && CONFIG_RAMINIT_SYSINFO +#if defined(__PRE_RAM__) && IS_ENABLED(CONFIG_RAMINIT_SYSINFO) void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo); void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo); diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index a979896..39c5ad8 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -33,11 +33,11 @@ #include "raminit.h" #include "f.h" #include <spd_ddr2.h> -#if CONFIG_HAVE_OPTION_TABLE +#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE) #include "option_table.h" #endif -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) #define printk_raminit(args...) printk(BIOS_DEBUG, args) #else #define printk_raminit(args...) @@ -845,7 +845,7 @@ /* Set the appropriate DIMM base address register */ pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), base0); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), base1); -#if CONFIG_QRANK_DIMM_SUPPORT +#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT) if (sz->rank == 4) { pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), base0); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), base1); @@ -873,7 +873,7 @@ } else { dword = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); //Channel A dword &= ~(ClkDis0 >> index); -#if CONFIG_QRANK_DIMM_SUPPORT +#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT) if (sz->rank == 4) { dword &= ~(ClkDis0 >> (index+2)); } @@ -883,7 +883,7 @@ if (meminfo->is_Width128) { // ChannelA+B dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC); dword &= ~(ClkDis0 >> index); -#if CONFIG_QRANK_DIMM_SUPPORT +#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT) if (sz->rank == 4) { dword &= ~(ClkDis0 >> (index+2)); } @@ -936,7 +936,7 @@ } map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); map &= ~(0xf << (index * 4)); -#if CONFIG_QRANK_DIMM_SUPPORT +#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT) if (sz->rank == 4) { map &= ~(0xf << ((index + 2) * 4)); } @@ -947,7 +947,7 @@ unsigned temp_map; temp_map = cs_map_aaa[(sz->bank-2)*3*4 + (sz->rows - 13)*3 + (sz->col - 9) ]; map |= temp_map << (index*4); -#if CONFIG_QRANK_DIMM_SUPPORT +#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT) if (sz->rank == 4) { map |= temp_map << ((index + 2) * 4); } @@ -1291,7 +1291,7 @@ } else { pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), 0); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), 0); -#if CONFIG_QRANK_DIMM_SUPPORT +#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT) if (meminfo->sz[index].rank == 4) { pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0); @@ -2173,7 +2173,7 @@ static void set_4RankRDimm(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) { -#if CONFIG_QRANK_DIMM_SUPPORT +#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT) int value; int i; long dimm_mask = meminfo->dimm_mask; @@ -2213,7 +2213,7 @@ uint32_t mask_single_rank; uint32_t mask_page_1k; int value; -#if CONFIG_QRANK_DIMM_SUPPORT +#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT) int rank; #endif @@ -2246,20 +2246,20 @@ value = spd_read_byte(spd_device, SPD_PRI_WIDTH); - #if CONFIG_QRANK_DIMM_SUPPORT + #if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT) rank = meminfo->sz[i].rank; #endif if (value == 4) { mask_x4 |= (1<<i); - #if CONFIG_QRANK_DIMM_SUPPORT + #if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT) if (rank == 4) { mask_x4 |= 1<<(i+2); } #endif } else if (value == 16) { mask_x16 |= (1<<i); - #if CONFIG_QRANK_DIMM_SUPPORT + #if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT) if (rank == 4) { mask_x16 |= 1<<(i+2); } @@ -2348,7 +2348,7 @@ dcl &= ~DCL_DimmEccEn; } #else // CMOS_VSTART_ECC_memory not defined -#if !CONFIG_ECC_MEMORY +#if !IS_ENABLED(CONFIG_ECC_MEMORY) dcl &= ~DCL_DimmEccEn; #endif #endif @@ -2932,7 +2932,7 @@ hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK; printk_raminit("Handling memory hole at 0x%08x (default)\n", hole_startk); -#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +#if IS_ENABLED(CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC) /* We need to double check if the hole_startk is valid, if it is equal to basek, we need to decrease it some */ uint32_t basek_pri; diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index c470b25..64b0c64 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -1782,7 +1782,7 @@ #endif } -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) #if CONFIG_MEM_TRAIN_SEQ == 0 static int save_index_to_pos(unsigned int dev, int size, int index, int nvram_pos) @@ -1937,7 +1937,7 @@ if (train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out; printk(BIOS_DEBUG, " done\n"); sysinfo->mem_trained[i]=1; -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) dqs_save_MC_NVRAM((ctrl+i)->f2); #endif } diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 0b08c20..306f3a7 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -128,16 +128,16 @@ //val = 2; /* S4 (Unbuffered SO-DIMMS) */ break; case NV_BYPMAX: -#if !CONFIG_GFXUMA +#if !IS_ENABLED(CONFIG_GFXUMA) val = 4; -#elif CONFIG_GFXUMA +#elif IS_ENABLED(CONFIG_GFXUMA) val = 7; #endif break; case NV_RDWRQBYP: -#if !CONFIG_GFXUMA +#if !IS_ENABLED(CONFIG_GFXUMA) val = 2; -#elif CONFIG_GFXUMA +#elif IS_ENABLED(CONFIG_GFXUMA) val = 3; #endif break; @@ -191,9 +191,9 @@ val = !!nvram; break; case NV_BurstLen32: -#if !CONFIG_GFXUMA +#if !IS_ENABLED(CONFIG_GFXUMA) val = 0; /* 64 byte mode */ -#elif CONFIG_GFXUMA +#elif IS_ENABLED(CONFIG_GFXUMA) val = 1; /* 32 byte mode */ #endif break; @@ -212,9 +212,9 @@ case NV_BottomIO: case NV_BottomUMA: /* address bits [31:24] */ -#if !CONFIG_GFXUMA +#if !IS_ENABLED(CONFIG_GFXUMA) val = (CONFIG_MMCONF_BASE_ADDRESS >> 24); -#elif CONFIG_GFXUMA +#elif IS_ENABLED(CONFIG_GFXUMA) #if (CONFIG_MMCONF_BASE_ADDRESS < (MAXIMUM_GFXUMA_SIZE + MINIMUM_DRAM_BELOW_4G)) #error "MMCONF_BASE_ADDRESS is too small" #endif diff --git a/src/northbridge/amd/cimx/rd890/NbPlatform.h b/src/northbridge/amd/cimx/rd890/NbPlatform.h index 9e75cb6..3efa84d 100644 --- a/src/northbridge/amd/cimx/rd890/NbPlatform.h +++ b/src/northbridge/amd/cimx/rd890/NbPlatform.h @@ -26,7 +26,7 @@ #ifdef CIMX_TRACE_SUPPORT #define CIMX_INIT_TRACE(Arguments) - #if CONFIG_REDIRECT_NBCIMX_TRACE_TO_SERIAL + #if IS_ENABLED(CONFIG_REDIRECT_NBCIMX_TRACE_TO_SERIAL) #define TRACE_DATA(Ptr, Level) BIOS_DEBUG //always enable #define CIMX_TRACE(Argument) do {do_printk Argument;} while (0) #else diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 5ba0e44..42df652 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -46,7 +46,7 @@ #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) -#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1 +#if (defined CONFIG_EXT_CONF_SUPPORT) && IS_ENABLED(CONFIG_EXT_CONF_SUPPORT) #error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore! #endif diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index f085d5c..f964c04 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -45,7 +45,7 @@ #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) -#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1 +#if (defined CONFIG_EXT_CONF_SUPPORT) && IS_ENABLED(CONFIG_EXT_CONF_SUPPORT) #error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore! #endif @@ -381,7 +381,7 @@ * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_MULTIPLE_VGA_ADAPTERS +#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) extern device_t vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c index 006bc48..02c4d72 100644 --- a/src/northbridge/amd/pi/00670F00/northbridge.c +++ b/src/northbridge/amd/pi/00670F00/northbridge.c @@ -45,7 +45,7 @@ #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) -#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1 +#if (defined CONFIG_EXT_CONF_SUPPORT) && IS_ENABLED(CONFIG_EXT_CONF_SUPPORT) #error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore! #endif @@ -381,7 +381,7 @@ * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_MULTIPLE_VGA_ADAPTERS +#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) extern device_t vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 960078e..de2059d 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -391,7 +391,7 @@ * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_MULTIPLE_VGA_ADAPTERS +#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) extern device_t vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); -- To view, visit https://review.coreboot.org/20345 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I763cbbc31dcd4cdd128c04793a742ab6daaf5f0c Gerrit-Change-Number: 20345 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2017