coreboot-gerrit June 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: src/lib: add IS_ENABLED() around Kconfig symbol references
by build bot (Jenkins) (Code Review) 25 Jun '17

25 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20341 ) Change subject: src/lib: add IS_ENABLED() around Kconfig symbol references ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56154/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/11757/ : SUCCESS -- To view, visit https://review.coreboot.org/20341 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idcea3f8b1a4246cb6b29999a84a191a3133e5c78 Gerrit-Change-Number: 20341 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 25 Jun 2017 19:29:16 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: cpu/amd: add IS_ENABLED() around Kconfig symbol references
by build bot (Jenkins) (Code Review) 25 Jun '17

25 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20335 ) Change subject: cpu/amd: add IS_ENABLED() around Kconfig symbol references ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56147/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/11750/ : SUCCESS -- To view, visit https://review.coreboot.org/20335 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9f4155285529ec28e826637a61436478f648704c Gerrit-Change-Number: 20335 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 25 Jun 2017 19:24:29 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: drivers/spi: add IS_ENABLED() around Kconfig symbol references
by build bot (Jenkins) (Code Review) 25 Jun '17

25 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20339 ) Change subject: drivers/spi: add IS_ENABLED() around Kconfig symbol references ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56152/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/11755/ : SUCCESS -- To view, visit https://review.coreboot.org/20339 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If80e0c4e1c9911b44853561b03aef1c741255229 Gerrit-Change-Number: 20339 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 25 Jun 2017 19:24:16 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: src/device: add IS_ENABLED() around Kconfig symbol references
by build bot (Jenkins) (Code Review) 25 Jun '17

25 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20338 ) Change subject: src/device: add IS_ENABLED() around Kconfig symbol references ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56151/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/11754/ : SUCCESS -- To view, visit https://review.coreboot.org/20338 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I66cde1adcf373889b03f144793c0b4f46d21ca31 Gerrit-Change-Number: 20338 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 25 Jun 2017 19:18:33 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: arch/*: Update Kconfig symbol usage
by build bot (Jenkins) (Code Review) 25 Jun '17

25 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20005 ) Change subject: arch/*: Update Kconfig symbol usage ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56149/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/11751/ : SUCCESS -- To view, visit https://review.coreboot.org/20005 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5a84414d2d1631e35ac91efb67a0d4c1f673bf85 Gerrit-Change-Number: 20005 Gerrit-PatchSet: 5 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 25 Jun 2017 19:16:20 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: cpu/intel: add IS_ENABLED() around Kconfig symbol references
by build bot (Jenkins) (Code Review) 25 Jun '17

25 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20336 ) Change subject: cpu/intel: add IS_ENABLED() around Kconfig symbol references ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56148/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/11752/ : SUCCESS -- To view, visit https://review.coreboot.org/20336 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie685bbbb1cbf06d32631ea40ad120b6f45374b2e Gerrit-Change-Number: 20336 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 25 Jun 2017 19:12:26 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: src: add IS_ENABLED() around Kconfig symbol references
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20358 Change subject: src: add IS_ENABLED() around Kconfig symbol references ...................................................................... src: add IS_ENABLED() around Kconfig symbol references These are places that were missed on the first pass. Change-Id: Ia6511f0325433ab020946078923bf7ad6f0362a3 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/arch/x86/pci_ops_conf1.c M src/arch/x86/smbios.c M src/console/vtxprintf.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/20358/1 diff --git a/src/arch/x86/pci_ops_conf1.c b/src/arch/x86/pci_ops_conf1.c index 820744c..a92fd31 100644 --- a/src/arch/x86/pci_ops_conf1.c +++ b/src/arch/x86/pci_ops_conf1.c @@ -20,7 +20,7 @@ * Functions for accessing PCI configuration space with type 1 accesses */ -#if !CONFIG_PCI_IO_CFG_EXT +#if !IS_ENABLED(CONFIG_PCI_IO_CFG_EXT) #define CONFIG_CMD(bus, devfn, where) (0x80000000 | (bus << 16) | \ (devfn << 8) | (where & ~3)) #else diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 9721802..e2ee545 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -278,7 +278,7 @@ t->length = len - 2; t->vendor = smbios_add_string(t->eos, "coreboot"); -#if !CONFIG_CHROMEOS +#if !IS_ENABLED(CONFIG_CHROMEOS) t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date); t->bios_version = smbios_add_string(t->eos, diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 5f37253..acf2f80 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -21,7 +21,7 @@ #define call_tx(x) tx_byte(x, data) -#if !CONFIG_ARCH_MIPS +#if !IS_ENABLED(CONFIG_ARCH_MIPS) #define SUPPORT_64BIT_INTS #endif -- To view, visit https://review.coreboot.org/20358 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia6511f0325433ab020946078923bf7ad6f0362a3 Gerrit-Change-Number: 20358 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: src/vendorcode: add IS_ENABLED() around Kconfig symbol refer...
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20357 Change subject: src/vendorcode: add IS_ENABLED() around Kconfig symbol references ...................................................................... src/vendorcode: add IS_ENABLED() around Kconfig symbol references Change-Id: I891cb4f799aaafcf4a0dd91b5533d2f8db7f3d61 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/vendorcode/amd/agesa/f10/Include/Ids.h M src/vendorcode/google/chromeos/chromeos.h M src/vendorcode/google/chromeos/ramoops.c 3 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/20357/1 diff --git a/src/vendorcode/amd/agesa/f10/Include/Ids.h b/src/vendorcode/amd/agesa/f10/Include/Ids.h index 2607b3d..df3ddc0 100644 --- a/src/vendorcode/amd/agesa/f10/Include/Ids.h +++ b/src/vendorcode/amd/agesa/f10/Include/Ids.h @@ -400,7 +400,7 @@ #define IDS_HDT_CONSOLE_INIT(x) #define IDS_HDT_CONSOLE_EXIT(x) #ifdef __GNUC__ - #if CONFIG_REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL + #if IS_ENABLED(CONFIG_REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL) #define IDS_HDT_CONSOLE(s, args...) do_printk(BIOS_DEBUG, s, ##args) ///#define IDS_HDT_CONSOLE(f, s, args...) printk(((MEM_FLOW) - (f) + (BIOS_DEBUG)), s, ##args) #else diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index e535751..a739ab7 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -24,7 +24,7 @@ #include <vboot/misc.h> #include <vboot/vboot_common.h> -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* functions implemented in watchdog.c */ void mark_watchdog_tombstone(void); void reboot_from_watchdog(void); @@ -38,9 +38,9 @@ #include "gnvs.h" struct device; -#if CONFIG_CHROMEOS_RAMOOPS +#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) void chromeos_ram_oops_init(chromeos_acpi_t *chromeos); -#if CONFIG_CHROMEOS_RAMOOPS_DYNAMIC +#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS_DYNAMIC) static inline void chromeos_reserve_ram_oops(struct device *dev, int idx) {} #else /* CONFIG_CHROMEOS_RAMOOPS_DYNAMIC */ void chromeos_reserve_ram_oops(struct device *dev, int idx); diff --git a/src/vendorcode/google/chromeos/ramoops.c b/src/vendorcode/google/chromeos/ramoops.c index 313025d..c72af00 100644 --- a/src/vendorcode/google/chromeos/ramoops.c +++ b/src/vendorcode/google/chromeos/ramoops.c @@ -50,7 +50,7 @@ set_ramoops(chromeos, ram_oops, size); } -#if CONFIG_CHROMEOS_RAMOOPS_DYNAMIC +#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS_DYNAMIC) static inline void set_global_chromeos_pointer(chromeos_acpi_t *chromeos) {} #else /* !CONFIG_CHROMEOS_RAMOOPS_DYNAMIC */ -- To view, visit https://review.coreboot.org/20357 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I891cb4f799aaafcf4a0dd91b5533d2f8db7f3d61 Gerrit-Change-Number: 20357 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: src/cpu: add IS_ENABLED() around Kconfig symbol references
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20356 Change subject: src/cpu: add IS_ENABLED() around Kconfig symbol references ...................................................................... src/cpu: add IS_ENABLED() around Kconfig symbol references Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: I4e5e585c3f98a129d89ef38b26d828d3bfeac7cf Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/cpu/dmp/vortex86ex/biosdata_ex.S M src/cpu/x86/lapic/apic_timer.c M src/cpu/x86/lapic/boot_cpu.c M src/cpu/x86/lapic/lapic_cpu_init.c M src/cpu/x86/lapic/secondary.S M src/cpu/x86/mtrr/mtrr.c M src/cpu/x86/smm/smihandler.c M src/cpu/x86/smm/smm_module_handler.c M src/cpu/x86/smm/smmrelocate.S M src/cpu/x86/tsc/delay_tsc.c 10 files changed, 40 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/20356/1 diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.S b/src/cpu/dmp/vortex86ex/biosdata_ex.S index 59d7ff1..6686bb7 100644 --- a/src/cpu/dmp/vortex86ex/biosdata_ex.S +++ b/src/cpu/dmp/vortex86ex/biosdata_ex.S @@ -38,7 +38,7 @@ 500/375/33 B4 53 0F 02 AF 09 */ -#if CONFIG_PLL_200_200_33 +#if IS_ENABLED(CONFIG_PLL_200_200_33) // 200/200/33 30 03 0F 02 8F 07 byte_fffb6 = 0x30 byte_fffb7 = 0x03 @@ -46,7 +46,7 @@ byte_fffbc = 0x02 byte_fffbe = 0xff byte_fffbf = 0x07 -#elif CONFIG_PLL_300_300_33 +#elif IS_ENABLED(CONFIG_PLL_300_300_33) // 300/300/33 48 03 0F 02 1F 07 byte_fffb6 = 0x48 byte_fffb7 = 0x03 @@ -54,7 +54,7 @@ byte_fffbc = 0x02 byte_fffbe = 0xff byte_fffbf = 0x07 -#elif CONFIG_PLL_300_300_100 +#elif IS_ENABLED(CONFIG_PLL_300_300_100) // 300/300/100 48 03 23 02 7F 07 byte_fffb6 = 0x48 byte_fffb7 = 0x03 @@ -62,7 +62,7 @@ byte_fffbc = 0x02 byte_fffbe = 0xff byte_fffbf = 0x07 -#elif CONFIG_PLL_400_200_33 +#elif IS_ENABLED(CONFIG_PLL_400_200_33) // 400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing byte_fffb6 = 0x60 byte_fffb7 = 0x43 @@ -70,7 +70,7 @@ byte_fffbc = 0x02 byte_fffbe = 0xff byte_fffbf = 0x07 -#elif CONFIG_PLL_400_200_100 +#elif IS_ENABLED(CONFIG_PLL_400_200_100) // 400/200/100 60 43 23 02 4F 07 byte_fffb6 = 0x60 byte_fffb7 = 0x43 @@ -78,7 +78,7 @@ byte_fffbc = 0x02 byte_fffbe = 0xff byte_fffbf = 0x07 -#elif CONFIG_PLL_400_400_33 +#elif IS_ENABLED(CONFIG_PLL_400_400_33) // 400/400/33 60 03 0F 02 BF 09 byte_fffb6 = 0x60 byte_fffb7 = 0x03 @@ -86,7 +86,7 @@ byte_fffbc = 0x02 byte_fffbe = 0xff byte_fffbf = 0x09 -#elif CONFIG_PLL_500_250_33 +#elif IS_ENABLED(CONFIG_PLL_500_250_33) // 500/250/33 50 42 0F 02 DF 07 byte_fffb6 = 0x50 byte_fffb7 = 0x42 @@ -94,7 +94,7 @@ byte_fffbc = 0x02 byte_fffbe = 0xff byte_fffbf = 0x07 -#elif CONFIG_PLL_500_500_33 +#elif IS_ENABLED(CONFIG_PLL_500_500_33) // 500/500/33 78 03 0F 02 4F 09 byte_fffb6 = 0x78 byte_fffb7 = 0x03 @@ -102,7 +102,7 @@ byte_fffbc = 0x02 byte_fffbe = 0xff byte_fffbf = 0x09 -#elif CONFIG_PLL_400_300_33 +#elif IS_ENABLED(CONFIG_PLL_400_300_33) // 400/300/33 90 53 0F 02 3F 07 byte_fffb6 = 0x90 byte_fffb7 = 0x53 @@ -110,7 +110,7 @@ byte_fffbc = 0x02 byte_fffbe = 0xff byte_fffbf = 0x07 -#elif CONFIG_PLL_400_300_100 +#elif IS_ENABLED(CONFIG_PLL_400_300_100) // 400/300/100 90 53 23 02 9F 07 byte_fffb6 = 0x90 byte_fffb7 = 0x53 @@ -118,7 +118,7 @@ byte_fffbc = 0x02 byte_fffbe = 0xff byte_fffbf = 0x07 -#elif CONFIG_PLL_444_333_33 +#elif IS_ENABLED(CONFIG_PLL_444_333_33) // 444/333/33 A0 53 0F 02 5F 08 byte_fffb6 = 0xa0 byte_fffb7 = 0x53 @@ -126,7 +126,7 @@ byte_fffbc = 0x02 byte_fffbe = 0xff byte_fffbf = 0x08 -#elif CONFIG_PLL_466_350_33 +#elif IS_ENABLED(CONFIG_PLL_466_350_33) // 466/350/33 A8 53 0F 02 DF 09 byte_fffb6 = 0xa8 byte_fffb7 = 0x53 @@ -134,7 +134,7 @@ byte_fffbc = 0x02 byte_fffbe = 0xff byte_fffbf = 0x09 -#elif CONFIG_PLL_500_375_33 +#elif IS_ENABLED(CONFIG_PLL_500_375_33) // 500/375/33 B4 53 0F 02 AF 09 byte_fffb6 = 0xb4 byte_fffb7 = 0x53 diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index cddc5ad..254bb07 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -29,7 +29,7 @@ * memory init. */ -#if CONFIG_UDELAY_LAPIC_FIXED_FSB +#if CONFIG_UDELAY_LAPIC_FIXED_FSB != 0 static inline u32 get_timer_fsb(void) { return CONFIG_UDELAY_LAPIC_FIXED_FSB; @@ -136,7 +136,7 @@ } while ((start - value) < ticks); } -#if CONFIG_LAPIC_MONOTONIC_TIMER && !defined(__PRE_RAM__) +#if IS_ENABLED(CONFIG_LAPIC_MONOTONIC_TIMER) && !defined(__PRE_RAM__) #include <timer.h> static struct monotonic_counter { diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c index 2942ff6..7ba21fe 100644 --- a/src/cpu/x86/lapic/boot_cpu.c +++ b/src/cpu/x86/lapic/boot_cpu.c @@ -14,7 +14,7 @@ #include <smp/node.h> #include <cpu/x86/msr.h> -#if CONFIG_SMP +#if IS_ENABLED(CONFIG_SMP) int boot_cpu(void) { int bsp; diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 427e537..83be53b 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -36,7 +36,7 @@ #include <cpu/intel/speedstep.h> #include <thread.h> -#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 +#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1 /* This is a lot more paranoid now, since Linux can NOT handle * being told there is a CPU when none exists. So any errors * will return 0, meaning no CPU. @@ -148,8 +148,9 @@ } return 0; } -#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_INTEL_MODEL_206AX \ - && !CONFIG_CPU_INTEL_MODEL_2065X +#if !IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX) \ + && !IS_ENABLED(CONFIG_CPU_INTEL_MODEL_206AX) \ + && !IS_ENABLED(CONFIG_CPU_INTEL_MODEL_2065X) mdelay(10); #endif @@ -324,7 +325,7 @@ return result; } -#if CONFIG_AP_IN_SIPI_WAIT +#if IS_ENABLED(CONFIG_AP_IN_SIPI_WAIT) /** * Sending INIT IPI to self is equivalent of asserting #INIT with a bit of @@ -556,17 +557,17 @@ /* Find the device structure for the boot CPU */ info->cpu = alloc_find_dev(cpu_bus, &cpu_path); -#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 +#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1 // why here? In case some day we can start core1 in amd_sibling_init copy_secondary_start_to_lowest_1M(); #endif -#if CONFIG_HAVE_SMI_HANDLER +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) if (!IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION)) smm_init(); #endif -#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 +#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1 /* start all aps at first, so we can init ECC all together */ if (IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)) start_other_cpus(cpu_bus, info->cpu); @@ -575,7 +576,7 @@ /* Initialize the bootstrap processor */ cpu_initialize(0); -#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 +#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1 if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)) start_other_cpus(cpu_bus, info->cpu); @@ -588,13 +589,13 @@ * smm_init() will queue a pending SMI on all cpus * and smm_other_cpus() will start them one by one */ smm_init(); -#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 +#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1 last_cpu_index = 0; smm_other_cpus(cpu_bus, info->cpu); #endif } -#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 +#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1 recover_lowest_1M(); #endif } diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index 0c4c0d0..a36502b 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -14,7 +14,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/lapic_def.h> -#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 +#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1 .text .globl _secondary_start, _secondary_start_end, _secondary_gdt_addr .balign 4096 diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 609d1e7..ef1bb31 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -36,7 +36,7 @@ #include <arch/cpu.h> #include <arch/acpi.h> #include <memrange.h> -#if CONFIG_X86_AMD_FIXED_MTRRS +#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS) #include <cpu/amd/mtrr.h> #define MTRR_FIXED_WRBACK_BITS (MTRR_READ_MEM | MTRR_WRITE_MEM) #else diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 16415ba..089456e 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -19,7 +19,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -#if CONFIG_SPI_FLASH_SMM +#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) #include <spi-generic.h> #endif @@ -185,7 +185,7 @@ /* Allow drivers to initialize variables in SMM context. */ if (do_driver_init) { -#if CONFIG_SPI_FLASH_SMM +#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) spi_init(); #endif do_driver_init = 0; diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 4bcd853..95f63a3 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -18,7 +18,7 @@ #include <cpu/x86/smm.h> #include <rmodule.h> -#if CONFIG_SPI_FLASH_SMM +#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) #include <spi-generic.h> #endif @@ -158,7 +158,7 @@ /* Allow drivers to initialize variables in SMM context. */ if (do_driver_init) { -#if CONFIG_SPI_FLASH_SMM +#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) spi_init(); #endif do_driver_init = 0; diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 2fe0156..2a950f3 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -21,19 +21,19 @@ // can it be cleaned up so this include is not required? // It's needed right now because we get our DEFAULT_PMBASE from // here. -#if CONFIG_SOUTHBRIDGE_INTEL_I82801GX +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) #include "../../../southbridge/intel/i82801gx/i82801gx.h" -#elif CONFIG_SOUTHBRIDGE_INTEL_I82801DX +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801DX) #include "../../../southbridge/intel/i82801dx/i82801dx.h" -#elif CONFIG_SOC_INTEL_SCH +#elif IS_ENABLED(CONFIG_SOC_INTEL_SCH) #include "../../../soc/intel/sch/sch.h" -#elif CONFIG_SOUTHBRIDGE_INTEL_I82801IX +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801IX) #include "../../../southbridge/intel/i82801ix/i82801ix.h" #else #error "Southbridge needs SMM handler support." #endif -#if CONFIG_SMM_TSEG +#if IS_ENABLED(CONFIG_SMM_TSEG) #error "Don't use this file with TSEG." #endif /* CONFIG_SMM_TSEG */ @@ -155,7 +155,7 @@ /* End of southbridge specific section. */ -#if CONFIG_DEBUG_SMM_RELOCATION +#if IS_ENABLED(CONFIG_DEBUG_SMM_RELOCATION) /* print [SMM-x] so we can determine if CPUx went to SMM */ movw $CONFIG_TTYS0_BASE, %dx mov $'[', %al diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index b2e20f4..ec2f1d7 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -136,7 +136,7 @@ } } -#if CONFIG_TSC_MONOTONIC_TIMER +#if IS_ENABLED(CONFIG_TSC_MONOTONIC_TIMER) #include <timer.h> static struct monotonic_counter { -- To view, visit https://review.coreboot.org/20356 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4e5e585c3f98a129d89ef38b26d828d3bfeac7cf Gerrit-Change-Number: 20356 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: src/soc: add IS_ENABLED() around Kconfig symbol references
by Martin Roth (Code Review) 25 Jun '17

25 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20355 Change subject: src/soc: add IS_ENABLED() around Kconfig symbol references ...................................................................... src/soc: add IS_ENABLED() around Kconfig symbol references Change-Id: I2e7b756296e861e08cea846297f687a880daaf45 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/soc/broadcom/cygnus/ddr_init.c M src/soc/dmp/vortex86ex/ide_sd_sata.c M src/soc/dmp/vortex86ex/raminit.c M src/soc/dmp/vortex86ex/southbridge.c M src/soc/mediatek/mt8173/i2c.c M src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8173/mt6391.c M src/soc/nvidia/tegra210/include/soc/mtc.h M src/soc/nvidia/tegra210/romstage.c 9 files changed, 53 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/20355/1 diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c index 5c4c985..1a5fd86 100644 --- a/src/soc/broadcom/cygnus/ddr_init.c +++ b/src/soc/broadcom/cygnus/ddr_init.c @@ -475,7 +475,7 @@ { int ddr32 = 0; -#if (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) +#if IS_ENABLED(CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) ddr32=1; #endif /* (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) */ @@ -966,7 +966,7 @@ reg = (uint32_t *)(*flptr++); val = (uint32_t *)(*flptr++); if ( (((uint32_t)reg >= DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + 0x114))) -#if (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT || defined(CONFIG_NS_PLUS)) +#if IS_ENABLED(CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) || defined(CONFIG_NS_PLUS) || (((uint32_t)reg >= DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN + 0x114))) #endif #ifdef CONFIG_IPROC_DDR_ECC @@ -1068,7 +1068,7 @@ *ptr++ = val; chksum += val; } -#if (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT || defined(CONFIG_NS_PLUS)) +#if IS_ENABLED(CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) || defined(CONFIG_NS_PLUS) if (is_ddr_32bit()) { for (i=0; i<sizeof(ddr_phy_wl_regs) / sizeof(ddr_phy_wl_regs[0]); i++) { reg = (uint32_t)DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN + ddr_phy_wl_regs[i]; @@ -1479,7 +1479,7 @@ } } -#if CONFIG_CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE +#if IS_ENABLED(CONFIG_CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE) #if (DDR_AUTO_SELF_REFRESH_IDLE_COUNT > 0) & (DDR_AUTO_SELF_REFRESH_IDLE_COUNT <= 0xff) /* Enable auto self-refresh */ reg32_set_bits((unsigned int *)DDR_DENALI_CTL_57, diff --git a/src/soc/dmp/vortex86ex/ide_sd_sata.c b/src/soc/dmp/vortex86ex/ide_sd_sata.c index 936505e..c60018a 100644 --- a/src/soc/dmp/vortex86ex/ide_sd_sata.c +++ b/src/soc/dmp/vortex86ex/ide_sd_sata.c @@ -80,20 +80,20 @@ u16 ata_timing_pri, ata_timing_sec; u32 ata_timing_reg32; /* Primary channel is SD. */ -#if CONFIG_IDE1_ENABLE +#if IS_ENABLED(CONFIG_IDE1_ENABLE) ata_timing_pri = 0x8000; #else ata_timing_pri = 0x0000; // Disable this channel. #endif /* Secondary channel is SATA. */ -#if CONFIG_IDE2_ENABLE +#if IS_ENABLED(CONFIG_IDE2_ENABLE) ata_timing_sec = 0xa30f; // This setting value works well. #else ata_timing_sec = 0x0000; // Disable this channel. #endif ata_timing_reg32 = (ata_timing_sec << 16) | ata_timing_pri; pci_write_config32(dev, 0x40, ata_timing_reg32); -#if CONFIG_IDE_NATIVE_MODE +#if IS_ENABLED(CONFIG_IDE_NATIVE_MODE) /* Set both IDE channels to native mode. */ u8 prog_if; prog_if = pci_read_config8(dev, 0x09); @@ -110,7 +110,7 @@ static void setup_std_ide_compatible(struct device *dev) { -#if CONFIG_IDE_STANDARD_COMPATIBLE +#if IS_ENABLED(CONFIG_IDE_STANDARD_COMPATIBLE) // Misc Control Register (MCR) Offset 90h // bit 0 = Vendor ID Access, bit 1 = Device ID Access. u8 mcr; diff --git a/src/soc/dmp/vortex86ex/raminit.c b/src/soc/dmp/vortex86ex/raminit.c index 1ccdb27..0d4b5b5 100644 --- a/src/soc/dmp/vortex86ex/raminit.c +++ b/src/soc/dmp/vortex86ex/raminit.c @@ -253,7 +253,7 @@ static void print_ddr3_memory_setup(void) { -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) printk(BIOS_DEBUG, "DDR3 Timing Reg 0-3:\n"); printk(BIOS_DEBUG, "NB 6e : "); print_debug_hex16(pci_read_config16(NB, 0x6e)); diff --git a/src/soc/dmp/vortex86ex/southbridge.c b/src/soc/dmp/vortex86ex/southbridge.c index 05702d1..451aea6 100644 --- a/src/soc/dmp/vortex86ex/southbridge.c +++ b/src/soc/dmp/vortex86ex/southbridge.c @@ -207,7 +207,7 @@ ext_int_routing |= irq_to_int_routing[CAN_IRQ] << CAN_IRQ_SHIFT; ext_int_routing |= irq_to_int_routing[HDA_IRQ] << HDA_IRQ_SHIFT; ext_int_routing |= irq_to_int_routing[USBD_IRQ] << USBD_IRQ_SHIFT; -#if CONFIG_IDE_NATIVE_MODE +#if IS_ENABLED(CONFIG_IDE_NATIVE_MODE) /* IDE in native mode, only uses one IRQ. */ ext_int_routing |= irq_to_int_routing[0] << SIDE_IRQ_SHIFT; ext_int_routing |= irq_to_int_routing[PIDE_IRQ] << PIDE_IRQ_SHIFT; @@ -250,21 +250,21 @@ { u32 lpt_reg = 0; -#if CONFIG_LPT_ENABLE +#if IS_ENABLED(CONFIG_LPT_ENABLE) int ppmod = 0; -#if CONFIG_LPT_MODE_BPP +#if IS_ENABLED(CONFIG_LPT_MODE_BPP) ppmod = 0; -#elif CONFIG_LPT_MODE_EPP_19_AND_SPP +#elif IS_ENABLED(CONFIG_LPT_MODE_EPP_19_AND_SPP) ppmod = 1; -#elif CONFIG_LPT_MODE_ECP +#elif IS_ENABLED(CONFIG_LPT_MODE_ECP) ppmod = 2; -#elif CONFIG_LPT_MODE_ECP_AND_EPP_19 +#elif IS_ENABLED(CONFIG_LPT_MODE_ECP_AND_EPP_19) ppmod = 3; -#elif CONFIG_LPT_MODE_SPP +#elif IS_ENABLED(CONFIG_LPT_MODE_SPP) ppmod = 4; -#elif CONFIG_LPT_MODE_EPP_17_AND_SPP +#elif IS_ENABLED(CONFIG_LPT_MODE_EPP_17_AND_SPP) ppmod = 5; -#elif CONFIG_LPT_MODE_ECP_AND_EPP_17 +#elif IS_ENABLED(CONFIG_LPT_MODE_ECP_AND_EPP_17) ppmod = 7; #else #error CONFIG_LPT_MODE error. @@ -303,67 +303,67 @@ * Bit 31-16 : DBA, GPIO direction base address. * Bit 15-0 : DPBA, GPIO data port base address. * */ -#if CONFIG_GPIO_P0_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P0_ENABLE) SETUP_GPIO_ADDR(0) #endif -#if CONFIG_GPIO_P1_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P1_ENABLE) SETUP_GPIO_ADDR(1) #endif -#if CONFIG_GPIO_P2_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P2_ENABLE) SETUP_GPIO_ADDR(2) #endif -#if CONFIG_GPIO_P3_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P3_ENABLE) SETUP_GPIO_ADDR(3) #endif -#if CONFIG_GPIO_P4_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P4_ENABLE) SETUP_GPIO_ADDR(4) #endif -#if CONFIG_GPIO_P5_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P5_ENABLE) SETUP_GPIO_ADDR(5) #endif -#if CONFIG_GPIO_P6_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P6_ENABLE) SETUP_GPIO_ADDR(6) #endif -#if CONFIG_GPIO_P7_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P7_ENABLE) SETUP_GPIO_ADDR(7) #endif -#if CONFIG_GPIO_P8_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P8_ENABLE) SETUP_GPIO_ADDR(8) #endif -#if CONFIG_GPIO_P9_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P9_ENABLE) SETUP_GPIO_ADDR(9) #endif /* Enable GPIO port 0~9. */ outl(gpio_enable_mask, base); /* Set GPIO port 0-9 initial dir and data. */ -#if CONFIG_GPIO_P0_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P0_ENABLE) INIT_GPIO(0) #endif -#if CONFIG_GPIO_P1_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P1_ENABLE) INIT_GPIO(1) #endif -#if CONFIG_GPIO_P2_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P2_ENABLE) INIT_GPIO(2) #endif -#if CONFIG_GPIO_P3_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P3_ENABLE) INIT_GPIO(3) #endif -#if CONFIG_GPIO_P4_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P4_ENABLE) INIT_GPIO(4) #endif -#if CONFIG_GPIO_P5_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P5_ENABLE) INIT_GPIO(5) #endif -#if CONFIG_GPIO_P6_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P6_ENABLE) INIT_GPIO(6) #endif -#if CONFIG_GPIO_P7_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P7_ENABLE) INIT_GPIO(7) #endif -#if CONFIG_GPIO_P8_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P8_ENABLE) INIT_GPIO(8) #endif -#if CONFIG_GPIO_P9_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P9_ENABLE) INIT_GPIO(9) #endif /* Disable GPIO Port Config IO Base Address. */ @@ -391,34 +391,34 @@ /* S/B register 61h - 60h : UART Config IO Base Address */ pci_write_config16(dev, SB_REG_UART_CFG_IO_BASE, base | 1); /* setup UART */ -#if CONFIG_UART1_ENABLE +#if IS_ENABLED(CONFIG_UART1_ENABLE) SETUP_UART(1) #endif -#if CONFIG_UART2_ENABLE +#if IS_ENABLED(CONFIG_UART2_ENABLE) SETUP_UART(2) #endif -#if CONFIG_UART3_ENABLE +#if IS_ENABLED(CONFIG_UART3_ENABLE) SETUP_UART(3) #endif -#if CONFIG_UART4_ENABLE +#if IS_ENABLED(CONFIG_UART4_ENABLE) SETUP_UART(4) #endif -#if CONFIG_UART5_ENABLE +#if IS_ENABLED(CONFIG_UART5_ENABLE) SETUP_UART(5) #endif -#if CONFIG_UART6_ENABLE +#if IS_ENABLED(CONFIG_UART6_ENABLE) SETUP_UART(6) #endif -#if CONFIG_UART7_ENABLE +#if IS_ENABLED(CONFIG_UART7_ENABLE) SETUP_UART(7) #endif -#if CONFIG_UART8_ENABLE +#if IS_ENABLED(CONFIG_UART8_ENABLE) SETUP_UART(8) #endif -#if CONFIG_UART9_ENABLE +#if IS_ENABLED(CONFIG_UART9_ENABLE) SETUP_UART(9) #endif -#if CONFIG_UART10_ENABLE +#if IS_ENABLED(CONFIG_UART10_ENABLE) SETUP_UART(10) #endif /* Keep UART Config I/O base address */ diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index 6c04ec3..f07ffc9 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -70,7 +70,7 @@ #define I2CTAG "[I2C][PL] " -#if CONFIG_DEBUG_I2C +#if IS_ENABLED(CONFIG_DEBUG_I2C) #define I2CLOG(fmt, arg...) printk(BIOS_INFO, I2CTAG fmt, ##arg) #else #define I2CLOG(fmt, arg...) diff --git a/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h index 1411d39..8d449f7 100644 --- a/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h @@ -178,7 +178,7 @@ void tx_delay_for_wrleveling(u32 channel, struct dqs_perbit_dly *dqdqs_perbit_dly, u8 *ave_dqdly_byte, u8 *max_dqsdly_byte); -#if CONFIG_DEBUG_DRAM +#if IS_ENABLED(CONFIG_DEBUG_DRAM) #define dramc_dbg_msg(_x_...) printk(BIOS_DEBUG, _x_) #else #define dramc_dbg_msg(_x_...) diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c index ec7fabc..9ba3503 100644 --- a/src/soc/mediatek/mt8173/mt6391.c +++ b/src/soc/mediatek/mt8173/mt6391.c @@ -21,7 +21,7 @@ #include <soc/pmic_wrap.h> #include <types.h> -#if CONFIG_DEBUG_PMIC +#if IS_ENABLED(CONFIG_DEBUG_PMIC) #define DEBUG_PMIC(level, x...) printk(level, x) #else #define DEBUG_PMIC(level, x...) diff --git a/src/soc/nvidia/tegra210/include/soc/mtc.h b/src/soc/nvidia/tegra210/include/soc/mtc.h index fa07f33..ca369ad 100644 --- a/src/soc/nvidia/tegra210/include/soc/mtc.h +++ b/src/soc/nvidia/tegra210/include/soc/mtc.h @@ -18,7 +18,7 @@ #include <boot/coreboot_tables.h> -#if CONFIG_HAVE_MTC +#if IS_ENABLED(CONFIG_HAVE_MTC) int tegra210_run_mtc(void); void soc_add_mtc(struct lb_header *header); diff --git a/src/soc/nvidia/tegra210/romstage.c b/src/soc/nvidia/tegra210/romstage.c index 9491570..7b6444d 100644 --- a/src/soc/nvidia/tegra210/romstage.c +++ b/src/soc/nvidia/tegra210/romstage.c @@ -45,7 +45,7 @@ printk(BIOS_INFO, "T210: romstage here\n"); -#if CONFIG_BOOTROM_SDRAM_INIT +#if IS_ENABLED(CONFIG_BOOTROM_SDRAM_INIT) printk(BIOS_INFO, "T210 romstage: SDRAM init done by BootROM, RAMCODE = %d\n", sdram_get_ram_code()); #else -- To view, visit https://review.coreboot.org/20355 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2e7b756296e861e08cea846297f687a880daaf45 Gerrit-Change-Number: 20355 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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coreboot-gerrit June 2017