coreboot-gerrit June 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/intel/dg41wv: Add mainboard
by Arthur Heymans (Code Review) 01 Jun '17

01 Jun '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/20003 to look at the new patch set (#3). Change subject: mb/intel/dg41wv: Add mainboard ...................................................................... mb/intel/dg41wv: Add mainboard Tested with one 2G single rank DDR3 dimm, booted SeaBIOS and Linux 4.9. Needs smbus_block_write patches for VGA output not to be wobbly, by configuring the clockgen on smbus offset 0x69. Change-Id: If01bf658e52d273c3c203d362f21c3cb9c623f40 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/intel/dg41wv/Kconfig A src/mainboard/intel/dg41wv/Kconfig.name A src/mainboard/intel/dg41wv/Makefile.inc A src/mainboard/intel/dg41wv/acpi/ec.asl A src/mainboard/intel/dg41wv/acpi/ich7_pci_irqs.asl A src/mainboard/intel/dg41wv/acpi/platform.asl A src/mainboard/intel/dg41wv/acpi/superio.asl A src/mainboard/intel/dg41wv/acpi/x4x_pci_irqs.asl A src/mainboard/intel/dg41wv/acpi_tables.c A src/mainboard/intel/dg41wv/board_info.txt A src/mainboard/intel/dg41wv/cmos.default A src/mainboard/intel/dg41wv/cmos.layout A src/mainboard/intel/dg41wv/cstates.c A src/mainboard/intel/dg41wv/devicetree.cb A src/mainboard/intel/dg41wv/dsdt.asl A src/mainboard/intel/dg41wv/gpio.c A src/mainboard/intel/dg41wv/hda_verb.c A src/mainboard/intel/dg41wv/romstage.c 18 files changed, 875 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/20003/3 -- To view, visit https://review.coreboot.org/20003 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: If01bf658e52d273c3c203d362f21c3cb9c623f40 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: ec/google/chromeec: Fix typo in ECUI device
by Furquan Shaikh (Code Review) 01 Jun '17

01 Jun '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/20007 ) Change subject: ec/google/chromeec: Fix typo in ECUI device ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/20007 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I387b1c36aa115e03d0c6f9939eb13c93b14ad909 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: ec/google/chromeec: Fix typo in ECUI device
by build bot (Jenkins) (Code Review) 01 Jun '17

01 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20007 ) Change subject: ec/google/chromeec: Fix typo in ECUI device ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/54744/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/10447/ : SUCCESS -- To view, visit https://review.coreboot.org/20007 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I387b1c36aa115e03d0c6f9939eb13c93b14ad909 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: ec/google/chromeec: Fix typo in ECUI device
by Duncan Laurie (Code Review) 01 Jun '17

01 Jun '17

Duncan Laurie has uploaded a new change for review. ( https://review.coreboot.org/20007 ) Change subject: ec/google/chromeec: Fix typo in ECUI device ...................................................................... ec/google/chromeec: Fix typo in ECUI device The IO region defined for EC_HOST_CMD_REGION1 was incorrectly using EC_HOST_CMD_REGION0 for the range maximum so the region was showing a minimum of 0x880 and a maximum of 0x800. Both min and max should report the same value as this region is fixed and cannot be relocated by the OS. Change-Id: I387b1c36aa115e03d0c6f9939eb13c93b14ad909 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/ec/google/chromeec/acpi/superio.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/20007/1 diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl index 04b112f..0f06e30 100644 --- a/src/ec/google/chromeec/acpi/superio.asl +++ b/src/ec/google/chromeec/acpi/superio.asl @@ -82,7 +82,7 @@ EC_HOST_CMD_REGION0, EC_HOST_CMD_REGION0, 0x08, EC_HOST_CMD_REGION_SIZE) IO (Decode16, - EC_HOST_CMD_REGION1, EC_HOST_CMD_REGION0, 0x08, + EC_HOST_CMD_REGION1, EC_HOST_CMD_REGION1, 0x08, EC_HOST_CMD_REGION_SIZE) }) -- To view, visit https://review.coreboot.org/20007 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I387b1c36aa115e03d0c6f9939eb13c93b14ad909 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: google/gru: enable the pull high for touchpad
by Julius Werner (Code Review) 01 Jun '17

01 Jun '17

Julius Werner has posted comments on this change. ( https://review.coreboot.org/19863 ) Change subject: google/gru: enable the pull high for touchpad ...................................................................... Patch Set 2: (1 comment) Okay... if what Jeffy said is right and the delay (with new firmware) is one second, I would be okay with merging something like this. But please explain more clearly in the commit message that we have to drive the stronger pull-up within 1 second of powering up the touchpad to prevent its firmware from falling into recovery. https://review.coreboot.org/#/c/19863/2/src/mainboard/google/gru/romstage.c File src/mainboard/google/gru/romstage.c: Line 81: prepare_i2c(); If the required delay is a full second, it should be okay to put this in ramstage. -- To view, visit https://review.coreboot.org/19863 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I9a67d1c041afafde24ed9f00716ba41a9b41a8da Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: sb/intel/*: Use common SMBus functions
by build bot (Jenkins) (Code Review) 01 Jun '17

01 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19258 ) Change subject: sb/intel/*: Use common SMBus functions ...................................................................... Patch Set 17: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/54743/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/10446/ : SUCCESS -- To view, visit https://review.coreboot.org/19258 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962 Gerrit-PatchSet: 17 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/*: Use common SMBus functions
by Arthur Heymans (Code Review) 01 Jun '17

01 Jun '17

Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19258 to look at the new patch set (#17). Change subject: sb/intel/*: Use common SMBus functions ...................................................................... sb/intel/*: Use common SMBus functions All Intel southbridges implement the same SMBus functions. This patch replaces all these similar and mostly identical implementations with a common file. This also makes i2c block read available to all those southbridges. If the northbridge has to read a lot of SPD bytes sequentially, using this function can reduce the time being spent to read SPD five-fold. Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/sandybridge/raminit.c M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/bd82x6x/smbus.c D src/southbridge/intel/bd82x6x/smbus.h M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc R src/southbridge/intel/common/smbus.c A src/southbridge/intel/common/smbus.h M src/southbridge/intel/fsp_bd82x6x/Kconfig M src/southbridge/intel/fsp_i89xx/Kconfig M src/southbridge/intel/fsp_i89xx/early_smbus.c M src/southbridge/intel/fsp_i89xx/pch.h D src/southbridge/intel/fsp_i89xx/smbus.h M src/southbridge/intel/fsp_rangeley/Kconfig M src/southbridge/intel/fsp_rangeley/early_smbus.c M src/southbridge/intel/fsp_rangeley/smbus.c D src/southbridge/intel/fsp_rangeley/smbus.h M src/southbridge/intel/fsp_rangeley/soc.h M src/southbridge/intel/i3100/Kconfig M src/southbridge/intel/i3100/early_smbus.c M src/southbridge/intel/i3100/smbus.c D src/southbridge/intel/i3100/smbus.h M src/southbridge/intel/i82371eb/Kconfig M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/intel/i82371eb/smbus.c D src/southbridge/intel/i82371eb/smbus.h M src/southbridge/intel/i82801ax/Kconfig M src/southbridge/intel/i82801ax/early_smbus.c M src/southbridge/intel/i82801ax/i82801ax.h M src/southbridge/intel/i82801ax/smbus.c D src/southbridge/intel/i82801ax/smbus.h M src/southbridge/intel/i82801bx/Kconfig M src/southbridge/intel/i82801bx/early_smbus.c M src/southbridge/intel/i82801bx/i82801bx.h M src/southbridge/intel/i82801bx/smbus.c D src/southbridge/intel/i82801bx/smbus.h M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801dx/i82801dx.h D src/southbridge/intel/i82801dx/smbus.c M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801gx/smbus.c D src/southbridge/intel/i82801gx/smbus.h M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801ix/smbus.c D src/southbridge/intel/i82801ix/smbus.h M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/ibexpeak/smbus.c M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/early_smbus.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/smbus.c D src/southbridge/intel/lynxpoint/smbus.h 61 files changed, 234 insertions(+), 1,807 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/19258/17 -- To view, visit https://review.coreboot.org/19258 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962 Gerrit-PatchSet: 17 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: [RFC] util/hugo: Add pre-processing
by Patrick Georgi (Code Review) 01 Jun '17

01 Jun '17

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/19922 ) Change subject: [RFC] util/hugo: Add pre-processing ...................................................................... Patch Set 1: could this be solved with a blackfriday plugin (when there's a way to add it to the container)? I'd prefer that over this kind of preprocessing. -- To view, visit https://review.coreboot.org/19922 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I8bb9365e84348997b04ef027b25e316fdac1ad5d Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: [WIP]soc/intel/apollolake: Add support in APL for PMC common...
by Hannah Williams (Code Review) 01 Jun '17

01 Jun '17

Hannah Williams has posted comments on this change. ( https://review.coreboot.org/19375 ) Change subject: [WIP]soc/intel/apollolake: Add support in APL for PMC common code ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/#/c/19375/10/src/soc/intel/apollolake/pmutil.c File src/soc/intel/apollolake/pmutil.c: PS10, Line 102: : uint16_t print_pm1_status(uint16_t pm1_sts) : { : static const char *const pm1_sts_bits[] = { why can't pm1_sts printing be moved to common code because the bits in here are anyway fixed in ACPI -- To view, visit https://review.coreboot.org/19375 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I322a25a8b608d7fe98bec626c6696e723357a9d2 Gerrit-PatchSet: 10 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/common/block: Add Intel common systemagent support
by Subrata Banik (Code Review) 01 Jun '17

01 Jun '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19668 ) Change subject: soc/intel/common/block: Add Intel common systemagent support ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/#/c/19668/8/src/soc/intel/common/block/include/… File src/soc/intel/common/block/include/intelblocks/systemagent.h: PS8, Line 25: #define MCHBAR 0x48 : #define GGC 0x50 : #define PCIEXBAR 0x60 : #define PCIEXBAR_LENGTH_64MB 2 : #define PCIEXBAR_LENGTH_128MB 1 : #define PCIEXBAR_LENGTH_256MB 0 : #define PCIEXBAR_PCIEXBAREN (1 << 0) : : #define PAM0 0x80 : #define PAM1 0x81 : #define PAM2 0x82 : #define PAM3 0x83 : #define PAM4 0x84 : #define PAM5 0x85 : #define PAM6 0x86 : : #define TOUUD 0xa8 /* Top of Upper Usable DRAM */ : #define BDSM 0xb0 /* Base Data Stolen Memory */ : #define BGSM 0xb4 /* Base GTT Stolen Memory */ : #define TSEG 0xb8 /* TSEG base */ : #define TOLUD 0xbc /* Top of Low Used Memory */ : : /* MCHBAR */ : #define MCHBAR8(x) (*(volatile u8 *)(MCH_BASE_ADDRESS + x)) : #define MCHBAR16(x) (*(volatile u16 *)(MCH_BASE_ADDRESS + x)) > Is all of this necessary to be exposed to the user of this module? i guess we can move this into sa-def.h which is local to SA code. https://review.coreboot.org/#/c/19668/8/src/soc/intel/common/block/systemag… File src/soc/intel/common/block/systemagent/systemagent.c: Line 238: return size_k; > I'm trying to understand why all this code was changed from apl. that code If your question specific about IMR implementation, why i havn;t copied entirely from APL IMR API. I could have done that, if you need, i will do this. But if your question is why entire SA not copied from APL, then answer is APL SA code don't provide me any options to use soc like override concept which SKL code provides. if you see fixed resource allocation table. In APL its done inside same function but SKL use a structure although static but we could make it extern to solve soc override concept as CNL might have diffent entries for the same. And rest DRAM and IMR, i was trying to match as close as APL because no inputs required from SOC. -- To view, visit https://review.coreboot.org/19668 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I969ff187e3d4199864cb2e9c9a13f4d04158e27c Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: Yes

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coreboot-gerrit June 2017