coreboot-gerrit June 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: src/soc/intel/common: Modify smihandler calls as per common ...
by build bot (Jenkins) (Code Review) 02 Jun '17

02 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20006 ) Change subject: src/soc/intel/common: Modify smihandler calls as per common pmc code ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/54765/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/10468/ : SUCCESS -- To view, visit https://review.coreboot.org/20006 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iabadd80962324cf8de6a01d24aad25d257bcb048 Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: google/fizz: Enable onboard lan
by Shelley Chen (Code Review) 02 Jun '17

02 Jun '17

Shelley Chen has uploaded a new change for review. ( https://review.coreboot.org/20008 ) Change subject: google/fizz: Enable onboard lan ...................................................................... google/fizz: Enable onboard lan BUG=b:62090148, b:35775024 BRANCH=None TEST=Boot to kernel. Ensure we have ip address with ifconfig. Ensure ethernet controller shows up with lspci. Change-Id: I7ff29de2c4c3635dc786686cc071c68d51b0f975 Signed-off-by: Shelley Chen <shchen(a)chromium.org> --- M src/mainboard/google/fizz/Makefile.inc A src/mainboard/google/fizz/lan.c M src/mainboard/google/fizz/mainboard.c A src/mainboard/google/fizz/onboard.h 4 files changed, 245 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/20008/1 diff --git a/src/mainboard/google/fizz/Makefile.inc b/src/mainboard/google/fizz/Makefile.inc index d74b707..b89e833 100644 --- a/src/mainboard/google/fizz/Makefile.inc +++ b/src/mainboard/google/fizz/Makefile.inc @@ -24,6 +24,7 @@ ramstage-y += boardid.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c +ramstage-y += lan.c ramstage-y += mainboard.c ramstage-y += ramstage.c diff --git a/src/mainboard/google/fizz/lan.c b/src/mainboard/google/fizz/lan.c new file mode 100644 index 0000000..ff1571c --- /dev/null +++ b/src/mainboard/google/fizz/lan.c @@ -0,0 +1,192 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <string.h> +#include <types.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <fmap.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include "onboard.h" + +static unsigned int search(char *p, u8 *a, unsigned int lengthp, + unsigned int lengtha) +{ + int i, j; + + /* Searching */ + for (j = 0; j <= lengtha - lengthp; j++) { + for (i = 0; i < lengthp && p[i] == a[i + j]; i++) + ; + if (i >= lengthp) + return j; + } + return lengtha; +} + +static unsigned char get_hex_digit(u8 *offset) +{ + unsigned char retval = 0; + + retval = *offset - '0'; + if (retval > 0x09) { + retval = *offset - 'A' + 0x0A; + if (retval > 0x0F) + retval = *offset - 'a' + 0x0a; + } + if (retval > 0x0F) { + printk(BIOS_DEBUG, "Error: Invalid Hex digit found: %c - 0x%02x\n", + *offset, *offset); + retval = 0; + } + + return retval; +} + +static int get_mac_address(u32 *high_dword, u32 *low_dword, + u8 *search_address, u32 search_length) +{ + char key[] = "ethernet_mac"; + unsigned int offset; + int i; + + offset = search(key, search_address, sizeof(key) - 1, search_length); + if (offset == search_length) { + printk(BIOS_DEBUG, + "Error: Could not locate '%s' in VPD\n", key); + return 0; + } + printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); + + offset += sizeof(key); /* move to next character */ + *high_dword = 0; + + /* Fetch the MAC address and put the octets in the correct order to + * be programmed. + * + * From RTL8105E_Series_EEPROM-Less_App_Note_1.1 + * If the MAC address is 001122334455h: + * Write 33221100h to I/O register offset 0x00 via double word access + * Write 00005544h to I/O register offset 0x04 via double word access + */ + + for (i = 0; i < 4; i++) { + *high_dword |= (get_hex_digit(search_address + offset) + << (4 + (i * 8))); + *high_dword |= (get_hex_digit(search_address + offset + 1) + << (i * 8)); + offset += 3; + } + + *low_dword = 0; + for (i = 0; i < 2; i++) { + *low_dword |= (get_hex_digit(search_address + offset) + << (4 + (i * 8))); + *low_dword |= (get_hex_digit(search_address + offset + 1) + << (i * 8)); + offset += 3; + } + + return *high_dword | *low_dword; +} + +static void program_mac_address(u16 io_base) +{ + void *search_address = NULL; + size_t search_length = -1; + + /* Default MAC Address of A0:00:BA:D0:0B:AD */ + u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ + u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ + + if (IS_ENABLED(CONFIG_CHROMEOS)) { + struct region_device rdev; + + if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { + search_address = rdev_mmap_full(&rdev); + + if (search_address != NULL) + search_length = region_device_sz(&rdev); + } + } else { + search_address = cbfs_boot_map_with_leak("vpd.bin", + CBFS_TYPE_RAW, + &search_length); + } + + if (search_address == NULL) + printk(BIOS_ERR, "LAN: VPD not found.\n"); + else + get_mac_address(&high_dword, &low_dword, search_address, + search_length); + + if (io_base) { + printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base); + printk(BIOS_DEBUG, "Programming MAC Address\n"); + + /* Disable register protection */ + outb(0xc0, io_base + 0x50); + outl(high_dword, io_base); + outl(low_dword, io_base + 0x04); + outb(0x60, io_base + 54); + /* Enable register protection again */ + outb(0x00, io_base + 0x50); + } +} + +void lan_init(void) +{ + u16 io_base = 0; + struct device *ethernet_dev = NULL; + + /* Get NIC's IO base address */ + ethernet_dev = dev_find_device(NIC_VENDOR_ID, + NIC_DEVICE_ID, 0); + if (ethernet_dev != NULL) { + io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe; + + /* + * Battery life time - LAN PCIe should enter ASPM L1 to save + * power when LAN connection is idle. + * enable CLKREQ: LAN pci config space 0x81h=01 + */ + pci_write_config8(ethernet_dev, 0x81, 0x01); + } + + if (io_base) { + /* Program MAC address based on VPD data */ + program_mac_address(io_base); + + /* + * Program NIC LEDS + * + * RTL8105E Series EEPROM-Less Application Note, + * Section 5.6 LED Mode Configuration + * + * Step1: Write C0h to I/O register 0x50 via byte access to + * disable 'register protection' + * Step2: Write xx001111b to I/O register 0x52 via byte access + * (bit7 is LEDS1 and bit6 is LEDS0) + * Step3: Write 0x00 to I/O register 0x50 via byte access to + * enable 'register protection' + */ + outb(0xc0, io_base + 0x50); /* Disable protection */ + outb((NIC_LED_MODE << 6) | 0x0f, io_base + 0x52); + outb(0x00, io_base + 0x50); /* Enable register protection */ + } +} diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index d515d29..0fe818d 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -18,10 +18,12 @@ #include <device/device.h> #include <ec/ec.h> #include <vendorcode/google/chromeos/chromeos.h> +#include "onboard.h" static void mainboard_init(device_t dev) { mainboard_ec_init(); + lan_init(); } static void mainboard_enable(device_t dev) diff --git a/src/mainboard/google/fizz/onboard.h b/src/mainboard/google/fizz/onboard.h new file mode 100644 index 0000000..4e68d25 --- /dev/null +++ b/src/mainboard/google/fizz/onboard.h @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_ONBOARD_H +#define __MAINBOARD_ONBOARD_H + +/* defines for programming the MAC address */ +#define NIC_VENDOR_ID 0x10EC +#define NIC_DEVICE_ID 0x8168 + +/* 0x00: White LINK LED and Amber ACTIVE LED */ +#define NIC_LED_MODE 0x00 + +/* NIC wake is GPIO 8 */ +#define NIC_WAKE_GPIO 8 + +/* WLAN wake is GPIO 10 */ +#define WLAN_WAKE_GPIO 10 + +/* IT8772F defs */ +#define IT8772F_BASE 0x2e +#define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1) +#define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO) +#define IT8772F_DUMMY_DEV PNP_DEV(IT8772F_BASE, 0) + +#ifndef __ACPI__ +void lan_init(void); + +void set_power_led(int state); + +enum { + LED_OFF = 0, + LED_ON, + LED_BLINK, +}; +#endif + +#endif /* __MAINBOARD_ONBOARD_H */ -- To view, visit https://review.coreboot.org/20008 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I7ff29de2c4c3635dc786686cc071c68d51b0f975 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shelley Chen <shchen(a)google.com>

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Change in coreboot[master]: src/soc/intel/common: Modify smihandler calls as per common ...
by Shaunak Saha (Code Review) 02 Jun '17

02 Jun '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/20006 to look at the new patch set (#7). Change subject: src/soc/intel/common: Modify smihandler calls as per common pmc code ...................................................................... src/soc/intel/common: Modify smihandler calls as per common pmc code Change-Id: Iabadd80962324cf8de6a01d24aad25d257bcb048 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- M src/soc/intel/common/smihandler.c 1 file changed, 80 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/20006/7 -- To view, visit https://review.coreboot.org/20006 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iabadd80962324cf8de6a01d24aad25d257bcb048 Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/common/block/gpio: Port gpio code from Apollolake ...
by Hannah Williams (Code Review) 01 Jun '17

01 Jun '17

Hannah Williams has posted comments on this change. ( https://review.coreboot.org/19759 ) Change subject: soc/intel/common/block/gpio: Port gpio code from Apollolake to common ...................................................................... Patch Set 20: (1 comment) https://review.coreboot.org/#/c/19759/20/src/soc/intel/common/block/gpio/gp… File src/soc/intel/common/block/gpio/gpio.c: PS20, Line 123: PAD_CFG_BASE > I believe this has to be provided by the SoC. It would be good to document Since I am planning to represent a group within a community (as in SKL) also with the same struct pad_community, a fixed PAD_CFG_BASE will not work for groups within a community - so I will instead add a field inside struct pad_community for this - With this I think we can also address the big core groups and each group should be represented by a struct pad_community (should I change the name from pad_community to pad_community_or_group ?) -- To view, visit https://review.coreboot.org/19759 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Gerrit-PatchSet: 20 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chella(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: sb/intel/bd82x6x/early_usb: Use register name
by Philippe Mathieu-Daudé (Code Review) 01 Jun '17

01 Jun '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/19954 ) Change subject: sb/intel/bd82x6x/early_usb: Use register name ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/19954 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I4f2f3f196c12489613333ab9f6098443edda927f Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block/gpio: Port gpio code from Apollolake ...
by Hannah Williams (Code Review) 01 Jun '17

01 Jun '17

Hannah Williams has posted comments on this change. ( https://review.coreboot.org/19759 ) Change subject: soc/intel/common/block/gpio: Port gpio code from Apollolake to common ...................................................................... Patch Set 15: (1 comment) https://review.coreboot.org/#/c/19759/15/src/soc/intel/common/block/gpio/gp… File src/soc/intel/common/block/gpio/gpio.c: PS15, Line 68: GPIO_MAX_NUM_PER_GROUP > I'll add this as a field inside the community. I looked across GPIOs in different SOC EDS. Although different groups have different pin count - for example, GPA has 24 and GPD has 12 , but as long as they are less than 32 which is the register size, they still will be bit mapped into 1 register. In this function and gpio_configure_owner, the pin parameter passed is the pin offset within this community or group. So I think we can still use the macro GPIO_MAX_NUM_PER_GROUP to get the max number which is 24 in example above and not have a new field added to get this number per group or community. -- To view, visit https://review.coreboot.org/19759 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Gerrit-PatchSet: 15 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chella(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: mb/asus/p5gc-mx: Implement resume from S3 support
by build bot (Jenkins) (Code Review) 01 Jun '17

01 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19602 ) Change subject: mb/asus/p5gc-mx: Implement resume from S3 support ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/54764/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/10467/ : SUCCESS -- To view, visit https://review.coreboot.org/19602 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I6ac927ee9dcce15fc7621aad57969fae8f5805ca Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: src/soc/intel/common: Modify smihandler calls as per common ...
by Shaunak Saha (Code Review) 01 Jun '17

01 Jun '17

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/20006 ) Change subject: src/soc/intel/common: Modify smihandler calls as per common pmc code ...................................................................... Patch Set 6: -Code-Review -- To view, visit https://review.coreboot.org/20006 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iabadd80962324cf8de6a01d24aad25d257bcb048 Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mb/intel/dg41wv: Add mainboard
by build bot (Jenkins) (Code Review) 01 Jun '17

01 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20003 ) Change subject: mb/intel/dg41wv: Add mainboard ...................................................................... Patch Set 4: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/54763/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/10466/ : SUCCESS -- To view, visit https://review.coreboot.org/20003 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: If01bf658e52d273c3c203d362f21c3cb9c623f40 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mb/asus/p5gc-mx: Implement resume from S3 support
by Arthur Heymans (Code Review) 01 Jun '17

01 Jun '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19602 to look at the new patch set (#2). Change subject: mb/asus/p5gc-mx: Implement resume from S3 support ...................................................................... mb/asus/p5gc-mx: Implement resume from S3 support Needs the ramstage configuration enabling of SuperIO GPIO pnp devices for BSEL straps. Also needs VSBGATE# to be on for ram to be powered during S3. TESTED with 800MHz ans 1067MHz FSB CPUs at the correct straps when resuming from S3. Change-Id: I6ac927ee9dcce15fc7621aad57969fae8f5805ca Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asus/p5gc-mx/Kconfig M src/mainboard/asus/p5gc-mx/devicetree.cb M src/mainboard/asus/p5gc-mx/romstage.c 3 files changed, 26 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/19602/2 -- To view, visit https://review.coreboot.org/19602 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6ac927ee9dcce15fc7621aad57969fae8f5805ca Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit June 2017