coreboot-gerrit June 2017

coreboot-gerrit@coreboot.org
  • 1 participants
  • 2269 discussions
Change in coreboot[master]: nb/intel/x4x/raminit: Limit DDR3 to 400MHz
by build bot (Jenkins) (Code Review) 01 Jun '17

01 Jun '17

01 Jun '17
Change in coreboot[master]: nb/intel/x4x: Adapt post JEDEC for DDR3
by build bot (Jenkins) (Code Review) 01 Jun '17

01 Jun '17
Change in coreboot[master]: nb/intel/x4x: DDR3 JEDEC init
by build bot (Jenkins) (Code Review) 01 Jun '17

01 Jun '17
Change in coreboot[master]: nb/intel/x4x/raminit: Add write leveling
by build bot (Jenkins) (Code Review) 01 Jun '17

01 Jun '17
Change in coreboot[master]: nb/intel/x4x/raminit: DDR3 specific ODT
by build bot (Jenkins) (Code Review) 01 Jun '17

01 Jun '17
Change in coreboot[master]: nb/x4x/raminit: Decode ddr3 dimms
by build bot (Jenkins) (Code Review) 01 Jun '17

01 Jun '17
Change in coreboot[master]: nb/intel/x4x: Add DDR3 rcomp
by build bot (Jenkins) (Code Review) 01 Jun '17

01 Jun '17
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