Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19927 )
Change subject: soc/intel/apollolake: Remove unused PCI ID from SOC header
......................................................................
Patch Set 3:
> > > Apparently this is a dupe: https://review.coreboot.org/#/c/19999/
> >
> > :) first patch was on 26th May. not sure how this got missed.
>
> Ya. Sorry. I just continually cycle back through my inbox. A lot of
> the patches seem like a blur.
thanks aaron for your time to review the patch and provide great feedback. Don't bother about my last comment, its okay :)
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Gerrit-Change-Id: I3a86256641f4b877de32ca81dfdaef4e9d49334a
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Hello Paul Menzel, build bot (Jenkins), coreboot org, Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18692
to look at the new patch set (#23).
Change subject: nb/intel/x4x/raminit: Rework receive enable calibration
......................................................................
nb/intel/x4x/raminit: Rework receive enable calibration
Moves receive enable calibration to a separate file to lighten
raminit.c a bit.
Receive enable calibration is quite similar to gm45 so it reuses some
of its function names.
The functional changes are:
* the minimum coarse is now reset for each channel;
* on the second fine search for DQS high, TAP overflow is handled by
increasing medium;
* start coarse at CAS + 1 instead of CAS - 1. Other Intel northbridges
do the same and the results are more in line with register dumps
from vendor bios.
These might improve stability.
TESTED on ga-g41m-es2l
Change-Id: I0c970455e609d3ce96a262cbf110336a2079da4d
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/northbridge/intel/x4x/Makefile.inc
M src/northbridge/intel/x4x/raminit_ddr2.c
A src/northbridge/intel/x4x/rcven.c
M src/northbridge/intel/x4x/x4x.h
4 files changed, 368 insertions(+), 282 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/18692/23
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Hello Paul Menzel, build bot (Jenkins), coreboot org, Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18692
to look at the new patch set (#22).
Change subject: nb/intel/x4x/raminit: Rework receive enable calibration
......................................................................
nb/intel/x4x/raminit: Rework receive enable calibration
Moves receive enable calibration to a separate file to lighten
raminit.c a bit.
Receive enable calibration is quite similar to gm45 so it reuses some
of its function names.
The functional changes are:
* the minimum coarse is now reset for each channel;
* on the second fine search for DQS high, TAP overflow is handled by
increasing medium;
* start coarse at CAS + 1 instead of CAS - 1. Other Intel northbridges
do the same and the results are more in line with register dumps
from vendor bios.
These might improve stability.
TESTED on ga-g41m-es2l
Change-Id: I0c970455e609d3ce96a262cbf110336a2079da4d
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/northbridge/intel/x4x/Makefile.inc
M src/northbridge/intel/x4x/raminit_ddr2.c
A src/northbridge/intel/x4x/rcven.c
M src/northbridge/intel/x4x/x4x.h
4 files changed, 372 insertions(+), 282 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/18692/22
--
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Gerrit-PatchSet: 22
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/18692 )
Change subject: nb/intel/x4x/raminit: Rework receive enable calibration
......................................................................
Patch Set 21:
(3 comments)
https://review.coreboot.org/#/c/18692/21/src/northbridge/intel/x4x/rcven.c
File src/northbridge/intel/x4x/rcven.c:
PS21, Line 40: #define SAMPLE_COUNT 3
does not seem to improve things.
PS21, Line 174: if (sampledqs(addr, lane, channel, DQS_HIGH)) {
: printk(BIOS_WARNING, "DQS already HIGH... DQS probe is incosistent!\n"
: "Continuing, but be cautious of possible instabilities.\n");
Is still being hit very consistently, so I think there is some hysteresis in this dram controller. I'll just documented it and maybe adapt printed message.
PS21, Line 218: /* Some settings are very noisy. Check the next tap */
: /* if the result of the probe is consistent. */
: if (sampledqs(addr, lane, channel, DQS_HIGH)) {
: increase_tap(timing);
: program_timing(timing, channel, lane);
: if (sampledqs(addr, lane, channel, DQS_HIGH)) {
: decrease_tap(timing);
: program_timing(timing, channel, lane);
: break;
: } else {
: decrease_tap(timing);
: }
: }
Does not seem to improve things since problems don't seem to be caused that much by noise but by hysteresis.
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19927 )
Change subject: soc/intel/apollolake: Remove unused PCI ID from SOC header
......................................................................
Patch Set 3:
> Apparently this is a dupe: https://review.coreboot.org/#/c/19999/
:) first patch was on 26th May. not sure how this got missed.
--
To view, visit https://review.coreboot.org/19927
To unsubscribe, visit https://review.coreboot.org/settings
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