Julius Werner has posted comments on this change. ( https://review.coreboot.org/19764 )
Change subject: lib/edid: Split out fill_lb_framebuffer()
......................................................................
Patch Set 6: Code-Review+1
Thanks, I'm okay with this as well. (I'm still not quite sure in what situation you think this is better than the weak symbol solution. Are you concerned about hypothetical platforms that could offer both native init and libgfxinit as choices? But then you just hide the source files that prove fill_lb_framebuffer() behind CONFIG_MAINBOARD_USE_LIBGFXINIT and it'll still work fine for either configuration? ...well, okay, as long as I don't have to select an extra option from every single ARM SoC I'm happy with it.)
--
To view, visit https://review.coreboot.org/19764
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: comment
Gerrit-Change-Id: I90634b835bd8e2d150b1c714328a5b2774d891bd
Gerrit-PatchSet: 6
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Julius Werner <jwerner(a)google.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-HasComments: No
Hello Arthur Heymans, Youness Alaoui, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19897
to look at the new patch set (#4).
Change subject: ec/librem/ec: Fix offset for Bluetooth enable (BTLE)
......................................................................
ec/librem/ec: Fix offset for Bluetooth enable (BTLE)
Test: boot OS (Ubuntu, Windows 10) on librem13v2, verify BT
function key toggle now works correctly.
Change-Id: I68dc99e72a09f7affbcd691d03dd4607a898313e
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/ec/purism/librem/acpi/ec.asl
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/19897/4
--
To view, visit https://review.coreboot.org/19897
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I68dc99e72a09f7affbcd691d03dd4607a898313e
Gerrit-PatchSet: 4
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Hello Aaron Durbin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19789
to look at the new patch set (#4).
Change subject: Consolidate reset API, add generic reset_prepare mechanism
......................................................................
Consolidate reset API, add generic reset_prepare mechanism
There are many good reasons why we may want to run some sort of generic
callback before we're executing a reset. Unfortunateley, that is really
hard right now: code that wants to reset simply calls the hard_reset()
function (or one of its ill-differentiated cousins) which is directly
implemented by a myriad of different mainboards, northbridges, SoCs,
etc. More recent x86 SoCs have tried to solve the problem in their own
little corner of soc/intel/common, but it's really something that would
benefit all of coreboot.
This patch expands the concept onto all boards: hard_reset() and friends
get implemented in a generic location where they can run hooks before
calling the platform-specific implementation that is now called
do_hard_reset(). The existing Intel reset_prepare() gets generalized as
soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now
easily be added later if necessary). We will also use this central point
to ensure all platforms flush their cache before reset, which is
generally useful for all cases where we're trying to persist information
in RAM across reboots (like the new persistent CBMEM console does).
Also remove cpu_reset() completely since it's not used anywhere and
doesn't seem very useful compared to the others.
Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
---
M src/include/reset.h
M src/lib/Makefile.inc
A src/lib/reset.c
M src/mainboard/asus/a8v-e_deluxe/romstage.c
M src/mainboard/asus/a8v-e_se/romstage.c
M src/mainboard/asus/k8v-x/romstage.c
M src/mainboard/asus/m2v-mx_se/romstage.c
M src/mainboard/asus/m2v/romstage.c
M src/mainboard/google/cosmos/reset.c
M src/mainboard/google/foster/reset.c
M src/mainboard/google/gale/reset.c
M src/mainboard/google/gru/reset.c
M src/mainboard/google/nyan/reset.c
M src/mainboard/google/nyan_big/reset.c
M src/mainboard/google/nyan_blaze/reset.c
M src/mainboard/google/purin/reset.c
M src/mainboard/google/rotor/reset.c
M src/mainboard/google/smaug/reset.c
M src/mainboard/google/storm/reset.c
M src/mainboard/google/veyron/reset.c
M src/mainboard/google/veyron_mickey/reset.c
M src/mainboard/google/veyron_rialto/reset.c
M src/northbridge/via/cx700/reset.c
M src/northbridge/via/vx900/northbridge.c
M src/soc/dmp/vortex86ex/hard_reset.c
M src/soc/imgtec/pistachio/reset.c
M src/soc/intel/apollolake/reset.c
M src/soc/intel/baytrail/reset.c
M src/soc/intel/broadwell/reset.c
M src/soc/intel/common/reset.c
M src/soc/intel/fsp_baytrail/reset.c
M src/soc/intel/fsp_broadwell_de/reset.c
M src/soc/intel/sch/reset.c
M src/soc/intel/skylake/reset.c
M src/soc/mediatek/mt8173/wdt.c
M src/soc/samsung/exynos5250/power.c
M src/southbridge/amd/agesa/hudson/reset.c
M src/southbridge/amd/amd8111/early_ctrl.c
M src/southbridge/amd/amd8111/reset.c
M src/southbridge/amd/cimx/sb700/reset.c
M src/southbridge/amd/cimx/sb800/reset.c
M src/southbridge/amd/cimx/sb900/reset.c
M src/southbridge/amd/pi/hudson/reset.c
M src/southbridge/amd/sb600/early_setup.c
M src/southbridge/amd/sb600/reset.c
M src/southbridge/amd/sb700/reset.c
M src/southbridge/amd/sb800/early_setup.c
M src/southbridge/amd/sb800/reset.c
M src/southbridge/broadcom/bcm5785/early_setup.c
M src/southbridge/broadcom/bcm5785/reset.c
M src/southbridge/intel/bd82x6x/reset.c
M src/southbridge/intel/fsp_bd82x6x/reset.c
M src/southbridge/intel/fsp_i89xx/reset.c
M src/southbridge/intel/fsp_rangeley/reset.c
M src/southbridge/intel/i3100/reset.c
M src/southbridge/intel/i82801ax/reset.c
M src/southbridge/intel/i82801bx/reset.c
M src/southbridge/intel/i82801dx/reset.c
M src/southbridge/intel/i82801ex/reset.c
M src/southbridge/intel/i82801gx/reset.c
M src/southbridge/intel/lynxpoint/reset.c
M src/southbridge/nvidia/ck804/early_setup.c
M src/southbridge/nvidia/ck804/early_setup_car.c
M src/southbridge/nvidia/ck804/reset.c
M src/southbridge/nvidia/mcp55/early_ctrl.c
M src/southbridge/nvidia/mcp55/reset.c
M src/southbridge/sis/sis966/early_ctrl.c
M src/southbridge/sis/sis966/reset.c
68 files changed, 183 insertions(+), 147 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/19789/4
--
To view, visit https://review.coreboot.org/19789
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f
Gerrit-PatchSet: 4
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Julius Werner has posted comments on this change. ( https://review.coreboot.org/19789 )
Change subject: Consolidate reset API, add generic reset_prepare mechanism
......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/19789/3/src/include/reset.h
File src/include/reset.h:
PS3, Line 12: /* SoC reset. Resets CPU and possibly some but not all IPs. */
> I think this is a confusing one in that it's not even really a reset on x86
Yeah, it looks like it's actually not used anywhere. I'll take it out.
--
To view, visit https://review.coreboot.org/19789
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: comment
Gerrit-Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f
Gerrit-PatchSet: 3
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-HasComments: Yes
Julius Werner has posted comments on this change. ( https://review.coreboot.org/19785 )
Change subject: arm64: Align cache maintenance code with libpayload and ARM32
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/19785/1/src/arch/arm64/armv8/cache.c
File src/arch/arm64/armv8/cache.c:
Line 126: else if (sctlr & SCTLR_I)
> But isn't that happening with clean_invalidate_all() as well with the scena
> Or did you mean that since there are lines fetched from the instruction fetch sitting in l2 the caches need to be invalided to pick up the new instructions sitting in ram at the same address?
Yes, the invalidate is the important part so that instruction fetches see the new code that's only in RAM. Honestly, I'm not sure why this is clean_invalidate instead of just invalidate... it probably doesn't make a difference because without data caching the cache lines couldn't become dirty anyways, so the clean might be a no-op. This is just what the Qualcomm guy uploaded back then and said fixes the issue on his board that I don't have, so I'd rather unify the implementations on that now and it can still be revisited if we find issues with it in the future.
--
To view, visit https://review.coreboot.org/19785
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: comment
Gerrit-Change-Id: I9e05b425eeeaa27a447b37f98c0928fed3f74340
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-HasComments: Yes
Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/19787 )
Change subject: arch/x86: Add function to determine if we're currently running from CAR
......................................................................
Patch Set 2: Code-Review+1
--
To view, visit https://review.coreboot.org/19787
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: comment
Gerrit-Change-Id: Ib7ad0896a691ef6e89e622b985417fedc43579c1
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-HasComments: No
Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/19788 )
Change subject: arch: Unify basic cache clearing API
......................................................................
Patch Set 3: Code-Review+1
--
To view, visit https://review.coreboot.org/19788
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: comment
Gerrit-Change-Id: I2c1723a287f76cd4118ef38a445339840601aeea
Gerrit-PatchSet: 3
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-HasComments: No