coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

1 participants
3888 discussions

Change in seabios[master]: hw/nvme: Enable NVMe support for non-qemu hardware
by Matt DeVillier (Code Review) 26 May '17

26 May '17

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/19443 ) Change subject: hw/nvme: Enable NVMe support for non-qemu hardware ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/19443 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I9d8a30f93462eb1b2838eb72524b498566af35bb Gerrit-PatchSet: 2 Gerrit-Project: seabios Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-HasComments: No

1 0

Change in coreboot[master]: purism/librem13v2: Add initial directory for librem13 v2
by Matt DeVillier (Code Review) 26 May '17

26 May '17

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/19932 ) Change subject: purism/librem13v2: Add initial directory for librem13 v2 ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/19932 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I24263fde18fcea70163dbdc59df6ea1d98c97af8 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-HasComments: No

1 0

Change in coreboot[master]: purism/librem13v1: Rename librem13 to librem13v1
by Matt DeVillier (Code Review) 26 May '17

26 May '17

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/19931 ) Change subject: purism/librem13v1: Rename librem13 to librem13v1 ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/19931 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I23fa977717230c2001868741bb684e9633a2c0bb Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-HasComments: No

1 0

Change in coreboot[master]: purism/librem13v2: Fix EC_SCI_GPI value
by Youness Alaoui (Code Review) 26 May '17

26 May '17

Hello Matt DeVillier, I'd like you to do a code review. Please visit https://review.coreboot.org/19945 to review the following change. Change subject: purism/librem13v2: Fix EC_SCI_GPI value ...................................................................... purism/librem13v2: Fix EC_SCI_GPI value Existing value was copied from librem13 v1 board, use value obtained from AMI firmware. TEST: Observe Windows boots correctly, function keys work under both Windows and Linux. Change-Id: I0ea6cc4602ce1047cb803acc65cbca1af1f480b0 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/purism/librem13v2/acpi/ec.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/19945/1 diff --git a/src/mainboard/purism/librem13v2/acpi/ec.asl b/src/mainboard/purism/librem13v2/acpi/ec.asl index cf8b9a9..4215213 100644 --- a/src/mainboard/purism/librem13v2/acpi/ec.asl +++ b/src/mainboard/purism/librem13v2/acpi/ec.asl @@ -13,6 +13,6 @@ * GNU General Public License for more details. */ -#define EC_SCI_GPI 10 +#define EC_SCI_GPI 0x50 #include <ec/purism/librem/acpi/ec.asl> -- To view, visit https://review.coreboot.org/19945 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I0ea6cc4602ce1047cb803acc65cbca1af1f480b0 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: purism/librem13v2: Fix HDA verb values, use azalia macros
by Youness Alaoui (Code Review) 26 May '17

26 May '17

Hello Matt DeVillier, I'd like you to do a code review. Please visit https://review.coreboot.org/19944 to review the following change. Change subject: purism/librem13v2: Fix HDA verb values, use azalia macros ...................................................................... purism/librem13v2: Fix HDA verb values, use azalia macros Use verb table values from AMI firmware, consolidate NID definitions using azalia macros. Fixes headphone jack detection and microphone. Change-Id: Ia31be6efc7afe921ad91b400f66694d951f0a260 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/purism/librem13v2/hda_verb.h 1 file changed, 13 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/19944/1 diff --git a/src/mainboard/purism/librem13v2/hda_verb.h b/src/mainboard/purism/librem13v2/hda_verb.h index a2984f0..660ad0c 100644 --- a/src/mainboard/purism/librem13v2/hda_verb.h +++ b/src/mainboard/purism/librem13v2/hda_verb.h @@ -35,72 +35,39 @@ /* Bits 7:0 - Payload */ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x19910269 */ - 0x00172069, - 0x00172102, - 0x00172291, - 0x00172319, + AZALIA_SUBVENDOR(0x0, 0x19910269), /* Pin Widget Verb Table */ /* Pin Complex (NID 0x12) */ - 0x01271c00, - 0x01271d00, - 0x01271e00, - 0x01271f40, + AZALIA_PIN_CFG(0x0, 0x12, 0x40000000), /* Pin Complex (NID 0x14) */ - 0x01471c10, - 0x01471d01, - 0x01471e17, - 0x01471f90, + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + + /* Pin Complex (NID 0x15) */ + AZALIA_PIN_CFG(0x0, 0x15, 0x04214020), /* Pin Complex (NID 0x17) */ - 0x01771cf0, - 0x01771d11, - 0x01771e11, - 0x01771f41, + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), /* Pin Complex (NID 0x18) */ - 0x01871c20, - 0x01871d10, - 0x01871ea1, - 0x01871f04, + AZALIA_PIN_CFG(0x0, 0x18, 0x04a19040), /* Pin Complex (NID 0x19) */ - 0x01971c30, - 0x01971d01, - 0x01971ea7, - 0x01971f90, + AZALIA_PIN_CFG(0x0, 0x19, 0x90a70130), /* Pin Complex (NID 0x1A) */ - 0x01a71cf0, - 0x01a71d11, - 0x01a71e11, - 0x01a71f41, + AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0), /* Pin Complex (NID 0x1B) */ - 0x01b71cf0, - 0x01b71d11, - 0x01b71e11, - 0x01b71f41, + AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0), /* Pin Complex (NID 0x1D) */ - 0x01d71c05, - 0x01d71d9d, - 0x01d71e56, - 0x01d71f40, + AZALIA_PIN_CFG(0x0, 0x1D, 0x40548505), /* Pin Complex (NID 0x1E) */ - 0x01e71cf0, - 0x01e71d11, - 0x01e71e11, - 0x01e71f41, - - /* Pin Complex (NID 0x21) */ - 0x02171c1f, - 0x02171d10, - 0x02171e21, - 0x02171f04, + AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0), }; const u32 pc_beep_verbs[] = { -- To view, visit https://review.coreboot.org/19944 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ia31be6efc7afe921ad91b400f66694d951f0a260 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: purism/librem13v2: Add audio support
by Youness Alaoui (Code Review) 26 May '17

26 May '17

Hello Matt DeVillier, I'd like you to do a code review. Please visit https://review.coreboot.org/19943 to review the following change. Change subject: purism/librem13v2: Add audio support ...................................................................... purism/librem13v2: Add audio support Initialize the audio codec without depending on DSP binary blobs. The hda_verb.c was copied from the intel/kblrvp rvp7 variant, and the hda_verb.h file was copied from the purism/librem13. The IoBufferOwnership FSP option in devicetree has to be 0 for the azalia driver to work. Change-Id: Ifa36ac0839daedfa59c497057da0ace04d401f2a Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/purism/librem13v2/Kconfig M src/mainboard/purism/librem13v2/Makefile.inc M src/mainboard/purism/librem13v2/devicetree.cb A src/mainboard/purism/librem13v2/hda_verb.c A src/mainboard/purism/librem13v2/hda_verb.h D src/mainboard/purism/librem13v2/mainboard.c 6 files changed, 195 insertions(+), 74 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/19943/1 diff --git a/src/mainboard/purism/librem13v2/Kconfig b/src/mainboard/purism/librem13v2/Kconfig index 75d3009..fff0256 100644 --- a/src/mainboard/purism/librem13v2/Kconfig +++ b/src/mainboard/purism/librem13v2/Kconfig @@ -4,8 +4,6 @@ def_bool y select SYSTEM_TYPE_LAPTOP select BOARD_ROMSIZE_KB_16384 - select DRIVERS_I2C_GENERIC - select DRIVERS_I2C_NAU8825 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MONOTONIC_TIMER_MSR diff --git a/src/mainboard/purism/librem13v2/Makefile.inc b/src/mainboard/purism/librem13v2/Makefile.inc index 6c8f38c..eb01360 100644 --- a/src/mainboard/purism/librem13v2/Makefile.inc +++ b/src/mainboard/purism/librem13v2/Makefile.inc @@ -15,7 +15,7 @@ romstage-y += pei_data.c -ramstage-y += mainboard.c ramstage-y += pei_data.c ramstage-y += ramstage.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb index f345c09..e113b3f 100644 --- a/src/mainboard/purism/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem13v2/devicetree.cb @@ -34,8 +34,8 @@ register "SataPortsEnable[0]" = "1" register "SataPortsEnable[2]" = "1" register "EnableAzalia" = "1" - register "DspEnable" = "1" - register "IoBufferOwnership" = "3" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" register "EnableTraceHub" = "0" register "XdciEnable" = "0" register "SsicPortEnable" = "0" diff --git a/src/mainboard/purism/librem13v2/hda_verb.c b/src/mainboard/purism/librem13v2/hda_verb.c new file mode 100644 index 0000000..e8eecdf --- /dev/null +++ b/src/mainboard/purism/librem13v2/hda_verb.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * (Written by Naresh G Solanki <naresh.solanki(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <chip.h> +#include <console/console.h> +#include <device/azalia_device.h> +#include <soc/intel/common/hda_verb.h> +#include <soc/pci_devs.h> + +#include "hda_verb.h" + +static void codecs_init(u8 *base, u32 codec_mask) +{ + int i; + + /* Can support up to 4 codecs */ + for (i = 3; i >= 0; i--) { + if (codec_mask & (1 << i)) + hda_codec_init(base, i, cim_verb_data_size, + cim_verb_data); + } + + if (pc_beep_verbs_size) + hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs); +} + +static void mb_hda_codec_init(void *unused) +{ + static struct soc_intel_skylake_config *config; + u8 *base; + struct resource *res; + u32 codec_mask; + struct device *dev; + + dev = SA_DEV_ROOT; + /* Check if HDA is enabled, else return */ + if (dev == NULL || dev->chip_info == NULL) + return; + + config = dev->chip_info; + + /* + * IoBufferOwnership 0:HD-A Link, 1:Shared HD-A Link and I2S Port, + * 3:I2S Ports. In HDA mode where codec need to be programmed with + * verb table + */ + if (config->IoBufferOwnership == 3) + return; + + /* Find base address */ + dev = dev_find_slot(0, PCH_DEVFN_HDA); + if (dev == NULL) + return; + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + + base = res2mmio(res, 0, 0); + printk(BIOS_DEBUG, "HDA: base = %p\n", base); + + codec_mask = hda_codec_detect(base); + + if (codec_mask) { + printk(BIOS_DEBUG, "HDA: codec_mask = %02x\n", codec_mask); + codecs_init(base, codec_mask); + } +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, mb_hda_codec_init, NULL); diff --git a/src/mainboard/purism/librem13v2/hda_verb.h b/src/mainboard/purism/librem13v2/hda_verb.h new file mode 100644 index 0000000..a2984f0 --- /dev/null +++ b/src/mainboard/purism/librem13v2/hda_verb.h @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */ + 0x19910269, /* Subsystem ID */ + 0x0000000c, /* Number of jacks (NID entries) */ + + 0x0017ff00, /* Function Reset */ + 0x0017ff00, /* Double Function Reset */ + 0x0017ff00, + 0x0017ff00, + + /* Bits 31:28 - Codec Address */ + /* Bits 27:20 - NID */ + /* Bits 19:8 - Verb ID */ + /* Bits 7:0 - Payload */ + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x19910269 */ + 0x00172069, + 0x00172102, + 0x00172291, + 0x00172319, + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x12) */ + 0x01271c00, + 0x01271d00, + 0x01271e00, + 0x01271f40, + + /* Pin Complex (NID 0x14) */ + 0x01471c10, + 0x01471d01, + 0x01471e17, + 0x01471f90, + + /* Pin Complex (NID 0x17) */ + 0x01771cf0, + 0x01771d11, + 0x01771e11, + 0x01771f41, + + /* Pin Complex (NID 0x18) */ + 0x01871c20, + 0x01871d10, + 0x01871ea1, + 0x01871f04, + + /* Pin Complex (NID 0x19) */ + 0x01971c30, + 0x01971d01, + 0x01971ea7, + 0x01971f90, + + /* Pin Complex (NID 0x1A) */ + 0x01a71cf0, + 0x01a71d11, + 0x01a71e11, + 0x01a71f41, + + /* Pin Complex (NID 0x1B) */ + 0x01b71cf0, + 0x01b71d11, + 0x01b71e11, + 0x01b71f41, + + /* Pin Complex (NID 0x1D) */ + 0x01d71c05, + 0x01d71d9d, + 0x01d71e56, + 0x01d71f40, + + /* Pin Complex (NID 0x1E) */ + 0x01e71cf0, + 0x01e71d11, + 0x01e71e11, + 0x01e71f41, + + /* Pin Complex (NID 0x21) */ + 0x02171c1f, + 0x02171d10, + 0x02171e21, + 0x02171f04, +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; +#endif diff --git a/src/mainboard/purism/librem13v2/mainboard.c b/src/mainboard/purism/librem13v2/mainboard.c deleted file mode 100644 index fae2889..0000000 --- a/src/mainboard/purism/librem13v2/mainboard.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <console/console.h> -#include <device/device.h> -#include <stdlib.h> -#include <soc/nhlt.h> - -static unsigned long mainboard_write_acpi_tables( - device_t device, unsigned long current, acpi_rsdp_t *rsdp) -{ - uintptr_t start_addr; - uintptr_t end_addr; - struct nhlt *nhlt; - - start_addr = current; - - nhlt = nhlt_init(); - - if (nhlt == NULL) - return start_addr; - - /* 2 Channel DMIC array. */ - if (nhlt_soc_add_dmic_array(nhlt, 2)) - printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); - - /* ADI Smart Amps for left and right. */ - if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0)) - printk(BIOS_ERR, "Couldn't add ssm4567.\n"); - - /* NAU88l25 Headset codec. */ - if (nhlt_soc_add_nau88l25(nhlt, AUDIO_LINK_SSP1)) - printk(BIOS_ERR, "Couldn't add headset codec.\n"); - - end_addr = nhlt_soc_serialize(nhlt, start_addr); - - if (end_addr != start_addr) - acpi_add_table(rsdp, (void *)start_addr); - - return end_addr; -} - -/* - * mainboard_enable is executed as first thing after - * enumerate_buses(). - */ -static void mainboard_enable(device_t dev) -{ - dev->ops->write_acpi_tables = mainboard_write_acpi_tables; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; -- To view, visit https://review.coreboot.org/19943 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ifa36ac0839daedfa59c497057da0ace04d401f2a Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: purism/librem13v2: Add Kconfig defaults
by Youness Alaoui (Code Review) 26 May '17

26 May '17

Youness Alaoui has uploaded a new change for review. ( https://review.coreboot.org/19942 ) Change subject: purism/librem13v2: Add Kconfig defaults ...................................................................... purism/librem13v2: Add Kconfig defaults Add default values for MAINBOARD_VERSION, FSP_IMAGE_ID_STRING, and CBFS_SIZE. Change-Id: Ib6461cef78f3fea448baf1ada456e3c8335f1543 Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> --- M src/mainboard/purism/librem13v2/Kconfig 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/19942/1 diff --git a/src/mainboard/purism/librem13v2/Kconfig b/src/mainboard/purism/librem13v2/Kconfig index 39866e1..75d3009 100644 --- a/src/mainboard/purism/librem13v2/Kconfig +++ b/src/mainboard/purism/librem13v2/Kconfig @@ -29,6 +29,10 @@ string default "Librem 13 v2" +config MAINBOARD_VERSION + string + default "2.0" + config MAINBOARD_DIR string default "purism/librem13v2" @@ -55,6 +59,10 @@ int default 512 +config FSP_IMAGE_ID_STRING + string + default "$SKLFSP$" + config CPU_MICROCODE_CBFS_LEN hex default 0x17800 @@ -63,4 +71,8 @@ hex default 0xFFE115A0 +config CBFS_SIZE + hex + default 0x5c0000 + endif -- To view, visit https://review.coreboot.org/19942 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ib6461cef78f3fea448baf1ada456e3c8335f1543 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com>

1 0

Change in coreboot[master]: purism/librem13v2: Clean up devicetree
by Youness Alaoui (Code Review) 26 May '17

26 May '17

Hello Matt DeVillier, I'd like you to do a code review. Please visit https://review.coreboot.org/19941 to review the following change. Change subject: purism/librem13v2: Clean up devicetree ...................................................................... purism/librem13v2: Clean up devicetree - remove unused I2C, serialIO defs - set PL2 override, VR mailbox cmd based on SKL-U ref board, as values copied from google/chell are for SKL-Y Change-Id: I3a138c28d0322df6cb41ec1a845ae31602cb69a7 Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/purism/librem13v2/devicetree.cb 1 file changed, 4 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/19941/1 diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb index 0defea0..f345c09 100644 --- a/src/mainboard/purism/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem13v2/devicetree.cb @@ -165,30 +165,11 @@ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right) register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + # PL2 override 25W + register "tdp_pl2_override" = "25" - # Must leave UART0 enabled or SD/eMMC will not work as PCI - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, - [PchSerialIoIndexUart0] = PchSerialIoPci, - [PchSerialIoIndexUart1] = PchSerialIoDisabled, - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, - }" - - # PL2 override 15W - register "tdp_pl2_override" = "15" - - register "tcc_offset" = "10" # TCC of 90C - - # Send an extra VR mailbox command for the supported MPS IMVP8 model - register "SendVrMbxCmd" = "1" + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" device cpu_cluster 0 on device lapic 0 on end -- To view, visit https://review.coreboot.org/19941 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I3a138c28d0322df6cb41ec1a845ae31602cb69a7 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: purism/librem13v2: Update USB config
by Youness Alaoui (Code Review) 26 May '17

26 May '17

Hello Matt DeVillier, I'd like you to do a code review. Please visit https://review.coreboot.org/19940 to review the following change. Change subject: purism/librem13v2: Update USB config ...................................................................... purism/librem13v2: Update USB config Update devicetree USB config based on board spec. Leave OC pins set to skip since info unavailable. Change-Id: I2a4fe17ed7edacbbbaf56969f9d2801b45a20da9 Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/purism/librem13v2/devicetree.cb 1 file changed, 7 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/19940/1 diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb index ffd33a2..0defea0 100644 --- a/src/mainboard/purism/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem13v2/devicetree.cb @@ -155,17 +155,15 @@ # ClkReq for NVMe - Bruteforced (no other value works) register "PcieRpClkReqNumber[8]" = "2" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_LONG(OC3)" # Type-C Port 2 + register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" # Type-C Port + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # SD + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left) + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # SD - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V -- To view, visit https://review.coreboot.org/19940 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I2a4fe17ed7edacbbbaf56969f9d2801b45a20da9 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: purism/librem13v2: Update PCI config
by Youness Alaoui (Code Review) 26 May '17

26 May '17

Hello Matt DeVillier, I'd like you to do a code review. Please visit https://review.coreboot.org/19939 to review the following change. Change subject: purism/librem13v2: Update PCI config ...................................................................... purism/librem13v2: Update PCI config Update devicetree PCI config based on board spec: - enable PCIe Root Ports 5 and 9 (wifi and nvme respectively) - enable PCIe CLKREQ on RP9, disable on RP5 - enable USB OTG - enable P2SB Note: PCIe RP5 is on 0.1c.0 despite this being labeled as RP1 Change-Id: Ia71ed25bd41668df1ee3e4b4e28f54482722452c Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/purism/librem13v2/devicetree.cb 1 file changed, 11 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/19939/1 diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb index 8f8dc92..ffd33a2 100644 --- a/src/mainboard/purism/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem13v2/devicetree.cb @@ -147,12 +147,13 @@ .voltage_limit = 1520, }" - # Enable Root port 1. - register "PcieRpEnable[0]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[0]" = "1" - # RP 1 uses SRCCLKREQ1# - register "PcieRpClkReqNumber[0]" = "1" + # Enable Root Ports 5 and 9 + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[8]" = "1" + # Enable CLKREQ# for RP9 + register "PcieRpClkReqSupport[8]" = "1" + # ClkReq for NVMe - Bruteforced (no other value works) + register "PcieRpClkReqNumber[8]" = "2" register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_LONG(OC3)" # Type-C Port 2 @@ -198,7 +199,7 @@ device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) + device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 @@ -206,12 +207,7 @@ device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 on end # SATA - device pci 1c.0 on - chip drivers/intel/wifi - register "wake" = "GPE0_DW0_16" - device pci 00.0 on end - end - end # PCI Express Port 1 + device pci 1c.0 on end # PCI Express Port 1 device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 @@ -219,7 +215,7 @@ device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.0 on end # PCI Express Port 9 device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 @@ -228,7 +224,7 @@ device pnp 0c09.0 on end end end # LPC Interface - device pci 1f.1 off end # P2SB + device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus -- To view, visit https://review.coreboot.org/19939 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ia71ed25bd41668df1ee3e4b4e28f54482722452c Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2017