Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19442 )
Change subject: soc/intel/skylake: Set xtal bypass on low power idle
......................................................................
soc/intel/skylake: Set xtal bypass on low power idle
When using Wake On Voice &/or DCI, it requires xtal to be active during
low power idle.
With xtal being active in S0ix state power impact is 1-2 mW.
Hence set xtal bypass bit in CIR31C for low power idle entry.
TEST= Build with s0ix enable for Poppy. Boot to OS & verify that
bit 22 of CIR31C register is set. s0ix works.
Change-Id: Ide2d01536f652cd1b0ac32eede89ec410c5101cf
Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com>
Reviewed-on: https://review.coreboot.org/19442
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
---
M src/soc/intel/skylake/finalize.c
M src/soc/intel/skylake/include/soc/pmc.h
2 files changed, 9 insertions(+), 1 deletion(-)
Approvals:
Aaron Durbin: Looks good to me, approved
build bot (Jenkins): Verified
Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index f489e4b..9cb246c 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -143,6 +143,13 @@
write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
}
+ /* Disable XTAL shutdown qualification for low power idle. */
+ if (config->s0ix_enable) {
+ reg32 = read32(pmcbase + CIR31C);
+ reg32 |= XTALSDQDIS;
+ write32(pmcbase + CIR31C, reg32);
+ }
+
/* we should disable Heci1 based on the devicetree policy */
if (config->HeciEnabled == 0)
pch_disable_heci();
diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h
index 10ea6ae..4a80917 100644
--- a/src/soc/intel/skylake/include/soc/pmc.h
+++ b/src/soc/intel/skylake/include/soc/pmc.h
@@ -98,5 +98,6 @@
#define GPE0_DW2_SHIFT 8
#define GBLRST_CAUSE0 0x124
#define GBLRST_CAUSE1 0x128
-
+#define CIR31C 0x31c
+#define XTALSDQDIS (1 << 22)
#endif
--
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Gerrit-MessageType: merged
Gerrit-Change-Id: Ide2d01536f652cd1b0ac32eede89ec410c5101cf
Gerrit-PatchSet: 8
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Gerrit-Reviewer: Roy Park <roy.mingi.park(a)intel.corp-partner.google.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins)
Gerrit-Reviewer: rushikesh s kadam <rushikesh.s.kadam(a)intel.com>
Hello Patrick Rudolph, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19500
to look at the new patch set (#17).
Change subject: nb/intel/gm45: Set display backlight according to EDID string
......................................................................
nb/intel/gm45: Set display backlight according to EDID string
Add some known good values for some thinkpads displays.
Known good means that at this pwm frequency the display is evenly lit
on all duty cycles, the display makes minimal to no noise at lower
duty cycles and the display does not flicker. This values differs from
vendor (which uses an obviously wrong display clock (190MHz instead
of 320MHz) resulting in frequency more than 60% off the intended
value.
TESTED on Thinkpad X200 with edid ascii string in list and removed
from list to see if notice message is shown.
Change-Id: Id7bc0d453fac31e806852206ba2c895720b2c843
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/lenovo/t400/Makefile.inc
A src/mainboard/lenovo/t400/blc.c
M src/mainboard/lenovo/x200/Makefile.inc
A src/mainboard/lenovo/x200/blc.c
M src/mainboard/roda/rk9/Makefile.inc
A src/mainboard/roda/rk9/blc.c
M src/northbridge/intel/gm45/chip.h
M src/northbridge/intel/gm45/gm45.h
M src/northbridge/intel/gm45/gma.c
9 files changed, 145 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/19500/17
--
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Id7bc0d453fac31e806852206ba2c895720b2c843
Gerrit-PatchSet: 17
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins)