coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common: Add PCI configuration code for UART
by build bot (Jenkins) (Code Review) 02 May '17

02 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19490 ) Change subject: soc/intel/common: Add PCI configuration code for UART ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53074/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/8910/ : SUCCESS -- To view, visit https://review.coreboot.org/19490 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ibce5623ffb879f2427b759106d1f350601837e4b Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Use common/block/uart code
by build bot (Jenkins) (Code Review) 02 May '17

02 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19491 ) Change subject: soc/intel/apollolake: Use common/block/uart code ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53076/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/8912/ : SUCCESS -- To view, visit https://review.coreboot.org/19491 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I92c654d59f1642bcd7c95de80dcc641bf816b542 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Use common/blocks/uart code
by build bot (Jenkins) (Code Review) 02 May '17

02 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19492 ) Change subject: soc/intel/skylake: Use common/blocks/uart code ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53075/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/8911/ : SUCCESS -- To view, visit https://review.coreboot.org/19492 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I53ed687dc49524e001889f091825b2cc530546a3 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Add PCI configuration code for UART
by Aamir Bohra (Code Review) 02 May '17

02 May '17

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/19490 ) Change subject: soc/intel/common: Add PCI configuration code for UART ...................................................................... Patch Set 3: (4 comments) https://review.coreboot.org/#/c/19490/1/src/soc/intel/common/block/uart/uar… File src/soc/intel/common/block/uart/uart.c: Line 23: uint32_t clk_n_val) > You can't have this be a nop. It won't read *any* resources. It needs to ca Ok.Revised implementation in PS#2 PS1, Line 56: /* > space after '*' Done PS1, Line 56: 0xa127, /* KBL-H UART0 */ : 0xa128, /* KBL-H UART1 */ : 0xa166, /* KBL-H UART2 */ : 0x5abc, /* Apollolake UART0 */ : 0x5abe, /* Apollolake UART1 */ : 0x5ac0, /* Apollolake UART2 */ : 0x5aee, /* Apollolake UART3 */ : 0x31bc, /* GLK UART0 */ : 0x31be, /* GLK UART1 */ : 0x31c0, /* GLK UART2 */ : 0x31ee, /* GLK UART3 */ : }; : : static const struct pci_ > These should be put into pci_ids.h then. Ok.Do you suggest to move it to soc/pci_ids.h or define it under common? Line 75 > seems like tabs and spaces are being mixed between .field and = Done -- To view, visit https://review.coreboot.org/19490 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ibce5623ffb879f2427b759106d1f350601837e4b Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/skylake: Use intel/common/block/smbus code
by build bot (Jenkins) (Code Review) 02 May '17

02 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19373 ) Change subject: soc/intel/skylake: Use intel/common/block/smbus code ...................................................................... Patch Set 9: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53071/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/8907/ : SUCCESS -- To view, visit https://review.coreboot.org/19373 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I2ca32ab594552424e4f1358302641f159a3d7e62 Gerrit-PatchSet: 9 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: Add Intel common SMBus code
by build bot (Jenkins) (Code Review) 02 May '17

02 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19372 ) Change subject: soc/intel/common/block: Add Intel common SMBus code ...................................................................... Patch Set 8: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53073/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/8909/ : SUCCESS -- To view, visit https://review.coreboot.org/19372 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I936143a334c31937d557c6828e5876d35b133567 Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Add PCI configuration code for UART
by build bot (Jenkins) (Code Review) 02 May '17

02 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19490 ) Change subject: soc/intel/common: Add PCI configuration code for UART ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/53072/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/8908/ : SUCCESS -- To view, visit https://review.coreboot.org/19490 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ibce5623ffb879f2427b759106d1f350601837e4b Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Add PCI configuration code for UART
by Aamir Bohra (Code Review) 02 May '17

02 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19490 to look at the new patch set (#3). Change subject: soc/intel/common: Add PCI configuration code for UART ...................................................................... soc/intel/common: Add PCI configuration code for UART Add PCI configuration code support for intel/common/ block/uart module. Change-Id: Ibce5623ffb879f2427b759106d1f350601837e4b Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/uart/Makefile.inc M src/soc/intel/common/block/uart/uart.c 3 files changed, 45 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/19490/3 -- To view, visit https://review.coreboot.org/19490 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ibce5623ffb879f2427b759106d1f350601837e4b Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: soc/intel/common: Add PCI configuration code for UART
by Aamir Bohra (Code Review) 02 May '17

02 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19490 to look at the new patch set (#2). Change subject: soc/intel/common: Add PCI configuration code for UART ...................................................................... soc/intel/common: Add PCI configuration code for UART Add PCI configuration code support for intel/common/ block/uart module. Change-Id: Ibce5623ffb879f2427b759106d1f350601837e4b Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/uart/Makefile.inc M src/soc/intel/common/block/uart/uart.c 3 files changed, 45 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/19490/2 -- To view, visit https://review.coreboot.org/19490 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ibce5623ffb879f2427b759106d1f350601837e4b Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: soc/intel/skylake: Use intel/common/block/smbus code
by build bot (Jenkins) (Code Review) 02 May '17

02 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19373 ) Change subject: soc/intel/skylake: Use intel/common/block/smbus code ...................................................................... Patch Set 8: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53068/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/8904/ : SUCCESS -- To view, visit https://review.coreboot.org/19373 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I2ca32ab594552424e4f1358302641f159a3d7e62 Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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coreboot-gerrit May 2017